OpenBench Logic Sniffer is an open source logic analyzer hardware design.

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jason p

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Mar 1, 2010, 2:42:25 PM3/1/10
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just came across this ,  thought might be of interest to the group !

http://www.gadgetfactory.net/gf/project/butterflylogic/

OpenBench Logic Sniffer is an open source logic analyzer hardware design. It’s purpose is to provide a hardware platform for the SUMP logic analyzer at the lowest possible cost.

This project started in the comments on a post. Initial circuit design, PCB layout, development, and testing continued in the forum under the code name Project SUMP PUMP. Many, many people contributed ideas and advice, the Gadget Factory and Dangerous Prototypes coordinated circuit development and routed the PCB. We borrowed heavily from the Gadget Factory's Butterfly Platform.

The OpenBench Logic Sniffer is a purpose-built logic analyzer board designed to be low cost but high speed. It sacrifices a lot of the features you’d look for in a full-scale FPGA development board to achieve our primary goals:

  • 70MHz+ sample speeds
  • 32 channels
  • 16 buffered, 5volt tolerant channels
  • USB interface, USB powered
  • USB upgradable everything
  • Make it as DIY as possible
  • Make it as open source as possible
  • $30-$40 price range

We didn’t quite hit our initial price range, but we got really close.

You can get your own assembled Open Logic Sniffer at Seeed Studio for $45, including worldwide shipping. 

Block Diagram

UART Demo Video

 

  

Features

  • Capture 50MHz+ waveforms on 32 channels
    • 200Msps captures up to 100MHz waveforms on 16 channels
    • 100Msps captures up to 50MHz waveforms on 32 channels
  • 16 buffered channels, 5volt tolerant
  • 216K Block RAM supports following memory configurations*
    • 8 channels with 24K sample depth
    • 16 channels with 12K sample depth
    • 32 channels with 6K sample depth
  • External clock and trigger input
    • Allows interfacing with external test equipment and daisy chaining OLS's for additional channels.
  • Internal clock and trigger output
  • 16bit wing expansion header
  • USB interface, USB powered
  • USB upgradable everything
  • Designed for the SUMP logic analyzer client
  • Open source
  • Low price
 

 

Quick Links
 

   

Sources and Attribution

  • Michael Poppitz was the original author of this great Logic Analyzer design. He wrote the original VHDL and Java client and released it GPL at http://www.sump.org/projects/analyzer/. Please visit his website for more information.
  • Jonas Diemer took the original design and ported it to the Spartan 3E by utilizing BRAM instead of SRAM he also integrated a RLE into the design. His source can be downloaded here.
  • The very latest development for the Java client is hosted on SourceForge here.
  • OakMicros has created a very nice tutorial for the Java client here.
 

 

Pictures


 

 

This open source hardware and software is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. If you can't accept this risk, please do not buy this hardware.

 




Christopher Cprek

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Mar 1, 2010, 4:01:40 PM3/1/10
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I saw that on hackaday today and really want it. I'm not going to do a pre-order though. I want to see some reviews first.

/Chris
CTotCW LVL1


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Brian Wagner

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Mar 1, 2010, 8:07:06 PM3/1/10
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I want one of the DSO Nanos that Seeed sells.  Sold Out though...I will have to wait.
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