[LLVMdev] FPU cannot be compatible with -soft-float code on mips by llc

[刘亚龙]

Hi all,

    -soft-float can not be rightly use by llc. All float function operation will call soft float, but not hard.

    My mips device cannot support half float type, so I hack the llvm, and add soft half float and add -soft-float option.

    I add the function define for __gnu_f2h_ieee() and __gnu_h2f_ieee (), and it can call the soft half float.

    However, all the others function about float also call the soft float, how I do make only __gnu_f2h_ieee() use soft float, other use hard float???

    Thank you all !!

Cheers, 

    Robin

[Jim Grosbach]

Hi Robin,

It sounds like you want to support half (f16 in LLVM terms) as a storage only interchange format. AArch64 and X86 (among others) do the same thing. You shouldn’t need the “-soft-float” option or anything of that nature at all. That, as you’ve found, disables all hard float operations. There’s been some recent cleanup in how this is handled in LLVM that should help guide you in what the Mips backend needs to do. In particular, Tim Northover’s recent patch, r213374.

Regards,

  Jim

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[Tim Northover]

On 25 July 2014 18:50, Jim Grosbach <gros...@apple.com> wrote:
> It sounds like you want to support half (f16 in LLVM terms) as a storage
> only interchange format. AArch64 and X86 (among others) do the same thing.
> You shouldn’t need the “-soft-float” option or anything of that nature at
> all. That, as you’ve found, disables all hard float operations. There’s been
> some recent cleanup in how this is handled in LLVM that should help guide
> you in what the Mips backend needs to do. In particular, Tim Northover’s
> recent patch, r213374.

As well as what's in that commit, you probably want to mark
ISD::FP16_TO_FP and ISD::FP_TO_FP16 as "Expand" in
MipsISelLowering.cpp. Then your implementations of "__gnu_..." should
be called for fp16 conversions, but not normal floating point
arithmetic.

Cheers.

Tim.

[Robin Lau]

Hi Tim,
   I already have done your words.  But I don't know how to only fp16, no others floating point.

 

---

liuyalo...@gmail.com

 

From: Tim Northover

Date: 2014-07-25 11:17

To: 刘亚龙

CC: LLVM Developers Mailing List; Jim Grosbach

Subject: Re: [LLVMdev] FPU cannot be compatible with -soft-float code on mips by llc

On 25 July 2014 18:50, Jim Grosbach <gros...@apple.com> wrote:

> It sounds like you want to support half (f16 in LLVM terms) as a storage

> only interchange format. AArch64 and X86 (among others) do the same thing.

> You shouldn’t need the “-soft-float” option or anything of that nature at

> all. That, as you’ve found, disables all hard float operations. There’s been

> some recent cleanup in how this is handled in LLVM that should help guide

> you in what the Mips backend needs to do. In particular, Tim Northover’s

> recent patch, r213374.

 

[刘亚龙]

Hi Jim,

    X86 and ARM have the assembly instruction convert float to half/covert half to float, so they need not to call libcall, but MIPS have not.  So we must add -soft-float option. The terrible thing is all function will be using soft, not FPU (hard).

Cheers,

Robin

---

liuyalo...@gmail.com

  

From: Jim Grosbach

Date: 2014-07-25 10:50

To: 刘亚龙

CC: llvmdev

Subject: Re: [LLVMdev] FPU cannot be compatible with -soft-float code on mips by llc

[Daniel Sanders]

The –soft-float option won't be necessary once FP16_TO_FP and FP_TO_FP16 are set to 'Expand' as Tim suggested. This will cause LLVM to replace these nodes with a libcall while everything else continues to use the hardware support.

 

I believe you need to add these calls to MipsISelLowering.cpp:

setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); // Conversion from half -> float

setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); // Conversion from float -> half

setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); // Conversion from half -> double

setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); // Conversion from double -> half