[llvm-dev] "Bits value must be constants" when generating ISel from Tablegen

[Zhang via llvm-dev]

I had two Instruction class definitions in my InstructionFormat TableGen, as listed below:

```

class InstRI8<bits<8> opcode,string asm,dag outs,dag ins> : Instruction{

  ........

}

class InstRI8222<bits<8> opcode,string asm,dag outs,dag ins,list<dag> Pat> : Instruction{

  ........

  let Pattern = Pat;

}

```

However later when initializing those two classes, if I use the following format to initialize the instruction:

```

def X : InstRI8<...>{

   let Pattern = [ ...... ];

}

```

I got a error from Tablegen that says "Bits value must be constants" for this def.

Using the second Instruction Class which models Pattern as the template argument works perfectly fine

[Paul C. Anagnostopoulos via llvm-dev]

Please post the full definitions of InstRI8 and InstRI8222, along with the full definition of X and the record that inherits from InstRI8222. Then I can reproduce the problem and try to help you.

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[Zhang via llvm-dev]

Hi Paul:

Thanks for the help. I've reduced my test case to the snippet below:

```

class InstTest<bits<8> opcode,string asm,dag outs,dag ins,bits<2> regType> : Instruction{

    bits<8> imm;

    bits<8> dst;

    field bits<32> Inst;

    let Inst{7-0} = imm;

    let Inst{8-15} = dst;

    let OutOperandList = outs;

    let InOperandList = ins;

    let AsmString = asm;

}

class InstTest2<bits<8> opcode,string asm,dag outs,dag ins,bits<2> regType> : Instruction{

    field bits<32> Inst;

    let Inst{7-0} = 0b00000000;

    let Inst{8-15} = 0b00000000;

    let OutOperandList = outs;

    let InOperandList = ins;

    let AsmString = asm;

}

def RI : InstTest2<0x1,"test $dst,$imm",(outs GP8:$dst),(ins i8imm:$imm),REB>{

    let Pattern = [(set GP8:$dst,(i8 imm:$imm))];

}

```

Test2 works but InstTest doesn't. It seems the mere presence of the two bits<8> field causes this issue

 

 

------------------ Original ------------------

From:  "llvm-dev"<llvm...@lists.llvm.org>;

Date:  Fri, Jan 1, 2021 00:12 AM

To:  "llvm-dev"<llvm...@lists.llvm.org>;

Subject:  Re: [llvm-dev] "Bits value must be constants" when generating ISel from Tablegen

[Paul C. Anagnostopoulos via llvm-dev]

Sorry, which TableGen backend is processing this?

I will need definitions for GP8 and REB is order to process your example.

At 1/1/2021 10:45 PM, Zhang wrote:
>Hi Paul:
>Thanks for the help. I've reduced my test case to the snippet below:
>```
>class InstTest<bits<8> opcode,string asm,dag outs,dag ins,bits<2> regType> : Instruction{
> bits<8> imm;
> bits<8> dst;
> field bits<32> Inst;
> let Inst{7-0} = imm;
> let Inst{8-15} = dst;
> let OutOperandList = outs;
> let InOperandList = ins;
> let AsmString = asm;
>}
>class InstTest2<bits<8> opcode,string asm,dag outs,dag ins,bits<2> regType> : Instruction{
> field bits<32> Inst;
> let Inst{7-0} = 0b00000000;
> let Inst{8-15} = 0b00000000;
> let OutOperandList = outs;
> let InOperandList = ins;
> let AsmString = asm;
>}
>def RI : InstTest2<0x1,"test $dst,$imm",(outs GP8:$dst),(ins i8imm:$imm),REB>{
> let Pattern = [(set GP8:$dst,(i8 imm:$imm))];
>}
>```
>
>Test2 works but InstTest doesn't. It seems the mere presence of the two bits<8> field causes this issue

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