[llvm-dev] Llvm-mca library.
lorenzo chelini via llvm-dev
Shoaib Meenai via llvm-dev
(Adding Matt Davis, who should be able to help out here.)
Matt Davis via llvm-dev
Hi Lorenzo,
I’ll answer the first question you have:
> I would like to use llvm-mca to estimate the IPC of a given code region. I am interested in the library version (https://reviews.llvm.org/D50929?id=162210) but I have troubles understanding how to use it. Could you please point me to some documentations or (better) some code examples if any?
The best example of the llvm-mca library being used is the actual llvm-mca tool itself. If you look in llvm/tools/llvm-mca/llvm-mca.cpp you’ll see that it is just a large program that uses the llvm-mca API and library. You’ll want to look at main() where the default pipline is created and the viewers are associated to that pipeline instance.
- You’ll need to construct an mca::Context and use that to create a mca::Pipeline instance. For starters, I suggest just using the default “out-of-order” pipeline. “createDefaultPipeline”
- Next, register some handlers take a look at the HWEventListener class in include/llvm/MCA. Use “Pipeline::addEventListener” to register for the events you might be interested in, such as pipeline stalls.
llvm-mca.cpp does this on behalf of the Viewers. If you trace what the viewers are doing in the source file, you’ll probably
want to do something similar.
- Call “Pipeline::run” to start your experiment and collect performance information.
Your second question:
> Reading the documentation (https://llvm.org/docs/CommandGuide/llvm-mca.html) it also seems that llvm-mca does not take into account the cache hierarchy. Does this mean that the tool assumes all the loads/stores hit the L1 cache?
As you pointed out, MCA does not really model the cache hierarchy. You might want to take a look at the Load/Store unit documentation as well: http://llvm.org/doxygen/classllvm_1_1mca_1_1LSUnit.html
You probably already saw this from the CommandGuide for llvm-mca, but I’ll repeat it here:
“The LSUnit does not attempt to predict if a load or store hits or misses the L1 cache. It only knows if an instruction “MayLoad” and/or “MayStore.” For loads, the scheduling model provides an “optimistic” load-to-use latency (which usually matches the load-to-use latency for when there is a hit in the L1D).”
Hope that helps,
-Matt
Sjoerd Meijer via llvm-dev
Sent: 02 May 2019 19:59
To: Shoaib Meenai; lorenzo chelini; llvm...@lists.llvm.org
Andrea Di Biagio via llvm-dev
I read that out-of-order cores are supported. How about in-order cores? Would it be easy/difficult to add support for that?
Cheers,Sjoerd.
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Sjoerd Meijer via llvm-dev
Sent: 03 May 2019 12:42
To: Sjoerd Meijer
Cc: Shoaib Meenai; lorenzo chelini; llvm...@lists.llvm.org; Matt Davis; nd
Sjoerd Meijer via llvm-dev
To: Sjoerd Meijer
Subject: Re: [llvm-dev] Llvm-mca library.
Hi Andrea,
We have quite a few Arm A-cores and also M-cores that would classify as in-order superscalars. I have been wanting to play with MCA for a while now, but never got round to it. I would be really interested in using it though. Just out of curiousity (I haven't looked much into this), why are the instruction itineraries more important for in-order cores?