[llvm-dev] Writing an LLVM Pass that depends on mem2reg

[Stanislav Manilov via llvm-dev]

Hello,

I am used to specifying dependence on other LLVM passes in the `getAnalysisUsage(AnalysisUsage &)` method of my pass. However, it doesn't seem that there is a header file that exposes the `mem2reg` pass - it is implemented in `Mem2Reg.cpp` as a wrapper.

Is there an easy way to reuse this pass, or should I, in essence, duplicate `Mem2Reg.cpp` in my project?

Cheers,

 - Stan

[Mehdi Amini via llvm-dev]

> On Feb 11, 2016, at 9:49 AM, Stanislav Manilov via llvm-dev <llvm...@lists.llvm.org> wrote:
>
> Hello,
>
> I am used to specifying dependence on other LLVM passes in the `getAnalysisUsage(AnalysisUsage &)` method of my pass. However, it doesn't seem that there is a header file that exposes the `mem2reg` pass - it is implemented in `Mem2Reg.cpp` as a wrapper.

Usually dependencies are expressed toward *analyses* and not toward other transformations.

It is the responsibility of the pass pipeline building to order transformations.

(hope I haven't misunderstood your question)

--
Mehdi

>
> Is there an easy way to reuse this pass, or should I, in essence, duplicate `Mem2Reg.cpp` in my project?
>
> Cheers,
> - Stan

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[Stanislav Manilov via llvm-dev]

Oh, I see, that makes a lot of sense.

How do I build the pass pipeline?

[via llvm-dev]

Hi,
I read your post in LLVM forum. I want to use getAnalysisUsage(AnalysisUsage &AU) to get MachineLoopInfo. I have used this on my passes before but, this time I am trying to get this information in ScheduleDAGRRList scheduler class. There is no runonmachinefunction function. Do you know how I can implement this?
Regards,
Fateme
I will appreciate it you can help me with this problem.
<quote author='Mehdi Amini via llvm-dev'>
Hello,

I am used to specifying dependence on other LLVM passes in the
`getAnalysisUsage(AnalysisUsage &)` method of my pass. However, it doesn't
seem that there is a header file that exposes the `mem2reg` pass - it is
implemented in `Mem2Reg.cpp` as a wrapper.

Is there an easy way to reuse this pass, or should I, in essence, duplicate
`Mem2Reg.cpp` in my project?

Cheers,
- Stan

_______________________________________________
LLVM Developers mailing list
llvm...@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev

</quote>
Quoted from:
http://llvm.1065342.n5.nabble.com/llvm-dev-Writing-an-LLVM-Pass-that-depends-on-mem2reg-tp91085.html

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[Mehdi Amini via llvm-dev]

Hi,

> On Feb 11, 2016, at 10:40 AM, via llvm-dev <llvm...@lists.llvm.org> wrote:
>
> Hi,
> I read your post in LLVM forum. I want to use getAnalysisUsage(AnalysisUsage &AU) to get MachineLoopInfo. I have used this on my passes before but, this time I am trying to get this information in ScheduleDAGRRList scheduler class. There is no runonmachinefunction function. Do you know how I can implement this?

Short answer: you can't, unless I am missing something really obvious.

I'm not sure it even makes sense since this is invoke *during instruction selection*. It means that all the machine basic blocks haven't been created yet. SelectionDAG operates on a single basic block only.
You should step back and think about what you're really trying to achieve here.
If you provide more information on what you're trying to do and why you need this, we may be able to better help to find a solution.

--
Mehdi

[Mehdi Amini via llvm-dev]

It depends how you interact with LLVM, one the command line with `opt` it is the order of the arguments.

Otherwise at the C++ API level it involves creating a PassManager and adding passes to it in order. 

Your pass is surely added to the PassManager at some point, you just have to figure out by which component (again I don't know your project).

-- 

Mehdi

[Stanislav Manilov via llvm-dev]

Okay, so I have to create my own PassManager. I think that answers my question.

Thanks for the help! When I have something useful implemented I'll be happy to share the details.

[Matthias Braun via llvm-dev]

I thinkt MachineLoopInfo requires the program to be in MI representation which it isn't yet when the selection DAG schedulers run. You may be able to hack around that by using the IR level loopinfo and trying to associate that information with the machine basic blocks (though that is probably tricky as well as I think expansion of pseudos may have created additional blocks which are not necessarily present in the IR).

In any way the selection DAG schedulers are usually not the place where you want to do advanced scheduling. The long term plan for the selection dag schedulers is to make them as simple as a reverse postorder walk on the selection DAG (we are not quite there yet) or not require them at all anymore with the upcoming GlobalISel. Scheduling for machine specifics is done with the MachineScheduler infrastructure, have you looked at implementing a pre-ra or post-ra MachineScheduler instead of creating a new ScheduleDAG scheduler?

- Matthias

> On Feb 11, 2016, at 10:40 AM, via llvm-dev <llvm...@lists.llvm.org> wrote:
>

[fateme Hoseini via llvm-dev]

Thank you for your replies. So I guess, the only way to implement this is to create a port-ra MachineScheduler pass. Basically, for my pass I just want to take the result of LLVM scheduler (Sequence vector) and do some modification on the scheduling order of instructions for blocks inside the loops. Therefore, in addition to MachineLoopInfo, I need the sequence of scheduling Units and their relations. Could you please give me a start point on how to include Sunits information in my pass. Is this information from the scheduler still available?

Regards,

Fami