[llvm-dev] scratch register for spill/reload

[David Callahan via llvm-dev]

I have a target architecture with a register class that requires a GPR as a scratch register to implement spill and reload operations. I have experimented with just using a pseudo instruction then scavenging a GPR on demand when that pseudo is lowered but that is not robust. Is there a protocol to allow a point GPR to be allocated when a spill or reload is generated?  

I tried to add a suitable virtual register as an implicit def, but this failed, at least in the fast register allocator, because the generated instruction is apparently not visited. 

My fall back was to add an implicit definition of an ABI defined scratch physical register. That generated incorrect code for some tests with the default allocator. 

How have other targets managed this problem? 

Thanks 

david 

 

[Peter Bergner via llvm-dev]

I can't answer how the ppc backend solves this, but the condition registers and link
register on ppc/ppc64 have no load and store registers, so to spill them, you first
have to copy them to/from a GPR and spill them that way. If this is similar to your
register class limitation, you could see how the ppc backend does this.

Peter
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