[llvm-dev] data flow graph

[huyite via llvm-dev]

Dear all,

      Please help me to generate DFG(Data flow graph) in LLVM.

 

Best regards,

    Huy

 

Mobile: +84942976091

 

[John Criswell via llvm-dev]

Dear Huyite,

Your question, as stated, is too broad to answer.  It would help if your question were more specific; what is it that you want to accomplish?  Are you interested in data flow within SSA virtual registers, or are you interested in data that is stored in memory (which is not in SSA form)?  Are you analyzing code at the LLVM IR level or at the MachineInstr (MI) or MC level?  Are you wanting to print a data-flow graph, or are you developing an analysis that needs to understand a program's data flow in some way?

Without a more specific question, I cannot give a useful answer.

Regards,

John Criswell

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[huyite via llvm-dev]

Dear professor John Criswell

      I would like to implement a new instruction scheduling algorithm so that I need the Data flow graph(DFG) is input of the algorithm.

 

Thanks

   Huy

[John Criswell via llvm-dev]

On 6/18/16 1:38 PM, huyite wrote:

Dear professor John Criswell

      I would like to implement a new instruction scheduling algorithm so that I need the Data flow graph(DFG) is input of the algorithm.

If I understand correctly, you need the data flow graph of the machine instructions, correct?  That would imply that you're analyzing the MachineInstr IR and that you need the data dependencies between machine instructions, correct?

I do not know of a data flow graph analysis at the MI level.  However, we have built a very basic reaching definitions analysis for registers at the MI level for x86 (it might work on other architectures, too, though I'm not sure).  We will be extending it to handle stack locations in the near future.  If this could would help you, please let me know.

Have you looked at LLVM's existing instruction scheduler to see how it handles data dependencies?

Regards,

John Criswell

[huyite via llvm-dev]

Yes, you understand me. I am phd student in university of technology HCM city in Viet Nam, I want to apply new instruction scheduling algorithm for Clustered VLIW architecture. At the moment, I try to find a tool to generate data flow graph(DFG) before implement new algorithm.

 

Thanks for support.