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[PATCH 0/5] KVM: nVMX: Enable nested apicv support.

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Wincy Van

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Jan 16, 2015, 12:50:06 AM1/16/15
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In nested vmx, the efficiency of interrupt virtualization is
very important, especially in high throughput scenes.

This patch set enables nested apicv support, which makes a
huge improvement in nested interrupt virtualization.

I also have done some simple tests:
L0: Intel Xeon E5-2630 v2
L1: CentOS 6.5 with 3.10.64-1.el6.elrepo.x86_64 kernel
16 vcpus, 32GB memory.

L2: Windows Server 2008 R2 Datacenter
8 vcpus, 16GB memory.

1. Run wprime 32M, 8 threads.

original nested apicv

7.782s 7.172s

Improvement: 7.8%

2. Run iperf -s -w 64k in L1,
iperf -c 10.1.0.2 -p 5001 -i 1 -t 30 -P 8 -w 64k in L2

original nested apicv

2.12 Gbits/s 3.50 Gbits/s

Improvement: 65.0%

_________________________________________________________

L2: CentOS 6.5 with 2.6.32-431 kernel
8 vcpus, 16GB memory.

1. Run iperf -s -w 64k in L1,
iperf -c 10.1.0.2 -p 5001 -i 1 -t 30 -P 8 -w 64k in L2

original nested apicv

6.58 Gbits/s 14.2 Gbits/s

Improvement: 115.8%

Wincy Van (5):
KVM: nVMX: Make nested control MSRs per-cpu.
KVM: nVMX: Enable nested virtualize x2apic mode.
KVM: nVMX: Enable nested apic register virtualization.
KVM: nVMX: Enable nested virtual interrupt delivery.
KVM: nVMX: Enable nested posted interrupt processing.

arch/x86/kvm/vmx.c | 444 +++++++++++++++++++++++++++++++++++++++++-----------
1 files changed, 355 insertions(+), 89 deletions(-)
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Wincy Van

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Jan 19, 2015, 10:50:05 PM1/19/15
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Hi, Yang,

Could you please have a look at this patch set?
Your comment is very appreciated!


Thanks,

Wincy

Zhang, Yang Z

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Jan 19, 2015, 11:00:06 PM1/19/15
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Wincy Van wrote on 2015-01-20:
> Hi, Yang,
>
> Could you please have a look at this patch set?
> Your comment is very appreciated!

Sure. I will take a look.

>
>
> Thanks,
>
> Wincy


Best regards,
Yang


Wincy Van

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Jan 24, 2015, 5:20:07 AM1/24/15
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v1 ---> v2:
Use spin lock to ensure vmcs12 is safe when doing nested
posted interrupt delivery.

v2 ---> v3:
1. Add a new field in nested_vmx to avoid the spin lock in v2.
2. Drop send eoi to L1 when doing nested interrupt delivery.
3. Use hardware MSR bitmap to enable nested virtualize x2apic
mode.

Wincy Van (6):
KVM: nVMX: Use hardware MSR bitmap
KVM: nVMX: Enable nested virtualize x2apic mode.
KVM: nVMX: Make nested control MSRs per-cpu.
KVM: nVMX: Enable nested apic register virtualization.
KVM: nVMX: Enable nested virtual interrupt delivery.
KVM: nVMX: Enable nested posted interrupt processing.

arch/x86/kvm/vmx.c | 570 +++++++++++++++++++++++++++++++++++++++++++---------
1 files changed, 470 insertions(+), 100 deletions(-)

Paolo Bonzini

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Jan 27, 2015, 5:10:06 PM1/27/15
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On 24/01/2015 11:18, Wincy Van wrote:
> v2 ---> v3:
> 1. Add a new field in nested_vmx to avoid the spin lock in v2.
> 2. Drop send eoi to L1 when doing nested interrupt delivery.
> 3. Use hardware MSR bitmap to enable nested virtualize x2apic
> mode.

I think the patches are mostly okay. I made a few comments.

One of the things to do on top could be to avoid rebuilding the whole
vmcs02 on every entry. Recomputing the MSR bitmap on every vmentry is
not particularly nice, for example. It is not necessary unless the
execution controls have changed.

Paolo

Wincy Van

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Jan 28, 2015, 1:40:06 AM1/28/15
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On Wed, Jan 28, 2015 at 6:06 AM, Paolo Bonzini <pbon...@redhat.com> wrote:
>
>
> On 24/01/2015 11:18, Wincy Van wrote:
>> v2 ---> v3:
>> 1. Add a new field in nested_vmx to avoid the spin lock in v2.
>> 2. Drop send eoi to L1 when doing nested interrupt delivery.
>> 3. Use hardware MSR bitmap to enable nested virtualize x2apic
>> mode.
>
> I think the patches are mostly okay. I made a few comments.
>

Thank you, Paolo and Yang. I can't accomplish this without your help.

> One of the things to do on top could be to avoid rebuilding the whole
> vmcs02 on every entry. Recomputing the MSR bitmap on every vmentry is
> not particularly nice, for example. It is not necessary unless the
> execution controls have changed.

Indeed, I was planned to do that optimization after this patch set.


Thanks,
Wincy
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