[PATCH v7 06/17] ARM64 / ACPI: Make PCI optional for ACPI on ARM64

[Hanjun Guo]

Since PCI is not required in ACPI spec and ARM can run without
it, introduce some stub functions to make PCI optional for ACPI,
and make ACPI core run without CONFIG_PCI on ARM64.

When PCI is enabled on ARM64, ACPI core will need some PCI functions
to make it functional, so introduce some empty functions here and
implement it later.

Since ACPI on X86 and IA64 depends on PCI and this patch only makes
PCI optional for ARM64, it will not break anything on X86 and IA64.

Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
Tested-by: Yijing Wang <wangy...@huawei.com>
Signed-off-by: Hanjun Guo <hanju...@linaro.org>
---
arch/arm64/include/asm/pci.h | 6 ++++++
arch/arm64/kernel/pci.c | 28 ++++++++++++++++++++++++++++
drivers/acpi/Makefile | 2 +-
drivers/acpi/internal.h | 5 +++++
include/linux/pci.h | 37 +++++++++++++++++++++++++++----------
5 files changed, 67 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/include/asm/pci.h b/arch/arm64/include/asm/pci.h
index 872ba93..fded096 100644
--- a/arch/arm64/include/asm/pci.h
+++ b/arch/arm64/include/asm/pci.h
@@ -24,6 +24,12 @@
*/
#define PCI_DMA_BUS_IS_PHYS (0)

+static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
+{
+ /* no legacy IRQ on arm64 */
+ return -ENODEV;
+}
+
extern int isa_dma_bridge_buggy;

#ifdef CONFIG_PCI
diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c
index ce5836c..42fb195 100644
--- a/arch/arm64/kernel/pci.c
+++ b/arch/arm64/kernel/pci.c
@@ -10,6 +10,7 @@
*
*/

+#include <linux/acpi.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
@@ -68,3 +69,30 @@ void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent)
bus->domain_nr = domain;
}
#endif
+
+/*
+ * raw_pci_read/write - Platform-specific PCI config space access.
+ *
+ * Default empty implementation. Replace with an architecture-specific setup
+ * routine, if necessary.
+ */
+int raw_pci_read(unsigned int domain, unsigned int bus,
+ unsigned int devfn, int reg, int len, u32 *val)
+{
+ return -EINVAL;
+}
+
+int raw_pci_write(unsigned int domain, unsigned int bus,
+ unsigned int devfn, int reg, int len, u32 val)
+{
+ return -EINVAL;
+}
+
+#ifdef CONFIG_ACPI
+/* Root bridge scanning */
+struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
+{
+ /* TODO: Should be revisited when implementing PCI on ACPI */
+ return NULL;
+}
+#endif
diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
index 39f3ec1..c346011 100644
--- a/drivers/acpi/Makefile
+++ b/drivers/acpi/Makefile
@@ -43,7 +43,7 @@ acpi-y += processor_core.o
acpi-$(CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC) += processor_pdc.o
acpi-y += ec.o
acpi-$(CONFIG_ACPI_DOCK) += dock.o
-acpi-y += pci_root.o pci_link.o pci_irq.o
+acpi-$(CONFIG_PCI) += pci_root.o pci_link.o pci_irq.o
acpi-y += acpi_lpss.o
acpi-y += acpi_platform.o
acpi-y += acpi_pnp.o
diff --git a/drivers/acpi/internal.h b/drivers/acpi/internal.h
index 163e82f..c5ff8ba 100644
--- a/drivers/acpi/internal.h
+++ b/drivers/acpi/internal.h
@@ -26,8 +26,13 @@
acpi_status acpi_os_initialize1(void);
int init_acpi_device_notify(void);
int acpi_scan_init(void);
+#ifdef CONFIG_PCI
void acpi_pci_root_init(void);
void acpi_pci_link_init(void);
+#else
+static inline void acpi_pci_root_init(void) {}
+static inline void acpi_pci_link_init(void) {}
+#endif
void acpi_processor_init(void);
void acpi_platform_init(void);
void acpi_pnp_init(void);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 360a966..1476a66 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -564,15 +564,6 @@ struct pci_ops {
int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
};

-/*
- * ACPI needs to be able to access PCI config space before we've done a
- * PCI bus scan and created pci_bus structures.
- */
-int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
- int reg, int len, u32 *val);
-int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
- int reg, int len, u32 val);
-
struct pci_bus_region {
dma_addr_t start;
dma_addr_t end;
@@ -1329,6 +1320,16 @@ typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
unsigned int command_bits, u32 flags);
void pci_register_set_vga_state(arch_set_vga_state_t func);

+/*
+ * ACPI needs to be able to access PCI config space before we've done a
+ * PCI bus scan and created pci_bus structures.
+ */
+int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
+ int reg, int len, u32 *val);
+int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
+ int reg, int len, u32 val);
+void pcibios_penalize_isa_irq(int irq, int active);
+
#else /* CONFIG_PCI is not enabled */

/*
@@ -1430,6 +1431,23 @@ static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
unsigned int devfn)
{ return NULL; }

+static inline struct pci_bus *pci_find_bus(int domain, int busnr)
+{ return NULL; }
+
+static inline int pci_bus_write_config_byte(struct pci_bus *bus,
+ unsigned int devfn, int where, u8 val)
+{ return -ENOSYS; }
+
+static inline int raw_pci_read(unsigned int domain, unsigned int bus,
+ unsigned int devfn, int reg, int len, u32 *val)
+{ return -ENOSYS; }
+
+static inline int raw_pci_write(unsigned int domain, unsigned int bus,
+ unsigned int devfn, int reg, int len, u32 val)
+{ return -ENOSYS; }
+
+static inline void pcibios_penalize_isa_irq(int irq, int active) { }
+
static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
@@ -1639,7 +1657,6 @@ int pcibios_set_pcie_reset_state(struct pci_dev *dev,
enum pcie_reset_state state);
int pcibios_add_device(struct pci_dev *dev);
void pcibios_release_device(struct pci_dev *dev);
-void pcibios_penalize_isa_irq(int irq, int active);

#ifdef CONFIG_HIBERNATE_CALLBACKS
extern struct dev_pm_ops pcibios_pm_ops;
--
1.9.1

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[Hanjun Guo]

Using the information presented by GTDT to initialize the arch
timer (not memory-mapped).

Originally-by: Amit Daniel Kachhap <amit....@samsung.com>

Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
Tested-by: Yijing Wang <wangy...@huawei.com>
Signed-off-by: Hanjun Guo <hanju...@linaro.org>
---

arch/arm64/kernel/time.c | 7 ++
drivers/clocksource/arm_arch_timer.c | 132 ++++++++++++++++++++++++++++-------
include/linux/clocksource.h | 6 ++
3 files changed, 118 insertions(+), 27 deletions(-)

diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c
index 1a7125c..42f9195 100644
--- a/arch/arm64/kernel/time.c
+++ b/arch/arm64/kernel/time.c
@@ -35,6 +35,7 @@
#include <linux/delay.h>
#include <linux/clocksource.h>
#include <linux/clk-provider.h>
+#include <linux/acpi.h>

#include <clocksource/arm_arch_timer.h>

@@ -72,6 +73,12 @@ void __init time_init(void)

tick_setup_hrtimer_broadcast();

+ /*
+ * Since ACPI or FDT will only one be available in the system,
+ * we can use acpi_generic_timer_init() here safely
+ */
+ acpi_generic_timer_init();
+
arch_timer_rate = arch_timer_get_rate();
if (!arch_timer_rate)
panic("Unable to initialise architected timer.\n");
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 095c177..407aa63 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -21,6 +21,7 @@
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/sched_clock.h>
+#include <linux/acpi.h>

#include <asm/arch_timer.h>
#include <asm/virt.h>
@@ -370,8 +371,12 @@ arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np)
if (arch_timer_rate)
return;

- /* Try to determine the frequency from the device tree or CNTFRQ */
- if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) {
+ /*
+ * Try to determine the frequency from the device tree or CNTFRQ,
+ * if ACPI is enabled, get the frequency from CNTFRQ ONLY.
+ */
+ if (!acpi_disabled ||
+ of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) {
if (cntbase)
arch_timer_rate = readl_relaxed(cntbase + CNTFRQ);
else
@@ -690,28 +695,8 @@ static void __init arch_timer_common_init(void)
arch_timer_arch_init();
}

-static void __init arch_timer_init(struct device_node *np)
+static void __init arch_timer_init(void)
{
- int i;
-
- if (arch_timers_present & ARCH_CP15_TIMER) {
- pr_warn("arch_timer: multiple nodes in dt, skipping\n");
- return;
- }
-
- arch_timers_present |= ARCH_CP15_TIMER;
- for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
- arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
- arch_timer_detect_rate(NULL, np);
-
- /*
- * If we cannot rely on firmware initializing the timer registers then
- * we should use the physical timers instead.
- */
- if (IS_ENABLED(CONFIG_ARM) &&
- of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
- arch_timer_use_virtual = false;
-
/*
* If HYP mode is available, we know that the physical timer
* has been configured to be accessible from PL1. Use it, so
@@ -730,13 +715,39 @@ static void __init arch_timer_init(struct device_node *np)
}
}

- arch_timer_c3stop = !of_property_read_bool(np, "always-on");
-
arch_timer_register();
arch_timer_common_init();
}
-CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_init);
-CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_init);
+
+static void __init arch_timer_of_init(struct device_node *np)
+{
+ int i;
+
+ if (arch_timers_present & ARCH_CP15_TIMER) {
+ pr_warn("arch_timer: multiple nodes in dt, skipping\n");
+ return;
+ }
+
+ arch_timers_present |= ARCH_CP15_TIMER;
+ for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
+ arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
+
+ arch_timer_detect_rate(NULL, np);
+
+ arch_timer_c3stop = !of_property_read_bool(np, "always-on");
+
+ /*
+ * If we cannot rely on firmware initializing the timer registers then
+ * we should use the physical timers instead.
+ */
+ if (IS_ENABLED(CONFIG_ARM) &&
+ of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
+ arch_timer_use_virtual = false;
+
+ arch_timer_init();
+}
+CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
+CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);

static void __init arch_timer_mem_init(struct device_node *np)
{
@@ -803,3 +814,70 @@ static void __init arch_timer_mem_init(struct device_node *np)
}
CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
arch_timer_mem_init);
+
+#ifdef CONFIG_ACPI
+static int __init map_generic_timer_interrupt(u32 interrupt, u32 flags)
+{
+ int trigger, polarity;
+
+ if (!interrupt)
+ return 0;
+
+ trigger = (flags & ACPI_GTDT_INTERRUPT_MODE) ? ACPI_EDGE_SENSITIVE
+ : ACPI_LEVEL_SENSITIVE;
+
+ polarity = (flags & ACPI_GTDT_INTERRUPT_POLARITY) ? ACPI_ACTIVE_LOW
+ : ACPI_ACTIVE_HIGH;
+
+ return acpi_register_gsi(NULL, interrupt, trigger, polarity);
+}
+
+/* Initialize per-processor generic timer */
+static int __init arch_timer_acpi_init(struct acpi_table_header *table)
+{
+ struct acpi_table_gtdt *gtdt;
+
+ if (arch_timers_present & ARCH_CP15_TIMER) {
+ pr_warn("arch_timer: already initialized, skipping\n");

+ return -EINVAL;
+ }
+

+ gtdt = container_of(table, struct acpi_table_gtdt, header);
+
+ arch_timers_present |= ARCH_CP15_TIMER;
+
+ arch_timer_ppi[PHYS_SECURE_PPI] =
+ map_generic_timer_interrupt(gtdt->secure_el1_interrupt,
+ gtdt->secure_el1_flags);
+
+ arch_timer_ppi[PHYS_NONSECURE_PPI] =
+ map_generic_timer_interrupt(gtdt->non_secure_el1_interrupt,
+ gtdt->non_secure_el1_flags);
+
+ arch_timer_ppi[VIRT_PPI] =
+ map_generic_timer_interrupt(gtdt->virtual_timer_interrupt,
+ gtdt->virtual_timer_flags);
+
+ arch_timer_ppi[HYP_PPI] =
+ map_generic_timer_interrupt(gtdt->non_secure_el2_interrupt,
+ gtdt->non_secure_el2_flags);
+
+ /* Get the frequency from CNTFRQ */
+ arch_timer_detect_rate(NULL, NULL);
+
+ /* Always-on capability */
+ arch_timer_c3stop = !(gtdt->non_secure_el1_flags & ACPI_GTDT_ALWAYS_ON);
+
+ arch_timer_init();
+ return 0;
+}
+
+/* Initialize all the generic timers presented in GTDT */
+void __init acpi_generic_timer_init(void)
+{
+ if (acpi_disabled)
+ return;
+
+ acpi_table_parse(ACPI_SIG_GTDT, arch_timer_acpi_init);
+}
+#endif
diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h
index abcafaa..af6155a 100644
--- a/include/linux/clocksource.h
+++ b/include/linux/clocksource.h
@@ -346,4 +346,10 @@ extern void clocksource_of_init(void);
static inline void clocksource_of_init(void) {}
#endif

+#ifdef CONFIG_ACPI
+void acpi_generic_timer_init(void);
+#else
+static inline void acpi_generic_timer_init(void) { }
+#endif
+
#endif /* _LINUX_CLOCKSOURCE_H */

[Hanjun Guo]

Introduce a new function map_gicc_mpidr() to allow MPIDRs to be obtained
from the GICC Structure introduced by ACPI 5.1.

MPIDR is the CPU hardware ID as local APIC ID on x86 platform, so we use
MPIDR not the GIC CPU interface ID to identify CPUs.

Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
Tested-by: Yijing Wang <wangy...@huawei.com>
Signed-off-by: Hanjun Guo <hanju...@linaro.org>
---

arch/arm64/include/asm/acpi.h | 29 +++++++++++++++++++++++++++++
arch/arm64/kernel/acpi.c | 1 -
drivers/acpi/processor_core.c | 37 +++++++++++++++++++++++++++++++++++++
3 files changed, 66 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h
index c82d4a1..639bb2a 100644
--- a/arch/arm64/include/asm/acpi.h
+++ b/arch/arm64/include/asm/acpi.h
@@ -12,6 +12,8 @@
#ifndef _ASM_ACPI_H
#define _ASM_ACPI_H

+#include <asm/smp_plat.h>
+
/* Basic configuration for ACPI */
#ifdef CONFIG_ACPI
#define acpi_strict 1 /* No out-of-spec workarounds on ARM64 */
@@ -45,6 +47,33 @@ static inline void enable_acpi(void)
acpi_noirq = 0;
}

+/* MPIDR value provided in GICC structure is 64 bits, but the
+ * existing apic_id (CPU hardware ID) using in acpi processor
+ * driver is 32-bit, to conform to the same datatype we need
+ * to repack the GICC structure MPIDR.
+ *
+ * Only 32 bits of MPIDR are used:
+ *
+ * Bits [0:7] Aff0;
+ * Bits [8:15] Aff1;
+ * Bits [16:23] Aff2;
+ * Bits [32:39] Aff3;
+ */
+static inline u32 pack_mpidr(u64 mpidr)
+{
+ return (u32) ((mpidr & 0xff00000000) >> 8) | mpidr;
+}
+
+/*
+ * The ACPI processor driver for ACPI core code needs this macro
+ * to find out this cpu was already mapped (mapping from CPU hardware
+ * ID to CPU logical ID) or not.
+ *
+ * cpu_logical_map(cpu) is the mapping of MPIDR and the logical cpu,
+ * and MPIDR is the cpu hardware ID we needed to pack.
+ */
+#define cpu_physical_id(cpu) pack_mpidr(cpu_logical_map(cpu))
+
/*
* It's used from ACPI core in kdump to boot UP system with SMP kernel,
* with this check the ACPI core will not override the CPU index
diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
index 55d99d9..0b7c3a6 100644
--- a/arch/arm64/kernel/acpi.c
+++ b/arch/arm64/kernel/acpi.c
@@ -24,7 +24,6 @@
#include <linux/bootmem.h>
#include <linux/smp.h>

-#include <asm/smp_plat.h>
#include <asm/cputype.h>
#include <asm/cpu_ops.h>

diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c
index 02e4839..e634b14 100644
--- a/drivers/acpi/processor_core.c
+++ b/drivers/acpi/processor_core.c
@@ -64,6 +64,38 @@ static int map_lsapic_id(struct acpi_subtable_header *entry,
return 0;
}

+/*
+ * On ARM platform, MPIDR value is the hardware ID as apic ID
+ * on Intel platforms
+ */
+static int map_gicc_mpidr(struct acpi_subtable_header *entry,
+ int device_declaration, u32 acpi_id, int *mpidr)
+{
+ struct acpi_madt_generic_interrupt *gicc =
+ container_of(entry, struct acpi_madt_generic_interrupt, header);
+
+ if (!(gicc->flags & ACPI_MADT_ENABLED))
+ return -ENODEV;
+
+ /* In the GIC interrupt model, logical processors are
+ * required to have a Processor Device object in the DSDT,
+ * so we should check device_declaration here
+ */
+ if (device_declaration && (gicc->uid == acpi_id)) {
+ /*
+ * Only bits [0:7] Aff0, bits [8:15] Aff1, bits [16:23] Aff2
+ * and bits [32:39] Aff3 are meaningful, so pack the Affx
+ * fields into a single 32 bit identifier to accommodate the
+ * acpi processor drivers.
+ */
+ *mpidr = ((gicc->arm_mpidr & 0xff00000000) >> 8)
+ | gicc->arm_mpidr;

+ return 0;
+ }
+

+ return -EINVAL;
+}
+

static int map_madt_entry(int type, u32 acpi_id)
{
unsigned long madt_end, entry;
@@ -99,6 +131,9 @@ static int map_madt_entry(int type, u32 acpi_id)
} else if (header->type == ACPI_MADT_TYPE_LOCAL_SAPIC) {
if (!map_lsapic_id(header, type, acpi_id, &phys_id))
break;
+ } else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT) {
+ if (!map_gicc_mpidr(header, type, acpi_id, &phys_id))
+ break;
}
entry += header->length;
}
@@ -131,6 +166,8 @@ static int map_mat_entry(acpi_handle handle, int type, u32 acpi_id)
map_lsapic_id(header, type, acpi_id, &phys_id);
else if (header->type == ACPI_MADT_TYPE_LOCAL_X2APIC)
map_x2apic_id(header, type, acpi_id, &phys_id);
+ else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT)
+ map_gicc_mpidr(header, type, acpi_id, &phys_id);

exit:
kfree(buffer.pointer);

[Hanjun Guo]

When MADT is parsed, print GIC information to make the boot
log look pretty:

ACPI: GICC (acpi_id[0x0000] address[00000000e112f000] MPIDR[0x0] enabled)
ACPI: GICC (acpi_id[0x0001] address[00000000e112f000] MPIDR[0x1] enabled)
...
ACPI: GICC (acpi_id[0x0201] address[00000000e112f000] MPIDR[0x201] enabled)

These information will be very helpful to bring up early systems to
see if acpi_id and MPIDR are matched or not as spec defined.

Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
Tested-by: Yijing Wang <wangy...@huawei.com>
Signed-off-by: Hanjun Guo <hanju...@linaro.org>

Signed-off-by: Tomasz Nowicki <tomasz....@linaro.org>
---
drivers/acpi/tables.c | 43 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)

diff --git a/drivers/acpi/tables.c b/drivers/acpi/tables.c
index 93b8152..42d314f 100644
--- a/drivers/acpi/tables.c
+++ b/drivers/acpi/tables.c
@@ -183,6 +183,49 @@ void acpi_table_print_madt_entry(struct acpi_subtable_header *header)
}
break;

+ case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
+ {
+ struct acpi_madt_generic_interrupt *p =
+ (struct acpi_madt_generic_interrupt *)header;
+ pr_info("GICC (acpi_id[0x%04x] address[%p] MPIDR[0x%llx] %s)\n",
+ p->uid, (void *)(unsigned long)p->base_address,
+ p->arm_mpidr,
+ (p->flags & ACPI_MADT_ENABLED) ? "enabled" : "disabled");
+
+ }
+ break;
+
+ case ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR:
+ {
+ struct acpi_madt_generic_distributor *p =
+ (struct acpi_madt_generic_distributor *)header;
+ pr_info("GIC Distributor (gic_id[0x%04x] address[%p] gsi_base[%d])\n",
+ p->gic_id,
+ (void *)(unsigned long)p->base_address,
+ p->global_irq_base);
+ }
+ break;
+
+ case ACPI_MADT_TYPE_GENERIC_MSI_FRAME:
+ {
+ struct acpi_madt_generic_msi_frame *p =
+ (struct acpi_madt_generic_msi_frame *)header;
+ pr_info("GIC MSI Frame (msi_fame_id[%d] address[%p])\n",
+ p->msi_frame_id,
+ (void *)(unsigned long)p->base_address);
+ }
+ break;
+
+ case ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR:
+ {
+ struct acpi_madt_generic_redistributor *p =
+ (struct acpi_madt_generic_redistributor *)header;
+ pr_info("GIC Redistributor (address[%p] region_size[0x%x])\n",
+ (void *)(unsigned long)p->base_address,
+ p->length);
+ }
+ break;
+
default:
pr_warn("Found unsupported MADT entry (type = 0x%x)\n",
header->type);

[Hanjun Guo]

From: Graeme Gregory <graeme....@linaro.org>

Add documentation for the guidelines of how to use ACPI
on ARM64.

Reviewed-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
Reviewed-by: Yi Li <phoeni...@huawei.com>
Signed-off-by: Graeme Gregory <graeme....@linaro.org>
Signed-off-by: Al Stone <al.s...@linaro.org>

Signed-off-by: Hanjun Guo <hanju...@linaro.org>
---

Documentation/arm64/arm-acpi.txt | 327 +++++++++++++++++++++++++++++++++++++++
1 file changed, 327 insertions(+)
create mode 100644 Documentation/arm64/arm-acpi.txt

diff --git a/Documentation/arm64/arm-acpi.txt b/Documentation/arm64/arm-acpi.txt
new file mode 100644
index 0000000..21e7020
--- /dev/null
+++ b/Documentation/arm64/arm-acpi.txt
@@ -0,0 +1,327 @@
+ACPI on ARMv8 Servers
+---------------------
+ACPI can be used for ARMv8 general purpose servers designed to follow
+the ARM SBSA (Server Base System Architecture) and SBBR (Server Base
+Boot Requirements) specifications, currently available to those with
+an ARM login at http://silver.arm.com.
+
+The ARMv8 kernel implements the reduced hardware model of ACPI version
+5.1 and later. Links to the specification and all external documents
+it refers to are managed by the UEFI Forum. The specification is
+available at http://www.uefi.org/specifications and external documents
+can be found via http://www.uefi.org/acpi.
+
+If an ARMv8 system does not meet the requirements of the SBSA, or cannot
+be described using the mechanisms defined in the required ACPI specifications,
+then it is likely that Device Tree (DT) is more suitable than ACPI for the
+hardware.
+
+
+Relationship with Device Tree
+-----------------------------
+ACPI support in drivers and subsystems for ARMv8 should never be mutually
+exclusive with DT support at compile time.
+
+At boot time the kernel will only use one description method depending on
+parameters passed from the bootloader (including kernel bootargs).
+
+Regardless of whether DT or ACPI is used, the kernel must always be capable
+of booting with either scheme (in kernels with both schemes enabled at compile
+time).
+
+
+Booting using ACPI tables
+-------------------------
+The only defined method for passing ACPI tables to the kernel on ARMv8
+is via the UEFI system configuration table.
+
+Processing of ACPI tables may be disabled by passing acpi=off on the kernel
+command line; this is the default behavior if both ACPI and DT tables are
+present. If acpi=force is used, the kernel will ONLY use device configuration
+information contained in the ACPI tables if those tables are available.
+
+In order for the kernel to load and use ACPI tables, the UEFI implementation
+MUST set the ACPI_20_TABLE_GUID to point to the RSDP table (the table with
+the ACPI signature "RSD PTR "). If this pointer is incorrect and acpi=force
+is used, the kernel will disable ACPI and try to use DT to boot instead.
+
+If the pointer to the RSDP table is correct, the table will be mapped into
+the kernel by the ACPI core, using the address provided by UEFI.
+
+The ACPI core will then locate and map in all other ACPI tables provided by
+using the addresses in the RSDP table to find the XSDT (eXtended System
+Description Table). The XSDT in turn provides the addresses to all other
+ACPI tables provided by the system firmware; the ACPI core will then traverse
+this table and map in the tables listed.
+
+The ACPI core will ignore any provided RSDT (Root System Description Table).
+RSDTs have been deprecated and are ignored on arm64 since they only allow
+for 32-bit addresses.
+
+Further, the ACPI core will only use the 64-bit address fields in the FADT
+(Fixed ACPI Description Table). Any 32-bit address fields in the FADT will
+be ignored on arm64.
+
+Hardware reduced mode (see Section 4.1 of the ACPI 5.1 specification) will
+be enforced by the ACPI core on arm64. Doing so allows the ACPI core to
+run less complex code since it no longer has to provide support for legacy
+hardware from other architectures.
+
+For the ACPI core to operate properly, and in turn provide the information
+the kernel needs to configure devices, it expects to find the following
+tables (all section numbers refer to the ACPI 5.1 specfication):
+
+ -- RSDP (Root System Description Pointer), section 5.2.5
+
+ -- XSDT (eXtended System Description Table), section 5.2.8
+
+ -- FADT (Fixed ACPI Description Table), section 5.2.9
+
+ -- DSDT (Differentiated System Description Table), section
+ 5.2.11.1
+
+ -- MADT (Multiple APIC Description Table), section 5.2.12
+
+ -- GTDT (Generic Timer Description Table), section 5.2.24
+
+ -- If PCI is supported, the MCFG (Memory mapped ConFiGuration
+ Table), section 5.2.6, specifically Table 5-31.
+
+If the above tables are not all present, the kernel may or may not be
+able to boot properly since it may not be able to configure all of the
+devices available.
+
+
+ACPI Detection
+--------------
+Drivers should determine their probe() type by checking for a null
+value for ACPI_HANDLE, or checking .of_node, or other information in
+the device structure. This is detailed further in the "Driver
+Recommendations" section.
+
+In non-driver code, if the presence of ACPI needs to be detected at
+runtime, then check the value of acpi_disabled. If CONFIG_ACPI is not
+set, acpi_disabled will always be 1.
+
+
+Device Enumeration
+------------------
+Device descriptions in ACPI should use standard recognized ACPI interfaces.
+These may contain less information than is typically provided via a Device
+Tree description for the same device. This is also one of the reasons that
+ACPI can be useful -- the driver takes into account that it may have less
+detailed information about the device and uses sensible defaults instead.
+If done properly in the driver, the hardware can change and improve over
+time without the driver having to change at all.
+
+Clocks provide an excellent example. In DT, clocks need to be specified
+and the drivers need to take them into account. In ACPI, the assumption
+is that UEFI will leave the device in a reasonable default state, including
+any clock settings. If for some reason the driver needs to change a clock
+value, this can be done in an ACPI method; all the driver needs to do is
+invoke the method and not concern itself with what the method needs to do
+to change the clock. Changing the hardware can then take place over time
+by changing what the ACPI method does, and not the driver.
+
+ACPI drivers should only look at one specific ASL object -- the _DSD object
+-- for device driver parameters (known in DT as "bindings", or "Device
+Properties" in ACPI). DT bindings also will be reviewed before used. The UEFI
+Forum provides a mechanism for registering such bindings [URL TBD by ASWG]
+so that they may be used on any operating system supporting ACPI. Device
+properties that have not been registered with the UEFI Forum should not be
+used.
+
+Drivers should look for device properties in the _DSD object ONLY; the _DSD
+object is described in the ACPI specification section 6.2.5, but more
+specifically, use the _DSD Device Properties UUID:
+
+ -- UUID: daffd814-6eba-4d8c-8a91-bc9bbf4aa301
+
+ -- http://www.uefi.org/sites/default/files/resources/_DSD-device-properties-UUID.pdf
+
+The kernel has an interface for looking up device properties in a manner
+independent of whether DT or ACPI is being used and that interface should
+be used; it can eliminate some duplication of code paths in driver probing
+functions and discourage divergence between DT bindings and ACPI device
+properties.
+
+ACPI tables are described with a formal language called ASL, the ACPI
+Source Language (section 19 of the specification). This means that there
+are always multiple ways to describe the same thing -- including device
+properties. For example, device properties could use an ASL construct
+that looks like this: Name(KEY0, "value0"). An ACPI device driver would
+then retrieve the value of the property by evaluating the KEY0 object.
+However, using Name() this way has multiple problems: (1) ACPI limits
+names ("KEY0") to four characters unlike DT; (2) there is no industry
+wide registry that maintains a list of names, minimzing re-use; (3)
+there is also no registry for the definition of property values ("value0"),
+again making re-use difficult; and (4) how does one maintain backward
+compatibility as new hardware comes out? The _DSD method was created
+to solve precisely these sorts of problems; Linux drivers should ALWAYS
+use the _DSD method for device properties and nothing else.
+
+The _DSM object (ACPI Section 9.14.1) could also be used for conveying
+device properties to a driver. Linux drivers should only expect it to
+be used if _DSD cannot represent the data required, and there is no way
+to create a new UUID for the _DSD object. Note that there is even less
+regulation of the use of _DSM than there is of _DSD. Drivers that depend
+on the contents of _DSM objects will be more difficult to maintain over
+time because of this.
+
+The _DSD object is a very flexible mechanism in ACPI, as are the registered
+Device Properties. This flexibility allows _DSD to cover more than just the
+generic server case and care should be taken in device drivers not to expect
+it to replicate highly specific embedded behaviour from DT.
+
+Both DT bindings and ACPI device properties for device drivers have review
+processes. Use them. And, before creating new device properties, check to
+be sure that they have not been defined before and either registered in the
+Linux kernel documentation or the UEFI Forum. If the device drivers supports
+ACPI and DT, please make sure the device properties are consistent in both
+places.
+
+
+Programmable Power Control Resources
+------------------------------------
+Programmable power control resources include such resources as voltage/current
+providers (regulators) and clock sources.
+
+The kernel assumes that power control of these resources is represented with
+Power Resource Objects (ACPI section 7.1). The ACPI core will then handle
+correctly enabling and disabling resources as they are needed. In order to
+get that to work, ACPI assumes each device has defined D-states and that these
+can be controlled through the optional ACPI methods _PS0, _PS1, _PS2, and _PS3;
+in ACPI, _PS0 is the method to invoke to turn a device full on, and _PS3 is for
+turning a device full off.
+
+There are two options for using those Power Resources.
+ -- be managed in _PSx routine which gets called on entry to Dx.
+
+ -- be declared separately as power resources with their own _ON and _OFF
+ methods. They are then tied back to D-states for a particular device
+ via _PRx which specifies which power resources a device needs to be on
+ while in Dx. Kernel then tracks number of devices using a power resource
+ and calls _ON/_OFF as needed.
+
+The kernel ACPI code will also assume that the _PSx methods follow the normal
+ACPI rules for such methods:
+
+ -- If either _PS0 or _PS3 is implemented, then the other method must also
+ be implemented.
+
+ -- If a device requires usage or setup of a power resource when on, the ASL
+ should organize that it is allocated/enabled using the _PS0 method.
+
+ -- Resources allocated or enabled in the _PS0 method should be disabled
+ or de-allocated in the _PS3 method.
+
+ -- Firmware will leave the resources in a reasonable state before handing
+ over control to the kernel.
+
+Such code in _PSx methods will of course be very platform specific. But,
+this allows the driver to abstract out the interface for operating the device
+and avoid having to read special non-standard values from ACPI tables. Further,
+abstracting the use of these resources allows the hardware to change over time
+without requiring updates to the driver.
+
+
+Clocks
+------
+ACPI makes the assumption that clocks are initialized by the firmware --
+UEFI, in this case -- to some working value before control is handed over
+to the kernel. This has implications for devices such as UARTs, or SoC-driven
+LCD displays, for example.
+
+When the kernel boots, the clock is assumed to be set to a reasonable
+working value. If for some reason the frequency needs to change -- e.g.,
+throttling for power management -- the device driver should expect that
+process to be abstracted out into some ACPI method that can be invoked
+(please see the ACPI specification for further recommendations on standard
+methods to be expected) except CPU clocks where CPPC provides a much richer
+interface instead of some method. If it is not, there is no direct way for
+ACPI to control the clocks.
+
+
+Driver Recommendations
+----------------------
+DO NOT remove any DT handling when adding ACPI support for a driver. The
+same device may be used on many different systems.
+
+DO try to structure the driver so that it is data-driven. That is, set up
+a struct containing internal per-device state based on defaults and whatever
+else must be discovered by the driver probe function. Then, have the rest
+of the driver operate off of the contents of that struct. Doing so should
+allow most divergence between ACPI and DT functionality to be kept local to
+the probe function instead of being scattered throughout the driver. For
+example:
+
+static int device_probe_dt(struct platform_device *pdev)
+{
+ /* DT specific functionality */
+ ...
+}
+
+static int device_probe_acpi(struct platform_device *pdev)
+{
+ /* ACPI specific functionality */
+ ...
+}
+
+static int device_probe(stuct platform_device *pdev)
+{
+ ...
+ struct device_node node = pdev->dev.of_node;
+ ...
+
+ if (node)
+ ret = device_probe_dt(pdev);
+ else if (ACPI_HANDLE(&pdev->dev))
+ ret = device_probe_acpi(pdev);
+ else
+ /* other initialization */
+ ...
+ /* Continue with any generic probe operations */
+ ...
+}
+
+DO keep the MODULE_DEVICE_TABLE entries together in the driver to make it
+clear the different names the driver is probed for, both from DT and from
+ACPI:
+
+static struct of_device_id virtio_mmio_match[] = {
+ { .compatible = "virtio,mmio", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, virtio_mmio_match);
+
+static const struct acpi_device_id virtio_mmio_acpi_match[] = {
+ { "LNRO0005", },
+ { }
+};
+MODULE_DEVICE_TABLE(acpi, virtio_mmio_acpi_match);
+
+
+ASWG
+----
+The following areas are not yet fully defined for ARM in the 5.1 version
+of the ACPI specification and are expected to be worked through in the
+UEFI ACPI Specification Working Group (ASWG):
+
+ -- ACPI based CPU topology
+ -- ACPI based CPU idle control
+ -- ACPI based SMMU and its IO topology
+ -- ITS support for GIC in MADT
+
+Participation in this group is open to all UEFI members. Please see
+http://www.uefi.org/workinggroup for details on group membership.
+
+It is the intent of the ARMv8 ACPI kernel code to follow the ACPI specification
+as closely as possible, and to only implement functionality that complies with
+the released standards from UEFI ASWG. As a practical matter, there will be
+vendors that provide bad ACPI tables or violate the standards in some way.
+If this is because of errors, quirks and fixups may be necessary, but will
+be avoided if possible. If there are features missing from ACPI that preclude
+it from being used on a platform, ECRs (Engineering Change Requests) should be
+submitted to ASWG and go through the normal approval process; for those that
+are not UEFI members, many other members of the Linux community are and would
+likely be willing to assist in submitting ECRs.

[Hanjun Guo]

From: Al Stone <al.s...@linaro.org>

ACPI reduced hardware mode is disabled by default, but ARM64
can only run properly in ACPI hardware reduced mode, so select
ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on ARM64.

Reviewed-by: Grant Likely <grant....@linaro.org>

Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
Tested-by: Yijing Wang <wangy...@huawei.com>

Signed-off-by: Al Stone <al.s...@linaro.org>
Signed-off-by: Hanjun Guo <hanju...@linaro.org>
---

arch/arm64/Kconfig | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index b1f9a20..c19ae5d 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1,5 +1,6 @@
config ARM64
def_bool y
+ select ACPI_REDUCED_HARDWARE_ONLY if ACPI
select ARCH_BINFMT_ELF_RANDOMIZE_PIE
select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
select ARCH_HAS_GCOV_PROFILE_ALL

[Hanjun Guo]

From: Graeme Gregory <graeme....@linaro.org>

ACPI 5.1 does not currently support S states for ARM64 hardware but
ACPI code will call acpi_target_system_state() for device power
managment, so introduce sleep-arm.c to allow other drivers to function
until S states are defined.

Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
Tested-by: Yijing Wang <wangy...@huawei.com>

Signed-off-by: Graeme Gregory <graeme....@linaro.org>
Signed-off-by: Tomasz Nowicki <tomasz....@linaro.org>

Signed-off-by: Hanjun Guo <hanju...@linaro.org>
---

drivers/acpi/Makefile | 4 ++++
drivers/acpi/sleep-arm.c | 28 ++++++++++++++++++++++++++++
2 files changed, 32 insertions(+)
create mode 100644 drivers/acpi/sleep-arm.c

diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
index f74317c..39f3ec1 100644
--- a/drivers/acpi/Makefile
+++ b/drivers/acpi/Makefile
@@ -23,7 +23,11 @@ acpi-y += nvs.o

# Power management related files
acpi-y += wakeup.o
+ifeq ($(ARCH), arm64)
+acpi-y += sleep-arm.o
+else # X86, IA64
acpi-y += sleep.o
+endif
acpi-y += device_pm.o
acpi-$(CONFIG_ACPI_SLEEP) += proc.o

diff --git a/drivers/acpi/sleep-arm.c b/drivers/acpi/sleep-arm.c
new file mode 100644
index 0000000..54578ef
--- /dev/null
+++ b/drivers/acpi/sleep-arm.c
@@ -0,0 +1,28 @@
+/*
+ * ARM64 Specific Sleep Functionality
+ *
+ * Copyright (C) 2013-2014, Linaro Ltd.
+ * Author: Graeme Gregory <graeme....@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/acpi.h>
+
+/*
+ * Currently the ACPI 5.1 standard does not define S states in a
+ * manner which is usable for ARM64. These two stubs are sufficient
+ * that system initialises and device PM works.
+ */
+u32 acpi_target_system_state(void)
+{
+ return ACPI_STATE_S0;
+}
+EXPORT_SYMBOL_GPL(acpi_target_system_state);
+
+int __init acpi_sleep_init(void)
+{
+ return -ENOSYS;
+}

[Hanjun Guo]

From: Tomasz Nowicki <tomasz....@linaro.org>

ACPI kernel uses MADT table for proper GIC initialization. It needs to
parse GIC related subtables, collect CPU interface and distributor
addresses and call driver initialization function (which is hardware
abstraction agnostic). In a similar way, FDT initialize GICv1/2.

NOTE: This commit allow to initialize GICv1/2 basic functionality.
GICv2 vitalization extension, GICv3/4 and ITS are considered as next
steps.

Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
Tested-by: Yijing Wang <wangy...@huawei.com>

Signed-off-by: Tomasz Nowicki <tomasz....@linaro.org>
Signed-off-by: Hanjun Guo <hanju...@linaro.org>
---

arch/arm64/kernel/acpi.c | 26 +++++++++
drivers/irqchip/irq-gic.c | 108 +++++++++++++++++++++++++++++++++++
drivers/irqchip/irqchip.c | 3 +
include/linux/irqchip/arm-gic-acpi.h | 31 ++++++++++
4 files changed, 168 insertions(+)
create mode 100644 include/linux/irqchip/arm-gic-acpi.h

diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
index c3e24c4..ea3c9fc 100644
--- a/arch/arm64/kernel/acpi.c
+++ b/arch/arm64/kernel/acpi.c
@@ -23,6 +23,7 @@
#include <linux/irqdomain.h>
#include <linux/bootmem.h>
#include <linux/smp.h>
+#include <linux/irqchip/arm-gic-acpi.h>

#include <asm/cputype.h>
#include <asm/cpu_ops.h>
@@ -315,6 +316,31 @@ void __init acpi_boot_table_init(void)
pr_err("Can't find FADT or error happened during parsing FADT\n");
}

+void __init acpi_gic_init(void)
+{
+ struct acpi_table_header *table;
+ acpi_status status;
+ acpi_size tbl_size;
+ int err;

+
+ if (acpi_disabled)
+ return;
+

+ status = acpi_get_table_with_size(ACPI_SIG_MADT, 0, &table, &tbl_size);
+ if (ACPI_FAILURE(status)) {
+ const char *msg = acpi_format_exception(status);
+
+ pr_err("Failed to get MADT table, %s\n", msg);
+ return;
+ }
+
+ err = gic_v2_acpi_init(table);
+ if (err)
+ pr_err("Failed to initialize GIC IRQ controller");
+
+ early_acpi_os_unmap_memory((char *)table, tbl_size);
+}
+
static int __init parse_acpi(char *arg)
{
if (!arg)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index d617ee5..89a8120 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -33,12 +33,14 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
+#include <linux/acpi.h>
#include <linux/irqdomain.h>
#include <linux/interrupt.h>
#include <linux/percpu.h>
#include <linux/slab.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqchip/arm-gic.h>
+#include <linux/irqchip/arm-gic-acpi.h>

#include <asm/cputype.h>
#include <asm/irq.h>
@@ -1083,3 +1085,109 @@ IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);

#endif
+
+#ifdef CONFIG_ACPI
+static phys_addr_t dist_phy_base, cpu_phy_base;
+static int cpu_base_assigned;
+
+static int __init
+gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header,
+ const unsigned long end)
+{
+ struct acpi_madt_generic_interrupt *processor;
+ phys_addr_t gic_cpu_base;
+
+ processor = (struct acpi_madt_generic_interrupt *)header;
+
+ if (BAD_MADT_ENTRY(processor, end))
+ return -EINVAL;
+
+ /*
+ * There is no support for non-banked GICv1/2 register in ACPI spec.
+ * All CPU interface addresses have to be the same.
+ */
+ gic_cpu_base = processor->base_address;
+ if (cpu_base_assigned && gic_cpu_base != cpu_phy_base)
+ return -EFAULT;
+
+ cpu_phy_base = gic_cpu_base;
+ cpu_base_assigned = 1;

+ return 0;
+}
+

+static int __init
+gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header,
+ const unsigned long end)
+{
+ struct acpi_madt_generic_distributor *dist;
+
+ dist = (struct acpi_madt_generic_distributor *)header;
+
+ if (BAD_MADT_ENTRY(dist, end))
+ return -EINVAL;
+
+ dist_phy_base = dist->base_address;

+ return 0;
+}
+

+int __init
+gic_v2_acpi_init(struct acpi_table_header *table)
+{
+ void __iomem *cpu_base, *dist_base;
+ int count;
+
+ /* Collect CPU base addresses */
+ count = acpi_parse_entries(ACPI_SIG_MADT,
+ sizeof(struct acpi_table_madt),
+ gic_acpi_parse_madt_cpu, table,
+ ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0);
+ if (count < 0) {
+ pr_err("Error during GICC entries parsing\n");
+ return -EFAULT;
+ } else if (!count) {
+ pr_err("No valid GICC entries exist\n");

+ return -EINVAL;
+ }
+

+ /*
+ * Find distributor base address. We expect one distributor entry since
+ * ACPI 5.1 spec neither support multi-GIC instances nor GIC cascade.
+ */
+ count = acpi_parse_entries(ACPI_SIG_MADT,
+ sizeof(struct acpi_table_madt),
+ gic_acpi_parse_madt_distributor, table,
+ ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0);
+ if (count <= 0) {
+ pr_err("Error during GICD entries parsing\n");
+ return -EFAULT;
+ } else if (!count) {
+ pr_err("No valid GICD entries exist\n");
+ return -EINVAL;
+ } else if (count > 1) {
+ pr_err("More than one GICD entry detected\n");

+ return -EINVAL;
+ }
+

+ cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE);
+ if (!cpu_base) {
+ pr_err("Unable to map GICC registers\n");
+ return -ENOMEM;
+ }
+
+ dist_base = ioremap(dist_phy_base, ACPI_GICV2_DIST_MEM_SIZE);
+ if (!dist_base) {
+ pr_err("Unable to map GICD registers\n");
+ iounmap(cpu_base);
+ return -ENOMEM;
+ }
+
+ /*
+ * Initialize zero GIC instance (no multi-GIC support). Also, set GIC
+ * as default IRQ domain to allow for GSI registration and GSI to IRQ
+ * number translation (see acpi_register_gsi() and acpi_gsi_to_irq()).
+ */
+ gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL);
+ irq_set_default_host(gic_data[0].domain);
+ return 0;
+}
+#endif
diff --git a/drivers/irqchip/irqchip.c b/drivers/irqchip/irqchip.c
index 0fe2f71..9106c6d 100644
--- a/drivers/irqchip/irqchip.c
+++ b/drivers/irqchip/irqchip.c
@@ -11,6 +11,7 @@
#include <linux/init.h>
#include <linux/of_irq.h>
#include <linux/irqchip.h>
+#include <linux/irqchip/arm-gic-acpi.h>

/*
* This special of_device_id is the sentinel at the end of the
@@ -26,4 +27,6 @@ extern struct of_device_id __irqchip_of_table[];
void __init irqchip_init(void)
{
of_irq_init(__irqchip_of_table);
+
+ acpi_gic_init();
}
diff --git a/include/linux/irqchip/arm-gic-acpi.h b/include/linux/irqchip/arm-gic-acpi.h
new file mode 100644
index 0000000..ad5b577
--- /dev/null
+++ b/include/linux/irqchip/arm-gic-acpi.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2014, Linaro Ltd.
+ * Author: Tomasz Nowicki <tomasz....@linaro.org>

+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+

+#ifndef ARM_GIC_ACPI_H_
+#define ARM_GIC_ACPI_H_
+
+#ifdef CONFIG_ACPI
+
+/*
+ * Hard code here, we can not get memory size from MADT (but FDT does),
+ * Actually no need to do that, because this size can be inferred
+ * from GIC spec.
+ */
+#define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K)
+#define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
+
+struct acpi_table_header;
+
+void acpi_gic_init(void);
+int gic_v2_acpi_init(struct acpi_table_header *table);
+#else
+static inline void acpi_gic_init(void) { }
+#endif
+
+#endif /* ARM_GIC_ACPI_H_ */

[Hanjun Guo]

From: Graeme Gregory <graeme....@linaro.org>

Add Kconfigs to build ACPI on ARM64, and make ACPI available on ARM64.

acpi_idle driver is x86/IA64 dependent now, so make CONFIG_ACPI_PROCESSOR
depend on X86 || IA64, and implement it on ARM64 in the future.

Reviewed-by: Grant Likely <grant....@linaro.org>

Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
Tested-by: Yijing Wang <wangy...@huawei.com>

Signed-off-by: Graeme Gregory <graeme....@linaro.org>
Signed-off-by: Al Stone <al.s...@linaro.org>

Signed-off-by: Hanjun Guo <hanju...@linaro.org>
---

arch/arm64/Kconfig | 2 ++
drivers/acpi/Kconfig | 6 +++---
2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index c19ae5d..915aa16 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -647,6 +647,8 @@ source "drivers/Kconfig"

source "drivers/firmware/Kconfig"

+source "drivers/acpi/Kconfig"
+
source "fs/Kconfig"

source "arch/arm64/kvm/Kconfig"
diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
index 8951cef..3e3bd35 100644
--- a/drivers/acpi/Kconfig
+++ b/drivers/acpi/Kconfig
@@ -5,8 +5,7 @@
menuconfig ACPI
bool "ACPI (Advanced Configuration and Power Interface) Support"
depends on !IA64_HP_SIM
- depends on IA64 || X86
- depends on PCI
+ depends on ((IA64 || X86) && PCI) || (ARM64 && EXPERT)
select PNP
default y
help
@@ -163,6 +162,7 @@ config ACPI_PROCESSOR
tristate "Processor"
select THERMAL
select CPU_IDLE
+ depends on X86 || IA64
default y
help
This driver installs ACPI as the idle handler for Linux and uses
@@ -263,7 +263,7 @@ config ACPI_DEBUG

config ACPI_PCI_SLOT
bool "PCI slot detection driver"
- depends on SYSFS
+ depends on SYSFS && PCI
default n
help
This driver creates entries in /sys/bus/pci/slots/ for all PCI

[Hanjun Guo]

From: Graeme Gregory <graeme....@linaro.org>

There are two flags: PSCI_COMPLIANT and PSCI_USE_HVC. When set,
the former signals to the OS that the firmware is PSCI compliant.
The latter selects the appropriate conduit for PSCI calls by
toggling between Hypervisor Calls (HVC) and Secure Monitor Calls
(SMC).

FADT table contains such information in ACPI 5.1, FADT table was
parsed in ACPI table init and copy to struct acpi_gbl_FADT, so
use the flags in struct acpi_gbl_FADT for PSCI init.

Since ACPI 5.1 doesn't support self defined PSCI function IDs,
which means that only PSCI 0.2+ is supported in ACPI.

Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
Tested-by: Yijing Wang <wangy...@huawei.com>
Signed-off-by: Graeme Gregory <graeme....@linaro.org>

Signed-off-by: Tomasz Nowicki <tomasz....@linaro.org>

Signed-off-by: Hanjun Guo <hanju...@linaro.org>
---

arch/arm64/include/asm/acpi.h | 14 ++++++++
arch/arm64/include/asm/psci.h | 3 +-
arch/arm64/kernel/psci.c | 78 ++++++++++++++++++++++++++++++-------------
arch/arm64/kernel/setup.c | 8 +++--
4 files changed, 75 insertions(+), 28 deletions(-)

diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h
index 496c33b..221ff15 100644
--- a/arch/arm64/include/asm/acpi.h
+++ b/arch/arm64/include/asm/acpi.h
@@ -19,6 +19,18 @@ extern int acpi_disabled;
extern int acpi_noirq;
extern int acpi_pci_disabled;

+/* 1 to indicate PSCI 0.2+ is implemented */
+static inline bool acpi_psci_present(void)
+{
+ return acpi_gbl_FADT.arm_boot_flags & ACPI_FADT_PSCI_COMPLIANT;
+}
+
+/* 1 to indicate HVC must be used instead of SMC as the PSCI conduit */
+static inline bool acpi_psci_use_hvc(void)
+{
+ return acpi_gbl_FADT.arm_boot_flags & ACPI_FADT_PSCI_USE_HVC;
+}
+
static inline void disable_acpi(void)
{
acpi_disabled = 1;
@@ -49,6 +61,8 @@ static inline void arch_fix_phys_package_id(int num, u32 slot) { }

#else
static inline void disable_acpi(void) { }
+static inline bool acpi_psci_present(void) { return false; }
+static inline bool acpi_psci_use_hvc(void) { return false; }
#endif /* CONFIG_ACPI */

#endif /*_ASM_ACPI_H*/
diff --git a/arch/arm64/include/asm/psci.h b/arch/arm64/include/asm/psci.h
index e5312ea..2454bc5 100644
--- a/arch/arm64/include/asm/psci.h
+++ b/arch/arm64/include/asm/psci.h
@@ -14,6 +14,7 @@
#ifndef __ASM_PSCI_H
#define __ASM_PSCI_H

-int psci_init(void);
+int psci_dt_init(void);
+int psci_acpi_init(void);

#endif /* __ASM_PSCI_H */
diff --git a/arch/arm64/kernel/psci.c b/arch/arm64/kernel/psci.c
index f1dbca7..0ec0dc5 100644
--- a/arch/arm64/kernel/psci.c
+++ b/arch/arm64/kernel/psci.c
@@ -15,6 +15,7 @@

#define pr_fmt(fmt) "psci: " fmt

+#include <linux/acpi.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/smp.h>
@@ -24,6 +25,7 @@
#include <linux/slab.h>
#include <uapi/linux/psci.h>

+#include <asm/acpi.h>
#include <asm/compiler.h>
#include <asm/cpu_ops.h>
#include <asm/errno.h>
@@ -304,6 +306,33 @@ static void psci_sys_poweroff(void)
invoke_psci_fn(PSCI_0_2_FN_SYSTEM_OFF, 0, 0, 0);
}

+static void __init psci_0_2_set_functions(void)
+{
+ pr_info("Using standard PSCI v0.2 function IDs\n");
+ psci_function_id[PSCI_FN_CPU_SUSPEND] = PSCI_0_2_FN64_CPU_SUSPEND;
+ psci_ops.cpu_suspend = psci_cpu_suspend;
+
+ psci_function_id[PSCI_FN_CPU_OFF] = PSCI_0_2_FN_CPU_OFF;
+ psci_ops.cpu_off = psci_cpu_off;
+
+ psci_function_id[PSCI_FN_CPU_ON] = PSCI_0_2_FN64_CPU_ON;
+ psci_ops.cpu_on = psci_cpu_on;
+
+ psci_function_id[PSCI_FN_MIGRATE] = PSCI_0_2_FN64_MIGRATE;
+ psci_ops.migrate = psci_migrate;
+
+ psci_function_id[PSCI_FN_AFFINITY_INFO] = PSCI_0_2_FN64_AFFINITY_INFO;
+ psci_ops.affinity_info = psci_affinity_info;
+
+ psci_function_id[PSCI_FN_MIGRATE_INFO_TYPE] =
+ PSCI_0_2_FN_MIGRATE_INFO_TYPE;
+ psci_ops.migrate_info_type = psci_migrate_info_type;
+
+ arm_pm_restart = psci_sys_reset;
+
+ pm_power_off = psci_sys_poweroff;
+}
+
/*
* PSCI Function IDs for v0.2+ are well defined so use
* standard values.
@@ -337,29 +366,7 @@ static int __init psci_0_2_init(struct device_node *np)
}
}

- pr_info("Using standard PSCI v0.2 function IDs\n");
- psci_function_id[PSCI_FN_CPU_SUSPEND] = PSCI_0_2_FN64_CPU_SUSPEND;
- psci_ops.cpu_suspend = psci_cpu_suspend;
-
- psci_function_id[PSCI_FN_CPU_OFF] = PSCI_0_2_FN_CPU_OFF;
- psci_ops.cpu_off = psci_cpu_off;
-
- psci_function_id[PSCI_FN_CPU_ON] = PSCI_0_2_FN64_CPU_ON;
- psci_ops.cpu_on = psci_cpu_on;
-
- psci_function_id[PSCI_FN_MIGRATE] = PSCI_0_2_FN64_MIGRATE;
- psci_ops.migrate = psci_migrate;
-
- psci_function_id[PSCI_FN_AFFINITY_INFO] = PSCI_0_2_FN64_AFFINITY_INFO;
- psci_ops.affinity_info = psci_affinity_info;
-
- psci_function_id[PSCI_FN_MIGRATE_INFO_TYPE] =
- PSCI_0_2_FN_MIGRATE_INFO_TYPE;
- psci_ops.migrate_info_type = psci_migrate_info_type;
-
- arm_pm_restart = psci_sys_reset;
-
- pm_power_off = psci_sys_poweroff;
+ psci_0_2_set_functions();

out_put_node:
of_node_put(np);
@@ -412,7 +419,7 @@ static const struct of_device_id psci_of_match[] __initconst = {
{},
};

-int __init psci_init(void)
+int __init psci_dt_init(void)
{
struct device_node *np;
const struct of_device_id *matched_np;
@@ -427,6 +434,29 @@ int __init psci_init(void)
return init_fn(np);
}

+/*
+ * We use PSCI 0.2+ when ACPI is deployed on ARM64 and it's
+ * explicitly clarified in SBBR
+ */
+int __init psci_acpi_init(void)
+{
+ if (!acpi_psci_present()) {
+ pr_info("is not implemented in ACPI.\n");
+ return -EOPNOTSUPP;
+ }
+
+ pr_info("probing for conduit method from ACPI.\n");
+
+ if (acpi_psci_use_hvc())
+ invoke_psci_fn = __invoke_psci_fn_hvc;
+ else
+ invoke_psci_fn = __invoke_psci_fn_smc;
+
+ psci_0_2_set_functions();
+

+ return 0;
+}
+

#ifdef CONFIG_SMP

static int __init cpu_psci_cpu_init(struct device_node *dn, unsigned int cpu)
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index 5d139e1..ef5b1e1 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -411,10 +411,12 @@ void __init setup_arch(char **cmdline_p)
efi_idmap_init();
early_ioremap_reset();

- if (acpi_disabled)
+ if (acpi_disabled) {
unflatten_device_tree();
-
- psci_init();
+ psci_dt_init();
+ } else {
+ psci_acpi_init();
+ }

cpu_read_bootcpu_ops();
#ifdef CONFIG_SMP

[Hanjun Guo]

Hi,

This is the v7 of ACPI core patches for ARM64 based on ACPI 5.1

updates from v6:
- Rebased on top of 3.19-rc4, add Mack Salter's patch to use
the early_ioremap after paging_init() for ACPI table mappings;

- Two patches about converting apic_id to phys_id to make it arch
agnostic were already merged into RC4 by Rafael.

- Split patch "Parse FADT table to get PSCI flags for PSCI init"
into two as Lorenzo's suggestion, also fix typo and lack of __init
for psci_0_2_set_functions() which is spotted by Lorenzo.

- Add Tested-by from Yijing Wang.

previous version is here:
v6: https://lkml.org/lkml/2015/1/4/40

1. Why we need ACPI on ARM64?

- Grant already posted a blog about this, and stated clearly
why we need ACPI on ARM64:

http://www.secretlab.ca/archives/151


2. What we need to do before the arm64 ACPI core patches
could be merged into the kernel?

- Al Stone posted a TODO list and updates v2 for the
progress we made:
http://www.spinics.net/lists/arm-kernel/msg390069.html

- so from the progress we can see that we already finished
most of the items, and _OSI we got a plan to fix it, RFC
patch is on the way.


This patch set was tested on FVP by Fuwei, and booted ok as expected.
(No functional change since last version)

Thanks
Hanjun

[Hanjun Guo]

Introduce ACPI_IRQ_MODEL_GIC which is needed for ARM64 as GIC is
used, and then register device's gsi with the core IRQ subsystem.

acpi_register_gsi() is similar to DT based irq_of_parse_and_map(),
since gsi is unique in the system, so use hwirq number directly
for the mapping.

Originally-by: Amit Daniel Kachhap <amit....@samsung.com>

Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
Tested-by: Yijing Wang <wangy...@huawei.com>

Signed-off-by: Hanjun Guo <hanju...@linaro.org>
---

arch/arm64/kernel/acpi.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++
drivers/acpi/bus.c | 3 ++
include/linux/acpi.h | 1 +
3 files changed, 77 insertions(+)

diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
index 0b7c3a6..c3e24c4 100644
--- a/arch/arm64/kernel/acpi.c
+++ b/arch/arm64/kernel/acpi.c
@@ -37,6 +37,12 @@ EXPORT_SYMBOL(acpi_pci_disabled);
static int enabled_cpus; /* Processors (GICC) with enabled flag in MADT */

/*
+ * Since we're on ARM, the default interrupt routing model
+ * clearly has to be GIC.
+ */
+enum acpi_irq_model_id acpi_irq_model = ACPI_IRQ_MODEL_GIC;
+
+/*
* __acpi_map_table() will be called before page_init(), so early_ioremap()
* or early_memremap() should be called here to for ACPI table mapping.
*/
@@ -184,6 +190,73 @@ void __init acpi_smp_init_cpus(void)
pr_info("%d CPUs enabled, %d CPUs total\n", enabled_cpus, total_cpus);
}

+int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
+{
+ *irq = irq_find_mapping(NULL, gsi);

+
+ return 0;
+}

+EXPORT_SYMBOL_GPL(acpi_gsi_to_irq);
+
+/*
+ * success: return IRQ number (>0)
+ * failure: return =< 0
+ */
+int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity)
+{
+ unsigned int irq;
+ unsigned int irq_type;
+
+ /*
+ * ACPI have no bindings to indicate SPI or PPI, so we
+ * use different mappings from DT in ACPI.
+ *
+ * For FDT
+ * PPI interrupt: in the range [0, 15];
+ * SPI interrupt: in the range [0, 987];
+ *
+ * For ACPI, GSI should be unique so using
+ * the hwirq directly for the mapping:
+ * PPI interrupt: in the range [16, 31];
+ * SPI interrupt: in the range [32, 1019];
+ */
+
+ if (trigger == ACPI_EDGE_SENSITIVE &&
+ polarity == ACPI_ACTIVE_LOW)
+ irq_type = IRQ_TYPE_EDGE_FALLING;
+ else if (trigger == ACPI_EDGE_SENSITIVE &&
+ polarity == ACPI_ACTIVE_HIGH)
+ irq_type = IRQ_TYPE_EDGE_RISING;
+ else if (trigger == ACPI_LEVEL_SENSITIVE &&
+ polarity == ACPI_ACTIVE_LOW)
+ irq_type = IRQ_TYPE_LEVEL_LOW;
+ else if (trigger == ACPI_LEVEL_SENSITIVE &&
+ polarity == ACPI_ACTIVE_HIGH)
+ irq_type = IRQ_TYPE_LEVEL_HIGH;
+ else
+ irq_type = IRQ_TYPE_NONE;
+
+ /*
+ * Since only one GIC is supported in ACPI 5.0, we can
+ * create mapping refer to the default domain
+ */
+ irq = irq_create_mapping(NULL, gsi);
+ if (!irq)
+ return irq;
+
+ /* Set irq type if specified and different than the current one */
+ if (irq_type != IRQ_TYPE_NONE &&
+ irq_type != irq_get_trigger_type(irq))
+ irq_set_irq_type(irq, irq_type);
+ return irq;
+}
+EXPORT_SYMBOL_GPL(acpi_register_gsi);
+
+void acpi_unregister_gsi(u32 gsi)
+{
+}
+EXPORT_SYMBOL_GPL(acpi_unregister_gsi);
+
static int __init acpi_parse_fadt(struct acpi_table_header *table)
{
struct acpi_table_fadt *fadt = (struct acpi_table_fadt *)table;
diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
index 8b67bd0..c412fdb 100644
--- a/drivers/acpi/bus.c
+++ b/drivers/acpi/bus.c
@@ -448,6 +448,9 @@ static int __init acpi_bus_init_irq(void)
case ACPI_IRQ_MODEL_IOSAPIC:
message = "IOSAPIC";
break;
+ case ACPI_IRQ_MODEL_GIC:
+ message = "GIC";
+ break;
case ACPI_IRQ_MODEL_PLATFORM:
message = "platform specific model";
break;
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index d459cd1..87f365e 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -72,6 +72,7 @@ enum acpi_irq_model_id {
ACPI_IRQ_MODEL_IOAPIC,
ACPI_IRQ_MODEL_IOSAPIC,
ACPI_IRQ_MODEL_PLATFORM,
+ ACPI_IRQ_MODEL_GIC,
ACPI_IRQ_MODEL_COUNT
};

--
1.9.1

[Hanjun Guo]

MADT contains the information for MPIDR which is essential for
SMP initialization, parse the GIC cpu interface structures to
get the MPIDR value and map it to cpu_logical_map(), and add
enabled cpu with valid MPIDR into cpu_possible_map.

ACPI 5.1 only has two explicit methods to boot up SMP, PSCI and
Parking protocol, but the Parking protocol is only specified for
ARMv7 now, so make PSCI as the only way for the SMP boot protocol
before some updates for the ACPI spec or the Parking protocol spec.

Parking protocol patches for SMP boot will be sent to upstream when
the new version of Parking protocol is ready.

Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
Tested-by: Yijing Wang <wangy...@huawei.com>
Signed-off-by: Hanjun Guo <hanju...@linaro.org>

Signed-off-by: Tomasz Nowicki <tomasz....@linaro.org>
---

arch/arm64/include/asm/acpi.h | 2 +
arch/arm64/include/asm/cpu_ops.h | 1 +
arch/arm64/include/asm/smp.h | 5 +-
arch/arm64/kernel/acpi.c | 150 ++++++++++++++++++++++++++++++++++++++-
arch/arm64/kernel/cpu_ops.c | 7 +-
arch/arm64/kernel/setup.c | 7 +-
arch/arm64/kernel/smp.c | 2 +-
7 files changed, 165 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h
index 221ff15..c82d4a1 100644
--- a/arch/arm64/include/asm/acpi.h
+++ b/arch/arm64/include/asm/acpi.h
@@ -58,11 +58,13 @@ static inline bool acpi_has_cpu_in_madt(void)

}

static inline void arch_fix_phys_package_id(int num, u32 slot) { }

+void __init acpi_smp_init_cpus(void);

#else
static inline void disable_acpi(void) { }

static inline bool acpi_psci_present(void) { return false; }

static inline bool acpi_psci_use_hvc(void) { return false; }

+static inline void acpi_smp_init_cpus(void) { }

#endif /* CONFIG_ACPI */

#endif /*_ASM_ACPI_H*/

diff --git a/arch/arm64/include/asm/cpu_ops.h b/arch/arm64/include/asm/cpu_ops.h
index 6f8e2ef..5615970 100644
--- a/arch/arm64/include/asm/cpu_ops.h
+++ b/arch/arm64/include/asm/cpu_ops.h
@@ -66,5 +66,6 @@ struct cpu_operations {
extern const struct cpu_operations *cpu_ops[NR_CPUS];
int __init cpu_read_ops(struct device_node *dn, int cpu);
void __init cpu_read_bootcpu_ops(void);
+const struct cpu_operations *cpu_get_ops(const char *name);

#endif /* ifndef __ASM_CPU_OPS_H */
diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h
index 780f82c..bf22650 100644
--- a/arch/arm64/include/asm/smp.h
+++ b/arch/arm64/include/asm/smp.h
@@ -39,9 +39,10 @@ extern void show_ipi_list(struct seq_file *p, int prec);
extern void handle_IPI(int ipinr, struct pt_regs *regs);

/*
- * Setup the set of possible CPUs (via set_cpu_possible)
+ * Discover the set of possible CPUs and determine their
+ * SMP operations.
*/
-extern void smp_init_cpus(void);
+extern void of_smp_init_cpus(void);

/*
* Provide a function to raise an IPI cross call on CPUs in callmap.
diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
index 4177758..55d99d9 100644
--- a/arch/arm64/kernel/acpi.c
+++ b/arch/arm64/kernel/acpi.c
@@ -24,6 +24,10 @@
#include <linux/bootmem.h>
#include <linux/smp.h>

+#include <asm/smp_plat.h>
+#include <asm/cputype.h>
+#include <asm/cpu_ops.h>
+
int acpi_noirq; /* skip ACPI IRQ initialization */
int acpi_disabled;
EXPORT_SYMBOL(acpi_disabled);
@@ -31,6 +35,8 @@ EXPORT_SYMBOL(acpi_disabled);
int acpi_pci_disabled; /* skip ACPI PCI scan and IRQ initialization */
EXPORT_SYMBOL(acpi_pci_disabled);

+static int enabled_cpus; /* Processors (GICC) with enabled flag in MADT */
+

/*
* __acpi_map_table() will be called before page_init(), so early_ioremap()
* or early_memremap() should be called here to for ACPI table mapping.

@@ -51,6 +57,134 @@ void __init __acpi_unmap_table(char *map, unsigned long size)
early_memunmap(map, size);
}

+/**
+ * acpi_map_gic_cpu_interface - generates a logical cpu number
+ * and map to MPIDR represented by GICC structure
+ * @mpidr: CPU's hardware id to register, MPIDR represented in MADT
+ * @enabled: this cpu is enabled or not
+ *
+ * Returns the logical cpu number which maps to MPIDR
+ */
+static int acpi_map_gic_cpu_interface(u64 mpidr, u8 enabled)
+{
+ int cpu;
+
+ if (mpidr == INVALID_HWID) {
+ pr_info("Skip MADT cpu entry with invalid MPIDR\n");

+ return -EINVAL;
+ }
+

+ total_cpus++;
+ if (!enabled)
+ return -EINVAL;
+
+ if (enabled_cpus >= NR_CPUS) {
+ pr_warn("NR_CPUS limit of %d reached, Processor %d/0x%llx ignored.\n",
+ NR_CPUS, total_cpus, mpidr);

+ return -EINVAL;
+ }
+

+ /* No need to check duplicate MPIDRs for the first CPU */
+ if (enabled_cpus) {
+ /*
+ * Duplicate MPIDRs are a recipe for disaster. Scan
+ * all initialized entries and check for
+ * duplicates. If any is found just ignore the CPU.
+ */
+ for_each_possible_cpu(cpu) {
+ if (cpu_logical_map(cpu) == mpidr) {
+ pr_err("Firmware bug, duplicate CPU MPIDR: 0x%llx in MADT\n",
+ mpidr);

+ return -EINVAL;
+ }
+ }
+

+ /* allocate a logical cpu id for the new comer */
+ cpu = cpumask_next_zero(-1, cpu_possible_mask);
+ } else {
+ /*
+ * First GICC entry must be BSP as ACPI spec said
+ * in section 5.2.12.15
+ */
+ if (cpu_logical_map(0) != mpidr) {
+ pr_err("First GICC entry with MPIDR 0x%llx is not BSP\n",
+ mpidr);
+ return -EINVAL;
+ }
+
+ /*
+ * boot_cpu_init() already hold bit 0 in cpu_present_mask
+ * for BSP, no need to allocate again.
+ */
+ cpu = 0;
+ }
+
+ /* CPU 0 was already initialized */
+ if (cpu) {
+ cpu_ops[cpu] = cpu_get_ops(acpi_psci_present() ? "psci" : NULL);
+ if (!cpu_ops[cpu])
+ return -EINVAL;
+
+ if (cpu_ops[cpu]->cpu_init(NULL, cpu))
+ return -EOPNOTSUPP;
+
+ /* map the logical cpu id to cpu MPIDR */
+ cpu_logical_map(cpu) = mpidr;
+
+ set_cpu_possible(cpu, true);
+ } else {
+ /* get cpu0's ops, no need to return if ops is null */
+ cpu_ops[0] = cpu_get_ops(acpi_psci_present() ? "psci" : NULL);
+ }
+
+ enabled_cpus++;
+ return cpu;

+}
+
+static int __init

+acpi_parse_gic_cpu_interface(struct acpi_subtable_header *header,

+ const unsigned long end)
+{
+ struct acpi_madt_generic_interrupt *processor;
+

+ processor = (struct acpi_madt_generic_interrupt *)header;
+
+ if (BAD_MADT_ENTRY(processor, end))
+ return -EINVAL;
+

+ acpi_table_print_madt_entry(header);
+
+ acpi_map_gic_cpu_interface(processor->arm_mpidr & MPIDR_HWID_BITMASK,
+ processor->flags & ACPI_MADT_ENABLED);

+
+ return 0;
+}
+

+/* Parse GIC cpu interface entries in MADT for SMP init */
+void __init acpi_smp_init_cpus(void)
+{
+ int count;
+
+ /*
+ * do a partial walk of MADT to determine how many CPUs
+ * we have including disabled CPUs, and get information
+ * we need for SMP init
+ */
+ count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
+ acpi_parse_gic_cpu_interface, 0);
+
+ if (!count) {
+ pr_err("No GIC CPU interface entries present\n");
+ return;
+ } else if (count < 0) {
+ pr_err("Error parsing GIC CPU interface entry\n");
+ return;
+ }
+
+ /* Make boot-up look pretty */
+ pr_info("%d CPUs enabled, %d CPUs total\n", enabled_cpus, total_cpus);
+}

+
static int __init acpi_parse_fadt(struct acpi_table_header *table)
{
struct acpi_table_fadt *fadt = (struct acpi_table_fadt *)table;

@@ -62,8 +196,20 @@ static int __init acpi_parse_fadt(struct acpi_table_header *table)
* to get arm boot flags, or we will disable ACPI.
*/
if (table->revision > 5 ||
- (table->revision == 5 && fadt->minor_revision >= 1))
- return 0;
+ (table->revision == 5 && fadt->minor_revision >= 1)) {
+ /*
+ * ACPI 5.1 only has two explicit methods to boot up SMP,
+ * PSCI and Parking protocol, but the Parking protocol is
+ * only specified for ARMv7 now, so make PSCI as the only
+ * way for the SMP boot protocol before some updates for
+ * the ACPI spec or the Parking protocol spec.
+ */
+ if (acpi_psci_present())
+ return 0;
+
+ pr_warn("No PSCI support, will not bring up secondary CPUs\n");
+ return -EOPNOTSUPP;
+ }

pr_warn("Unsupported FADT revision %d.%d, should be 5.1+, will disable ACPI\n",
table->revision, fadt->minor_revision);
diff --git a/arch/arm64/kernel/cpu_ops.c b/arch/arm64/kernel/cpu_ops.c
index cce9524..1ea7b9f 100644
--- a/arch/arm64/kernel/cpu_ops.c
+++ b/arch/arm64/kernel/cpu_ops.c
@@ -27,7 +27,7 @@ extern const struct cpu_operations cpu_psci_ops;

const struct cpu_operations *cpu_ops[NR_CPUS];

-static const struct cpu_operations *supported_cpu_ops[] __initconst = {
+static const struct cpu_operations *supported_cpu_ops[] = {
#ifdef CONFIG_SMP
&smp_spin_table_ops,
#endif
@@ -35,10 +35,13 @@ static const struct cpu_operations *supported_cpu_ops[] __initconst = {
NULL,
};

-static const struct cpu_operations * __init cpu_get_ops(const char *name)
+const struct cpu_operations *cpu_get_ops(const char *name)
{
const struct cpu_operations **ops = supported_cpu_ops;

+ if (!name)
+ return NULL;
+
while (*ops) {
if (!strcmp(name, (*ops)->name))
return *ops;
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index ef5b1e1..54e39e3 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -414,13 +414,16 @@ void __init setup_arch(char **cmdline_p)
if (acpi_disabled) {
unflatten_device_tree();
psci_dt_init();
+ cpu_read_bootcpu_ops();
+#ifdef CONFIG_SMP
+ of_smp_init_cpus();
+#endif
} else {
psci_acpi_init();
+ acpi_smp_init_cpus();
}

- cpu_read_bootcpu_ops();
#ifdef CONFIG_SMP
- smp_init_cpus();
smp_build_mpidr_hash();
#endif

diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 7ae6ee0..5aaf5a4 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -323,7 +323,7 @@ void __init smp_prepare_boot_cpu(void)
* cpu logical map array containing MPIDR values related to logical
* cpus. Assumes that cpu_logical_map(0) has already been initialized.
*/
-void __init smp_init_cpus(void)
+void __init of_smp_init_cpus(void)
{
struct device_node *dn = NULL;
unsigned int i, cpu = 1;
--
1.9.1

[Hanjun Guo]

From: Al Stone <al.s...@linaro.org>

Introduce one early parameters "off" and "force" for "acpi", acpi=off
will be the default behavior for ARM64, so introduce acpi=force to
enable ACPI on ARM64.

Disable ACPI before early parameters parsed, and enable it to pass
"acpi=force" if people want use ACPI on ARM64. This ensures DT be
the prefer one if ACPI table and DT both are provided at this moment.

Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
Tested-by: Yijing Wang <wangy...@huawei.com>

Signed-off-by: Al Stone <al.s...@linaro.org>
Signed-off-by: Graeme Gregory <graeme....@linaro.org>

Signed-off-by: Hanjun Guo <hanju...@linaro.org>
---

Documentation/kernel-parameters.txt | 3 ++-
arch/arm64/include/asm/acpi.h | 9 +++++++++
arch/arm64/kernel/acpi.c | 17 +++++++++++++++++
arch/arm64/kernel/setup.c | 3 +++
4 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 4df73da..4adfd50 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -165,7 +165,7 @@ multipliers 'Kilo', 'Mega', and 'Giga', equalling 2^10, 2^20, and 2^30
bytes respectively. Such letter suffixes can also be entirely omitted.


- acpi= [HW,ACPI,X86]
+ acpi= [HW,ACPI,X86,ARM64]
Advanced Configuration and Power Interface
Format: { force | off | strict | noirq | rsdt }
force -- enable ACPI if default was off
@@ -175,6 +175,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
strictly ACPI specification compliant.
rsdt -- prefer RSDT over (default) XSDT
copy_dsdt -- copy DSDT to memory
+ For ARM64, ONLY "acpi=off" or "acpi=force" are available

See also Documentation/power/runtime_pm.txt, pci=noacpi

diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h
index 8b837ab..496c33b 100644
--- a/arch/arm64/include/asm/acpi.h
+++ b/arch/arm64/include/asm/acpi.h
@@ -26,6 +26,13 @@ static inline void disable_acpi(void)
acpi_noirq = 1;
}

+static inline void enable_acpi(void)
+{
+ acpi_disabled = 0;
+ acpi_pci_disabled = 0;
+ acpi_noirq = 0;
+}

+
/*
* It's used from ACPI core in kdump to boot UP system with SMP kernel,
* with this check the ACPI core will not override the CPU index

@@ -40,6 +47,8 @@ static inline bool acpi_has_cpu_in_madt(void)

static inline void arch_fix_phys_package_id(int num, u32 slot) { }

+#else
+static inline void disable_acpi(void) { }

#endif /* CONFIG_ACPI */

#endif /*_ASM_ACPI_H*/

diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
index 9252f72..39a1655 100644
--- a/arch/arm64/kernel/acpi.c
+++ b/arch/arm64/kernel/acpi.c
@@ -67,3 +67,20 @@ void __init acpi_boot_table_init(void)
if (acpi_table_init())
disable_acpi();
}
+
+static int __init parse_acpi(char *arg)
+{
+ if (!arg)
+ return -EINVAL;
+
+ /* "acpi=off" disables both ACPI table parsing and interpreter */
+ if (strcmp(arg, "off") == 0)
+ disable_acpi();
+ else if (strcmp(arg, "force") == 0) /* force ACPI to be enabled */
+ enable_acpi();
+ else
+ return -EINVAL; /* Core will print when we return error */

+
+ return 0;
+}

+early_param("acpi", parse_acpi);
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index 726b019..4580ed3 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -62,6 +62,7 @@
#include <asm/memblock.h>
#include <asm/psci.h>
#include <asm/efi.h>
+#include <asm/acpi.h>

unsigned int processor_id;
EXPORT_SYMBOL(processor_id);
@@ -388,6 +389,8 @@ void __init setup_arch(char **cmdline_p)
early_fixmap_init();
early_ioremap_init();

+ disable_acpi();
+
parse_early_param();

/*
--
1.9.1

[Hanjun Guo]

From: Al Stone <al.s...@linaro.org>

As we want to get ACPI tables to parse and then use the information
for system initialization, we should get the RSDP (Root System
Description Pointer) first, it then locates Extended Root Description
Table (XSDT) which contains all the 64-bit physical address that
pointer to other boot-time tables.

Introduce acpi.c and its related head file in this patch to provide
fundamental needs of extern variables and functions for ACPI core,
and then get boot-time tables as needed.
- asm/acenv.h for arch specific ACPICA environments and
implementation, It is needed unconditionally by ACPI core;
- asm/acpi.h for arch specific variables and functions needed by
ACPI driver core;
- acpi.c for ARM64 related ACPI implementation for ACPI driver
core;

acpi_boot_table_init() is introduced to get RSDP and boot-time tables,
it will be called in setup_arch() before paging_init(), so we should
use eary_memremap() mechanism here to get the RSDP and all the table
pointers.

Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
Tested-by: Yijing Wang <wangy...@huawei.com>
Signed-off-by: Al Stone <al.s...@linaro.org>
Signed-off-by: Graeme Gregory <graeme....@linaro.org>

Signed-off-by: Tomasz Nowicki <tomasz....@linaro.org>

Signed-off-by: Hanjun Guo <hanju...@linaro.org>
---

arch/arm64/include/asm/acenv.h | 18 +++++++++++
arch/arm64/include/asm/acpi.h | 45 +++++++++++++++++++++++++++
arch/arm64/kernel/Makefile | 1 +
arch/arm64/kernel/acpi.c | 69 ++++++++++++++++++++++++++++++++++++++++++
arch/arm64/kernel/setup.c | 4 +++
5 files changed, 137 insertions(+)
create mode 100644 arch/arm64/include/asm/acenv.h
create mode 100644 arch/arm64/include/asm/acpi.h
create mode 100644 arch/arm64/kernel/acpi.c

diff --git a/arch/arm64/include/asm/acenv.h b/arch/arm64/include/asm/acenv.h
new file mode 100644
index 0000000..b49166f
--- /dev/null
+++ b/arch/arm64/include/asm/acenv.h
@@ -0,0 +1,18 @@
+/*
+ * ARM64 specific ACPICA environments and implementation
+ *

+ * Copyright (C) 2014, Linaro Ltd.

+ * Author: Hanjun Guo <hanju...@linaro.org>

+ * Author: Graeme Gregory <graeme....@linaro.org>

+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+

+#ifndef _ASM_ACENV_H
+#define _ASM_ACENV_H
+
+/* It is required unconditionally by ACPI core, update it when needed. */
+
+#endif /* _ASM_ACENV_H */
diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h
new file mode 100644
index 0000000..8b837ab
--- /dev/null
+++ b/arch/arm64/include/asm/acpi.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2013-2014, Linaro Ltd.
+ * Author: Al Stone <al.s...@linaro.org>

+ * Author: Graeme Gregory <graeme....@linaro.org>

+ * Author: Hanjun Guo <hanju...@linaro.org>

+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as

+ * published by the Free Software Foundation;
+ */
+
+#ifndef _ASM_ACPI_H
+#define _ASM_ACPI_H
+
+/* Basic configuration for ACPI */
+#ifdef CONFIG_ACPI
+#define acpi_strict 1 /* No out-of-spec workarounds on ARM64 */
+extern int acpi_disabled;
+extern int acpi_noirq;
+extern int acpi_pci_disabled;
+
+static inline void disable_acpi(void)
+{
+ acpi_disabled = 1;
+ acpi_pci_disabled = 1;
+ acpi_noirq = 1;
+}
+
+/*
+ * It's used from ACPI core in kdump to boot UP system with SMP kernel,
+ * with this check the ACPI core will not override the CPU index
+ * obtained from GICC with 0 and not print some error message as well.
+ * Since MADT must provide at least one GICC structure for GIC
+ * initialization, CPU will be always available in MADT on ARM64.
+ */
+static inline bool acpi_has_cpu_in_madt(void)
+{
+ return true;
+}
+
+static inline void arch_fix_phys_package_id(int num, u32 slot) { }
+
+#endif /* CONFIG_ACPI */
+
+#endif /*_ASM_ACPI_H*/
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index eaa77ed..8bdc6bd 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -34,6 +34,7 @@ arm64-obj-$(CONFIG_KGDB) += kgdb.o
arm64-obj-$(CONFIG_EFI) += efi.o efi-stub.o efi-entry.o
arm64-obj-$(CONFIG_PCI) += pci.o
arm64-obj-$(CONFIG_ARMV8_DEPRECATED) += armv8_deprecated.o
+arm64-obj-$(CONFIG_ACPI) += acpi.o

obj-y += $(arm64-obj-y) vdso/
obj-m += $(arm64-obj-m)
diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
new file mode 100644
index 0000000..9252f72
--- /dev/null
+++ b/arch/arm64/kernel/acpi.c
@@ -0,0 +1,69 @@
+/*
+ * ARM64 Specific Low-Level ACPI Boot Support
+ *
+ * Copyright (C) 2013-2014, Linaro Ltd.
+ * Author: Al Stone <al.s...@linaro.org>

+ * Author: Graeme Gregory <graeme....@linaro.org>

+ * Author: Hanjun Guo <hanju...@linaro.org>

+ * Author: Tomasz Nowicki <tomasz....@linaro.org>

+ * Author: Naresh Bhat <nares...@linaro.org>

+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+

+#include <linux/init.h>
+#include <linux/acpi.h>
+#include <linux/cpumask.h>
+#include <linux/memblock.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/bootmem.h>
+#include <linux/smp.h>
+
+int acpi_noirq; /* skip ACPI IRQ initialization */
+int acpi_disabled;
+EXPORT_SYMBOL(acpi_disabled);
+
+int acpi_pci_disabled; /* skip ACPI PCI scan and IRQ initialization */
+EXPORT_SYMBOL(acpi_pci_disabled);
+
+/*
+ * __acpi_map_table() will be called before page_init(), so early_ioremap()
+ * or early_memremap() should be called here to for ACPI table mapping.
+ */
+char *__init __acpi_map_table(unsigned long phys, unsigned long size)
+{
+ if (!phys || !size)
+ return NULL;
+
+ return early_memremap(phys, size);
+}
+
+void __init __acpi_unmap_table(char *map, unsigned long size)
+{
+ if (!map || !size)
+ return;
+
+ early_memunmap(map, size);
+}
+
+/*
+ * acpi_boot_table_init() called from setup_arch(), always.
+ * 1. find RSDP and get its address, and then find XSDT
+ * 2. extract all tables and checksums them all
+ *
+ * We can parse ACPI boot-time tables such as MADT after
+ * this function is called.
+ */
+void __init acpi_boot_table_init(void)
+{
+ /* If acpi_disabled, bail out */

+ if (acpi_disabled)
+ return;
+

+ /* Initialize the ACPI boot-time table parser. */
+ if (acpi_table_init())
+ disable_acpi();
+}
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index 20fe293..726b019 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -17,6 +17,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/

+#include <linux/acpi.h>
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/stddef.h>
@@ -398,6 +399,9 @@ void __init setup_arch(char **cmdline_p)
efi_init();
arm64_memblock_init();

+ /* Parse the ACPI tables for possible boot-time configuration */
+ acpi_boot_table_init();
+
paging_init();
request_standard_resources();

--
1.9.1

[Hanjun Guo]

FADT Major.Minor version was introduced in ACPI 5.1, it is the same
as ACPI version.

In ACPI 5.1, some major gaps are fixed for ARM, such as updates in
MADT table for GIC and SMP init, without those updates, we can not
get the MPIDR for SMP init, and GICv2/3 related init information, so
we can't boot arm64 ACPI properly with table versions predating 5.1.

If firmware provides ACPI tables with ACPI version less than 5.1,
OS will be messed up with those information and have no way to init
smp and GIC, so disable ACPI if we get an FADT table with version
less that 5.1.

Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
Tested-by: Yijing Wang <wangy...@huawei.com>

Signed-off-by: Hanjun Guo <hanju...@linaro.org>
---

arch/arm64/kernel/acpi.c | 31 ++++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
index 39a1655..4177758 100644
--- a/arch/arm64/kernel/acpi.c
+++ b/arch/arm64/kernel/acpi.c
@@ -13,6 +13,8 @@

* published by the Free Software Foundation.

*/

+#define pr_fmt(fmt) "ACPI: " fmt
+
#include <linux/init.h>
#include <linux/acpi.h>
#include <linux/cpumask.h>
@@ -49,10 +51,32 @@ void __init __acpi_unmap_table(char *map, unsigned long size)
early_memunmap(map, size);
}

+static int __init acpi_parse_fadt(struct acpi_table_header *table)
+{
+ struct acpi_table_fadt *fadt = (struct acpi_table_fadt *)table;
+
+ /*
+ * Revision in table header is the FADT Major revision,
+ * and there is a minor revision of FADT which was introduced
+ * by ACPI 5.1, we only deal with ACPI 5.1 or newer revision
+ * to get arm boot flags, or we will disable ACPI.
+ */
+ if (table->revision > 5 ||

+ (table->revision == 5 && fadt->minor_revision >= 1))

+ return 0;
+

+ pr_warn("Unsupported FADT revision %d.%d, should be 5.1+, will disable ACPI\n",

+ table->revision, fadt->minor_revision);
+ disable_acpi();
+

+ return -EINVAL;
+}
+
/*

* acpi_boot_table_init() called from setup_arch(), always.

* 1. find RSDP and get its address, and then find XSDT

* 2. extract all tables and checksums them all

+ * 3. check ACPI FADT revision
*

* We can parse ACPI boot-time tables such as MADT after

* this function is called.

@@ -64,8 +88,13 @@ void __init acpi_boot_table_init(void)
return;

/* Initialize the ACPI boot-time table parser. */

- if (acpi_table_init())
+ if (acpi_table_init()) {
disable_acpi();
+ return;
+ }
+
+ if (acpi_table_parse(ACPI_SIG_FADT, acpi_parse_fadt))
+ pr_err("Can't find FADT or error happened during parsing FADT\n");

}

static int __init parse_acpi(char *arg)

--
1.9.1

[Hanjun Guo]

From: Mark Salter <msa...@redhat.com>

Commit 0e63ea48b4d8 (arm64/efi: add missing call to early_ioremap_reset())
added a missing call to early_ioremap_reset(). This triggers a BUG if code
tries using early_ioremap() after the early_ioremap_reset(). This is a
problem for some ACPI code which needs short-lived temporary mappings
after paging_init() but before acpi_early_init() in start_kernel(). This
patch adds definitions for the __late_set_fixmap() and __late_clear_fixmap()
which avoids the BUG by allowing later use of early_ioremap().

Signed-off-by: Mark Salter <msa...@redhat.com>
CC: Leif Lindholm <leif.l...@linaro.org>
CC: Ard Biesheuvel <ard.bie...@linaro.org>
[hj: update the change log]

Signed-off-by: Hanjun Guo <hanju...@linaro.org>
---

arch/arm64/include/asm/fixmap.h | 3 +++
1 file changed, 3 insertions(+)

diff --git a/arch/arm64/include/asm/fixmap.h b/arch/arm64/include/asm/fixmap.h
index 9ef6eca..e629c70 100644
--- a/arch/arm64/include/asm/fixmap.h
+++ b/arch/arm64/include/asm/fixmap.h
@@ -61,6 +61,9 @@ void __init early_fixmap_init(void);

#define __early_set_fixmap __set_fixmap

+#define __late_set_fixmap __set_fixmap
+#define __late_clear_fixmap(idx) __set_fixmap((idx), 0, FIXMAP_PAGE_CLEAR)
+
extern void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot);

#include <asm-generic/fixmap.h>
--
1.9.1

[Hanjun Guo]

From: Graeme Gregory <graeme....@linaro.org>

If the early boot methods of acpi are happy that we have valid ACPI
tables and acpi=force has been passed, then do not unflat devicetree
effectively disabling further hardware probing from DT.

Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
Tested-by: Yijing Wang <wangy...@huawei.com>

Signed-off-by: Graeme Gregory <graeme....@linaro.org>

Signed-off-by: Hanjun Guo <hanju...@linaro.org>
---

arch/arm64/kernel/setup.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index 4580ed3..5d139e1 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -411,7 +411,8 @@ void __init setup_arch(char **cmdline_p)
efi_idmap_init();
early_ioremap_reset();

- unflatten_device_tree();
+ if (acpi_disabled)
+ unflatten_device_tree();

psci_init();

--
1.9.1

[Grant Likely]

On Wed, Jan 14, 2015 at 3:04 PM, Hanjun Guo <hanju...@linaro.org> wrote:
> Hi,
>
> This is the v7 of ACPI core patches for ARM64 based on ACPI 5.1

Hi Catalin and Will,

I'll get right to the point: Can we please have this series queued up
for v3.20? I really think we've hit the point where it is more
valuable to merge it (or at least prepare to merge it) rather than
keeping it out of mainline.

First, I think we've agreed that the patches themselves are fine. The
remaining objections are based on maturity and whether or not we can
handle long term support. At this point, for all of the items on Al's
ACPI todo list, we've either got solutions for the problems, or solid
plans on how it is going to get solved (I'll go through each item one
by one at the end of this email). I won't claim that list is
exhaustive though. Please shout if there are new issues that need to
be added.

Second, real platforms using ACPI are showing up in various places.
Platforms are available from both APM and AMD. Huawei have spoken up
with test results that the patches boot on their unreleased platform
(Huawei needs GICv3 extensions, but otherwise it works). The
commercial products that are being built right now are being built
around these patches. Fedora Rawhide has picked them up also.

Continuing to keep the patches out I think is having the opposite
effect from what is desired. Catalin, you've told me a few times that
saying "no" is the only leverage you have to keeping crap drivers out
of the kernel until things mature, and by extension influence how
firmware gets implemented. However, as far as drivers are concerned,
there is nothing stopping maintainers from picking up ACPI drivers for
ARM hardware regardless of whether or not the core ARM code is merged.
If a driver depends on CONFIG_ACPI, and if the code seems to look
good, there is nothing preventing it from being merged. There are
already ARM related ACPI patches going into mainline.

For example: https://lkml.org/lkml/2014/12/25/120

Instead, keeping these patches out means that hardware is getting
developed and tested against Fedora, early access RHEL and Linaro
kernels. It means that we're abdicating on any influence mainline has
over how those platforms are developed. The longer these patches stay
out of mainline, the greater the potential for delta between what is
in the vendor kernels and what we accept into mainline.

The other concern may be keeping crap out of the core ARM code, but I
really don't think that will be an issue. The two of you still have
complete control over arch/arm64 and I fully expect crap code will be
aggressively NAKed whether or not it is ACPI related. All that merging
this series does is lays down a foundation of functionality on the
stuff we are pretty confident is correct. It keeps the delta between
mainline and the development code small and restricted to only the
bits that are still in flux.

Finally, keeping them out has the practical effect of causing extra
work to continually rebase them, while potentially running into new
conflicts and bugs, for little if any real benefit. Whereas getting
them into linux-next starts giving us some feedback on conflicts with
other things that are being queued up for mainline. Not to mention
reviewer fatigue having to go over the same set of patches again and
again.

Right now we're at -rc4. We'll be at -rc5 this weekend, and quite
possibly have a new merge window right at the start of Connect.
Queuing these patches up now isn't even a 100% commitment for you to
ask Linus to pull them. We can have further discussions at Connect. If
you're still not satisfied then drop them out again for another cycle.
However, if they aren't queued up now, then we're looking at mid-June
before they show up in a mainline kernel release.

As promised earlier, I said that I'd go through the todo list items.
Here they are with discussion:
1. Define how Aarch64 OS identifies itself to firmware
- We've pretty much settled on dropping the _OSI interface entirely,
which is trivial to do. All of the current platforms can adapt to
this. There are still some discussions around _OSC, but given that
this is the first release there isn't anything for the platform to
differentiate on regarding features. This isn't going to affect
current platforms, but rather will be important with the release of
the next version of the ACPI spec. It shouldn't affect our ability to
merge core support

2. Linux must choose DT booting by default when offered both ACPI and
* Status: DONE, but being revisited for possible algorithmic change

3. Linux UEFI/ACPI testing tools must be made available
* Done. We're implementing more tests of course, but that is expected.

4. Set clear expectations for those providing ACPI for use with Linux
* We have a document that covers what we know so far, and will
continue to expand it. Also talking with the SBBR folks to move
relevant requirements into the SBBR doc.

5. Platform support patches need verification and review
* ACPI core works on at least the Foundation model, Juno, APM
Mustang, and AMD Seattle
* There still are driver patches being discussed. See Al's summary
for details
* As I argued above, the state of driver patches isn't going to be

6. How does the kernel handle_DSD usage?
While important, these issues are separate from whether or not to
merge the core aarch64 code. This work was defined and driven by Intel
for their embedded platforms, and it is already in mainline. Keeping
aarch64 support out isn't going to prevent drivers using it from being
merged. I don't think this should be a reason for blocking this
series.

7. Why is ACPI required?
I hope I've addressed this[1], but discussion continues.

[1] http://www.spinics.net/lists/arm-kernel/msg389955.html

[Catalin Marinas]

Hi Grant,

On Thu, Jan 15, 2015 at 04:26:20PM +0000, Grant Likely wrote:
> On Wed, Jan 14, 2015 at 3:04 PM, Hanjun Guo <hanju...@linaro.org> wrote:
> > This is the v7 of ACPI core patches for ARM64 based on ACPI 5.1
>

> I'll get right to the point: Can we please have this series queued up
> for v3.20?

Before you even ask for this, please look at the patches and realise
that there is a complete lack of Reviewed-by tags on the code (well,
apart from trivial Kconfig changes). In addition, the series touches on
other subsystems like clocksource, irqchip, acpi and I don't see any
acks from the corresponding maintainers. So even if I wanted to merge
the series, there is no way it can be done without additional
reviews/acks. On the document (last patch), I'd like to see a statement
from HP as they've been vocal in private but no public endorsement of
this doc.

I also have trouble seeing the full picture. Is there a git repository
somewhere with this series and any additional patches required for a
real hardware platform?

> I really think we've hit the point where it is more valuable to merge
> it (or at least prepare to merge it) rather than keeping it out of
> mainline.

That's pretty subjective.

> Continuing to keep the patches out I think is having the opposite
> effect from what is desired. Catalin, you've told me a few times that
> saying "no" is the only leverage you have to keeping crap drivers out
> of the kernel until things mature, and by extension influence how
> firmware gets implemented. However, as far as drivers are concerned,
> there is nothing stopping maintainers from picking up ACPI drivers for
> ARM hardware regardless of whether or not the core ARM code is merged.
> If a driver depends on CONFIG_ACPI, and if the code seems to look
> good, there is nothing preventing it from being merged. There are
> already ARM related ACPI patches going into mainline.
>
> For example: https://lkml.org/lkml/2014/12/25/120

I wasn't really referring to simple driver changes like the above but to
whole subsystems like clocks done in ACPI. My point was that before we
enable arm64 ACPI, we need to have some clear guidelines to firmware and
hardware vendors, otherwise if we don't know how to do it properly, we
shouldn't even bother (or we may end up re-creating the DT support in
ACPI; I'm not convinced that's sorted yet).

> Instead, keeping these patches out means that hardware is getting
> developed and tested against Fedora, early access RHEL and Linaro
> kernels. It means that we're abdicating on any influence mainline has
> over how those platforms are developed. The longer these patches stay
> out of mainline, the greater the potential for delta between what is
> in the vendor kernels and what we accept into mainline.

I'm not buying this argument. Putting pressure on maintainers to merge
something because Fedora or some other distro has merged them is not the
right approach. If such Linux vendors ignore arguments on the list just
for the sake of providing ACPI support, there is a high chance that they
will accept non-standard code any other time when the kernel community
disagrees.

Just to be clear, I don't block the ACPI patches for fun, reading these
long threads is not fun anymore. I don't have any religious arguments
against ACPI, longer term I see it as a first class citizen alongside
DT, but I want to make sure we do it properly and have a clear vision on
how we support it in the future. You can call this "delayed
gratification" if you want.

And it's not about code going into arch/arm64 and not even small driver
changes to enable ACPI but the longer term plans on how we reduce
(rather than eliminate) future kernel quirks because we didn't first get
to an agreement on how kernel and firmware interact. Things are getting
better and Al's to-do list is a good benchmark (more comments below).

(I have my concerns with DT as well but the requirement of compatibility
between older/newer kernels/firmware is not as strict)

> Finally, keeping them out has the practical effect of causing extra
> work to continually rebase them, while potentially running into new
> conflicts and bugs, for little if any real benefit. Whereas getting
> them into linux-next starts giving us some feedback on conflicts with
> other things that are being queued up for mainline. Not to mention
> reviewer fatigue having to go over the same set of patches again and
> again.

17 patches is really not too hard and it looks like the number is slowly
decreasing as they are picked by the corresponding maintainers.

> Right now we're at -rc4. We'll be at -rc5 this weekend, and quite
> possibly have a new merge window right at the start of Connect.
> Queuing these patches up now isn't even a 100% commitment for you to
> ask Linus to pull them. We can have further discussions at Connect. If
> you're still not satisfied then drop them out again for another cycle.
> However, if they aren't queued up now, then we're looking at mid-June
> before they show up in a mainline kernel release.

See the beginning of the email about the prerequisites for queuing
something up into linux-next.

> As promised earlier, I said that I'd go through the todo list items.
> Here they are with discussion:
> 1. Define how Aarch64 OS identifies itself to firmware
> - We've pretty much settled on dropping the _OSI interface entirely,
> which is trivial to do. All of the current platforms can adapt to
> this. There are still some discussions around _OSC, but given that
> this is the first release there isn't anything for the platform to
> differentiate on regarding features. This isn't going to affect
> current platforms, but rather will be important with the release of
> the next version of the ACPI spec. It shouldn't affect our ability to
> merge core support

I'm fine with this.

> 2. Linux must choose DT booting by default when offered both ACPI and
> * Status: DONE, but being revisited for possible algorithmic change

OK.

> 3. Linux UEFI/ACPI testing tools must be made available
> * Done. We're implementing more tests of course, but that is expected.

OK.

> 4. Set clear expectations for those providing ACPI for use with Linux
> * We have a document that covers what we know so far, and will
> continue to expand it. Also talking with the SBBR folks to move
> relevant requirements into the SBBR doc.

Moving bits of it into SBBR is a good long term plan but it should not
prevent the merging. However, I'd like to see more vendors ok'ing the
kernel document.

> 5. Platform support patches need verification and review
> * ACPI core works on at least the Foundation model, Juno, APM
> Mustang, and AMD Seattle
> * There still are driver patches being discussed. See Al's summary
> for details
> * As I argued above, the state of driver patches isn't going to be

We are still lacking here. To quote Al, "First version for AMD Seattle
has been posted to the public linaro-acpi mailing list for initial
review". Sorry but I don't follow linaro-acpi list. I don't know what's
in those patches and I can't tell which subsystems they touch, whether
maintainers agree with them. So in conclusion, I'm not confident the
arm64 hardware ACPI story looks that great yet.

As for Juno and foundation models, I don't consider them server
platforms.

> 6. How does the kernel handle_DSD usage?
> While important, these issues are separate from whether or not to
> merge the core aarch64 code. This work was defined and driven by Intel
> for their embedded platforms, and it is already in mainline. Keeping
> aarch64 support out isn't going to prevent drivers using it from being
> merged. I don't think this should be a reason for blocking this
> series.

Intel folk is coming from the other direction, relatively standard
hardware getting slightly more non-standard and they need a few bits
added in _DSD. On ARM, we have completely non-standard hardware with DT
used to describe complex topology (clocks, pin controls, voltage
regulators etc.) with a high risk that vendors see _DSD as a work around
standardising hardware or doing it properly in ACPI (whatever that
means, AML?).

> 7. Why is ACPI required?
> I hope I've addressed this[1], but discussion continues.
>
> [1] http://www.spinics.net/lists/arm-kernel/msg389955.html

That's great. I see this as a good reference for the future.

To complete the picture, we probably need a "Why *not* ACPI on ARM" blog
as well explaining when ACPI is *not* suitable (e.g. no SBSA
compliance). The arm-acpi.txt covers the ACPI requirements from the
kernel perspective and, by contrast, DT would be better suited for
certain platforms. The way you present it is that ACPI solves lots of
problems that DT doesn't but not necessarily where the ACPI limitations
are (vs DT).

--
Catalin

[Mark Langsdorf]

On 01/14/2015 09:04 AM, Hanjun Guo wrote:
> From: Al Stone <al.s...@linaro.org>
>
> Introduce one early parameters "off" and "force" for "acpi", acpi=off
> will be the default behavior for ARM64, so introduce acpi=force to
> enable ACPI on ARM64.
>
> Disable ACPI before early parameters parsed, and enable it to pass
> "acpi=force" if people want use ACPI on ARM64. This ensures DT be
> the prefer one if ACPI table and DT both are provided at this moment.
>
> Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
> Tested-by: Yijing Wang <wangy...@huawei.com>
> Signed-off-by: Al Stone <al.s...@linaro.org>
> Signed-off-by: Graeme Gregory <graeme....@linaro.org>
> Signed-off-by: Hanjun Guo <hanju...@linaro.org>
> ---

Tested-by: Mark Langsdorf <mlan...@redhat.com>

[Mark Langsdorf]

On 01/14/2015 09:04 AM, Hanjun Guo wrote:

> From: Graeme Gregory <graeme....@linaro.org>
>
> If the early boot methods of acpi are happy that we have valid ACPI
> tables and acpi=force has been passed, then do not unflat devicetree
> effectively disabling further hardware probing from DT.
>
> Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
> Tested-by: Yijing Wang <wangy...@huawei.com>
> Signed-off-by: Graeme Gregory <graeme....@linaro.org>
> Signed-off-by: Hanjun Guo <hanju...@linaro.org>
> ---

Tested-by: Mark Langsdorf <mlan...@redhat.com>

[Mark Langsdorf]

On 01/14/2015 09:04 AM, Hanjun Guo wrote:

> From: Mark Salter <msa...@redhat.com>
>
> Commit 0e63ea48b4d8 (arm64/efi: add missing call to early_ioremap_reset())
> added a missing call to early_ioremap_reset(). This triggers a BUG if code
> tries using early_ioremap() after the early_ioremap_reset(). This is a
> problem for some ACPI code which needs short-lived temporary mappings
> after paging_init() but before acpi_early_init() in start_kernel(). This
> patch adds definitions for the __late_set_fixmap() and __late_clear_fixmap()
> which avoids the BUG by allowing later use of early_ioremap().
>
> Signed-off-by: Mark Salter <msa...@redhat.com>
> CC: Leif Lindholm <leif.l...@linaro.org>
> CC: Ard Biesheuvel <ard.bie...@linaro.org>
> [hj: update the change log]
> Signed-off-by: Hanjun Guo <hanju...@linaro.org>
> ---

Tested-by: Mark Langsdorf <mlan...@redhat.com>

[Mark Langsdorf]

On 01/14/2015 09:04 AM, Hanjun Guo wrote:

> Since PCI is not required in ACPI spec and ARM can run without
> it, introduce some stub functions to make PCI optional for ACPI,
> and make ACPI core run without CONFIG_PCI on ARM64.
>
> When PCI is enabled on ARM64, ACPI core will need some PCI functions
> to make it functional, so introduce some empty functions here and
> implement it later.
>
> Since ACPI on X86 and IA64 depends on PCI and this patch only makes
> PCI optional for ARM64, it will not break anything on X86 and IA64.
>
> Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
> Tested-by: Yijing Wang <wangy...@huawei.com>
> Signed-off-by: Hanjun Guo <hanju...@linaro.org>
> ---

Tested-by: Mark Langsdorf <mlan...@redhat.com>

[Mark Langsdorf]

On 01/14/2015 09:04 AM, Hanjun Guo wrote:

Tested-by: Mark Langsdorf <mlan...@redhat.com>

[Mark Langsdorf]

On 01/14/2015 09:04 AM, Hanjun Guo wrote:

> Introduce a new function map_gicc_mpidr() to allow MPIDRs to be obtained
> from the GICC Structure introduced by ACPI 5.1.
>
> MPIDR is the CPU hardware ID as local APIC ID on x86 platform, so we use
> MPIDR not the GIC CPU interface ID to identify CPUs.
>
> Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
> Tested-by: Yijing Wang <wangy...@huawei.com>
> Signed-off-by: Hanjun Guo <hanju...@linaro.org>
> ---

Tested-by: Mark Langsdorf <mlan...@redhat.com>

[Mark Langsdorf]

On 01/14/2015 09:04 AM, Hanjun Guo wrote:

> When MADT is parsed, print GIC information to make the boot
> log look pretty:
>
> ACPI: GICC (acpi_id[0x0000] address[00000000e112f000] MPIDR[0x0] enabled)
> ACPI: GICC (acpi_id[0x0001] address[00000000e112f000] MPIDR[0x1] enabled)
> ...
> ACPI: GICC (acpi_id[0x0201] address[00000000e112f000] MPIDR[0x201] enabled)
>
> These information will be very helpful to bring up early systems to
> see if acpi_id and MPIDR are matched or not as spec defined.
>
> Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
> Tested-by: Yijing Wang <wangy...@huawei.com>
> Signed-off-by: Hanjun Guo <hanju...@linaro.org>
> Signed-off-by: Tomasz Nowicki <tomasz....@linaro.org>
> ---

Tested-by: Mark Langsdorf <mlan...@redhat.com>

[Mark Langsdorf]

On 01/14/2015 09:04 AM, Hanjun Guo wrote:

> From: Graeme Gregory <graeme....@linaro.org>
>
> There are two flags: PSCI_COMPLIANT and PSCI_USE_HVC. When set,
> the former signals to the OS that the firmware is PSCI compliant.
> The latter selects the appropriate conduit for PSCI calls by
> toggling between Hypervisor Calls (HVC) and Secure Monitor Calls
> (SMC).
>
> FADT table contains such information in ACPI 5.1, FADT table was
> parsed in ACPI table init and copy to struct acpi_gbl_FADT, so
> use the flags in struct acpi_gbl_FADT for PSCI init.
>
> Since ACPI 5.1 doesn't support self defined PSCI function IDs,
> which means that only PSCI 0.2+ is supported in ACPI.
>
> Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
> Tested-by: Yijing Wang <wangy...@huawei.com>
> Signed-off-by: Graeme Gregory <graeme....@linaro.org>
> Signed-off-by: Tomasz Nowicki <tomasz....@linaro.org>
> Signed-off-by: Hanjun Guo <hanju...@linaro.org>
> ---

Tested-by: Mark Langsdorf <mlan...@redhat.com>

[Mark Langsdorf]

On 01/14/2015 09:04 AM, Hanjun Guo wrote:

> From: Graeme Gregory <graeme....@linaro.org>
>
> ACPI 5.1 does not currently support S states for ARM64 hardware but
> ACPI code will call acpi_target_system_state() for device power
> managment, so introduce sleep-arm.c to allow other drivers to function
> until S states are defined.
>
> Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
> Tested-by: Yijing Wang <wangy...@huawei.com>
> Signed-off-by: Graeme Gregory <graeme....@linaro.org>
> Signed-off-by: Tomasz Nowicki <tomasz....@linaro.org>
> Signed-off-by: Hanjun Guo <hanju...@linaro.org>
> ---

Tested-by: Mark Langsdorf <mlan...@redhat.com>

[Mark Langsdorf]

On 01/14/2015 09:04 AM, Hanjun Guo wrote:

> FADT Major.Minor version was introduced in ACPI 5.1, it is the same
> as ACPI version.
>
> In ACPI 5.1, some major gaps are fixed for ARM, such as updates in
> MADT table for GIC and SMP init, without those updates, we can not
> get the MPIDR for SMP init, and GICv2/3 related init information, so
> we can't boot arm64 ACPI properly with table versions predating 5.1.
>
> If firmware provides ACPI tables with ACPI version less than 5.1,
> OS will be messed up with those information and have no way to init
> smp and GIC, so disable ACPI if we get an FADT table with version
> less that 5.1.
>
> Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
> Tested-by: Yijing Wang <wangy...@huawei.com>
> Signed-off-by: Hanjun Guo <hanju...@linaro.org>
> ---

Tested-by: Mark Langsdorf <mlan...@redhat.com>

[Mark Langsdorf]

On 01/14/2015 09:05 AM, Hanjun Guo wrote:
> Using the information presented by GTDT to initialize the arch
> timer (not memory-mapped).

>
> Originally-by: Amit Daniel Kachhap <amit....@samsung.com>

> Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
> Tested-by: Yijing Wang <wangy...@huawei.com>
> Signed-off-by: Hanjun Guo <hanju...@linaro.org>
> ---
Tested-by: Mark Langsdorf <mlan...@redhat.com>

[Mark Langsdorf]

On 01/14/2015 09:05 AM, Hanjun Guo wrote:

> From: Graeme Gregory <graeme....@linaro.org>
>
> Add Kconfigs to build ACPI on ARM64, and make ACPI available on ARM64.
>
> acpi_idle driver is x86/IA64 dependent now, so make CONFIG_ACPI_PROCESSOR
> depend on X86 || IA64, and implement it on ARM64 in the future.
>
> Reviewed-by: Grant Likely <grant....@linaro.org>
> Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
> Tested-by: Yijing Wang <wangy...@huawei.com>
> Signed-off-by: Graeme Gregory <graeme....@linaro.org>
> Signed-off-by: Al Stone <al.s...@linaro.org>
> Signed-off-by: Hanjun Guo <hanju...@linaro.org>
> ---

Tested-by: Mark Langsdorf <mlan...@redhat.com>

[Mark Langsdorf]

On 01/14/2015 09:05 AM, Hanjun Guo wrote:

> Introduce ACPI_IRQ_MODEL_GIC which is needed for ARM64 as GIC is
> used, and then register device's gsi with the core IRQ subsystem.
>
> acpi_register_gsi() is similar to DT based irq_of_parse_and_map(),
> since gsi is unique in the system, so use hwirq number directly
> for the mapping.
>
> Originally-by: Amit Daniel Kachhap <amit....@samsung.com>
> Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
> Tested-by: Yijing Wang <wangy...@huawei.com>
> Signed-off-by: Hanjun Guo <hanju...@linaro.org>
> ---

Tested-by: Mark Langsdorf <mlan...@redhat.com>

[Mark Langsdorf]

On 01/14/2015 09:05 AM, Hanjun Guo wrote:

> From: Tomasz Nowicki <tomasz....@linaro.org>
>
> ACPI kernel uses MADT table for proper GIC initialization. It needs to
> parse GIC related subtables, collect CPU interface and distributor
> addresses and call driver initialization function (which is hardware
> abstraction agnostic). In a similar way, FDT initialize GICv1/2.
>
> NOTE: This commit allow to initialize GICv1/2 basic functionality.
> GICv2 vitalization extension, GICv3/4 and ITS are considered as next
> steps.

>
> Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
> Tested-by: Yijing Wang <wangy...@huawei.com>

> Signed-off-by: Tomasz Nowicki <tomasz....@linaro.org>

> Signed-off-by: Hanjun Guo <hanju...@linaro.org>
> ---
Tested-by: Mark Langsdorf <mlan...@redhat.com>

[Mark Langsdorf]

On 01/14/2015 09:04 AM, Hanjun Guo wrote:

> MADT contains the information for MPIDR which is essential for
> SMP initialization, parse the GIC cpu interface structures to
> get the MPIDR value and map it to cpu_logical_map(), and add
> enabled cpu with valid MPIDR into cpu_possible_map.
>
> ACPI 5.1 only has two explicit methods to boot up SMP, PSCI and
> Parking protocol, but the Parking protocol is only specified for
> ARMv7 now, so make PSCI as the only way for the SMP boot protocol
> before some updates for the ACPI spec or the Parking protocol spec.
>
> Parking protocol patches for SMP boot will be sent to upstream when
> the new version of Parking protocol is ready.
>
> Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
> Tested-by: Yijing Wang <wangy...@huawei.com>
> Signed-off-by: Hanjun Guo <hanju...@linaro.org>
> Signed-off-by: Tomasz Nowicki <tomasz....@linaro.org>
> ---

Tested-by: Mark Langsdorf <mlan...@redhat.com>

[Mark Langsdorf]

On 01/14/2015 09:05 AM, Hanjun Guo wrote:

> From: Graeme Gregory <graeme....@linaro.org>
>
> Add documentation for the guidelines of how to use ACPI
> on ARM64.
>
> Reviewed-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
> Reviewed-by: Yi Li <phoeni...@huawei.com>

> Signed-off-by: Graeme Gregory <graeme....@linaro.org>
> Signed-off-by: Al Stone <al.s...@linaro.org>

> Signed-off-by: Hanjun Guo <hanju...@linaro.org>
> ---

There's enough here to get people started. Additional
information can be added in later patches as needed and
as we get more experience with ACPI on ARM64.

Reviewed-by: Mark Langsdorf <mlan...@redhat.com>

[Mark Langsdorf]

On 01/14/2015 09:05 AM, Hanjun Guo wrote:

> From: Al Stone <al.s...@linaro.org>
>
> ACPI reduced hardware mode is disabled by default, but ARM64
> can only run properly in ACPI hardware reduced mode, so select
> ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on ARM64.
>
> Reviewed-by: Grant Likely <grant....@linaro.org>

> Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
> Tested-by: Yijing Wang <wangy...@huawei.com>

> Signed-off-by: Al Stone <al.s...@linaro.org>
> Signed-off-by: Hanjun Guo <hanju...@linaro.org>
> ---

Tested-by: Mark Langsdorf <mlan...@redhat.com>

[Jon Masters]

On 01/14/2015 10:04 AM, Hanjun Guo wrote:
> Hi,

>
> This is the v7 of ACPI core patches for ARM64 based on ACPI 5.1
>

> updates from v6:
> - Rebased on top of 3.19-rc4, add Mack Salter's patch to use
> the early_ioremap after paging_init() for ACPI table mappings;
>
> - Two patches about converting apic_id to phys_id to make it arch
> agnostic were already merged into RC4 by Rafael.
>
> - Split patch "Parse FADT table to get PSCI flags for PSCI init"
> into two as Lorenzo's suggestion, also fix typo and lack of __init
> for psci_0_2_set_functions() which is spotted by Lorenzo.
>
> - Add Tested-by from Yijing Wang.
>
> previous version is here:
> v6: https://lkml.org/lkml/2015/1/4/40
>
> 1. Why we need ACPI on ARM64?
>
> - Grant already posted a blog about this, and stated clearly
> why we need ACPI on ARM64:
>
> http://www.secretlab.ca/archives/151
>
>
> 2. What we need to do before the arm64 ACPI core patches
> could be merged into the kernel?
>
> - Al Stone posted a TODO list and updates v2 for the
> progress we made:
> http://www.spinics.net/lists/arm-kernel/msg390069.html
>
> - so from the progress we can see that we already finished
> most of the items, and _OSI we got a plan to fix it, RFC
> patch is on the way.
>
>
> This patch set was tested on FVP by Fuwei, and booted ok as expected.
> (No functional change since last version)

For the entire series:

Tested-by: Jon Masters <j...@redhat.com>

[Mark Brown]

On Thu, Jan 15, 2015 at 06:23:47PM +0000, Catalin Marinas wrote:
> On Thu, Jan 15, 2015 at 04:26:20PM +0000, Grant Likely wrote:

> > I'll get right to the point: Can we please have this series queued up
> > for v3.20?

> Before you even ask for this, please look at the patches and realise
> that there is a complete lack of Reviewed-by tags on the code (well,
> apart from trivial Kconfig changes). In addition, the series touches on
> other subsystems like clocksource, irqchip, acpi and I don't see any
> acks from the corresponding maintainers. So even if I wanted to merge
> the series, there is no way it can be done without additional
> reviews/acks. On the document (last patch), I'd like to see a statement

There's probably a bit of a process problem here - these patches are all
being posted as part of big and apparently controversial threads with
subject lines in the form "ARM / ACPI:" so people could be forgiven for
just not even reading the e-mails enough to notice changes to their
subsystems. Is it worth posting those patches separately more directly
to the relevant maintainers?

[Jason Cooper]

I think it's beneficial to post the entire series as one thread, but to
change the subject line of each patch to adequately reflect the affected
subsystem.

thx,

Jason.

[Mark Brown]

On Thu, Jan 15, 2015 at 03:04:37PM -0500, Jason Cooper wrote:
> On Thu, Jan 15, 2015 at 07:02:20PM +0000, Mark Brown wrote:

> > There's probably a bit of a process problem here - these patches are all
> > being posted as part of big and apparently controversial threads with
> > subject lines in the form "ARM / ACPI:" so people could be forgiven for
> > just not even reading the e-mails enough to notice changes to their
> > subsystems. Is it worth posting those patches separately more directly
> > to the relevant maintainers?

> I think it's beneficial to post the entire series as one thread, but to
> change the subject line of each patch to adequately reflect the affected
> subsystem.

Just changing the subject lines to be more suitable would help, but
given the painful thread it's probably worth going the extra step if
the lack of these reviews is a causing problems - I know that even with
a suitable subject line if I'm busy then I'm fairly likely to zone out
something in the middle a big series that doesn't seem to be going
anywhere.

[Jason Cooper]

True, I was merely expressing a preference. A lot of series containing
irqchip changes tend to have build dependencies outside of
drivers/irqchip. So I like to see the whole picture to decide how best
to handle the patches.

I suppose the ideal solution would be to have a "mute sub-thread" option
in the MUA. But that doesn't help us today. :)

Whichever way they do it is fine by me.

[Al Stone]

On 01/15/2015 11:23 AM, Catalin Marinas wrote:
> On Thu, Jan 15, 2015 at 04:26:20PM +0000, Grant Likely wrote:
>> On Wed, Jan 14, 2015 at 3:04 PM, Hanjun Guo <hanju...@linaro.org> wrote:
>>> This is the v7 of ACPI core patches for ARM64 based on ACPI 5.1
>>
>> I'll get right to the point: Can we please have this series queued up
>> for v3.20?

> [snip ... ]

>> 5. Platform support patches need verification and review
>> * ACPI core works on at least the Foundation model, Juno, APM
>> Mustang, and AMD Seattle
>> * There still are driver patches being discussed. See Al's summary
>> for details
>> * As I argued above, the state of driver patches isn't going to be
>
> We are still lacking here. To quote Al, "First version for AMD Seattle
> has been posted to the public linaro-acpi mailing list for initial
> review". Sorry but I don't follow linaro-acpi list. I don't know what's
> in those patches and I can't tell which subsystems they touch, whether
> maintainers agree with them. So in conclusion, I'm not confident the
> arm64 hardware ACPI story looks that great yet.
>

This is solely my fault -- too much time on processes, email, and
documentation, not enough time on the Seattle patches. And not
enough Seattles to go around for someone else to pick up the slack.

I am aware not everyone is subscribed to linaro-acpi; we use that
for internal review before posting more broadly, which is the only
reason I sent them there.

I'm in the middle of updating them as I have time, based on really
good feedback from Arnd; few of them are terribly new (the very first
posting was [0]) -- it's mostly a matter of rebasing, integrating
updates from AMD and others, and reacting to the comments. One can
also see what these patches will probably look like via one of the
Fedora kernel trees [1].


[0] https://lkml.org/lkml/2014/9/15/1308
[1] https://git.fedorahosted.org/git/kernel-arm64 -- this is
what I run on an AMD Seattle daily driver, btw, and is used
in Fedora 21 as well.

--
ciao,
al
-----------------------------------
Al Stone
Software Engineer
Red Hat, Inc.
ah...@redhat.com
-----------------------------------

[Suravee Suthikulanit]

On 1/14/2015 9:04 AM, Hanjun Guo wrote:
> Hi,
>

> This is the v7 of ACPI core patches for ARM64 based on ACPI 5.1
>

> Thanks
> Hanjun
>

The V7 patch series has also been re-tested on AMD Seattle server
platform along with the "Introduce ACPI support for ahci_platform
driver" patch series here (https://lkml.org/lkml/2015/1/5/662).

Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>

Thanks,

Suravee

[Jon Masters]

On 01/15/2015 04:31 PM, Al Stone wrote:
> On 01/15/2015 11:23 AM, Catalin Marinas wrote:
>> On Thu, Jan 15, 2015 at 04:26:20PM +0000, Grant Likely wrote:
>>> On Wed, Jan 14, 2015 at 3:04 PM, Hanjun Guo <hanju...@linaro.org> wrote:
>>>> This is the v7 of ACPI core patches for ARM64 based on ACPI 5.1
>>>
>>> I'll get right to the point: Can we please have this series queued up
>>> for v3.20?
>> [snip ... ]
>
>>> 5. Platform support patches need verification and review
>>> * ACPI core works on at least the Foundation model, Juno, APM
>>> Mustang, and AMD Seattle
>>> * There still are driver patches being discussed. See Al's summary
>>> for details
>>> * As I argued above, the state of driver patches isn't going to be
>>
>> We are still lacking here. To quote Al, "First version for AMD Seattle
>> has been posted to the public linaro-acpi mailing list for initial
>> review". Sorry but I don't follow linaro-acpi list. I don't know what's
>> in those patches and I can't tell which subsystems they touch, whether
>> maintainers agree with them. So in conclusion, I'm not confident the
>> arm64 hardware ACPI story looks that great yet.
>>
>
> This is solely my fault -- too much time on processes, email, and
> documentation, not enough time on the Seattle patches. And not
> enough Seattles to go around for someone else to pick up the slack.

As an aside: a few of us have discretely assisted in ensuring that the
right folks have access to hardware platforms over the past few months.
If one of the upstream maintainers does not have v8 hardware and doing
so will unblock progress please get in touch off list.

Jon.

[Hanjun Guo]

On 2015年01月16日 02:23, Catalin Marinas wrote:
> Hi Grant,

>
> On Thu, Jan 15, 2015 at 04:26:20PM +0000, Grant Likely wrote:
>> On Wed, Jan 14, 2015 at 3:04 PM, Hanjun Guo <hanju...@linaro.org> wrote:
>>> This is the v7 of ACPI core patches for ARM64 based on ACPI 5.1
>>
>> I'll get right to the point: Can we please have this series queued up
>> for v3.20?
>

> Before you even ask for this, please look at the patches and realise
> that there is a complete lack of Reviewed-by tags on the code (well,
> apart from trivial Kconfig changes). In addition, the series touches on
> other subsystems like clocksource, irqchip, acpi and I don't see any
> acks from the corresponding maintainers. So even if I wanted to merge

For the ACPI part, Rafael already said that "Having looked at the
patches recently, I don't see any major problems in them from the ACPI
core perspective, so to me they are good to go." [1]
Is that kind of ack for this ?

Thanks
Hanjun

[1]:
http://lkml.iu.edu/hypermail/linux/kernel/1409.1/03363.html

[Hanjun Guo]

On 2015年01月16日 04:31, Mark Brown wrote:
> On Thu, Jan 15, 2015 at 03:04:37PM -0500, Jason Cooper wrote:
>> On Thu, Jan 15, 2015 at 07:02:20PM +0000, Mark Brown wrote:
>
>>> There's probably a bit of a process problem here - these patches are all
>>> being posted as part of big and apparently controversial threads with
>>> subject lines in the form "ARM / ACPI:" so people could be forgiven for
>>> just not even reading the e-mails enough to notice changes to their
>>> subsystems. Is it worth posting those patches separately more directly
>>> to the relevant maintainers?
>
>> I think it's beneficial to post the entire series as one thread, but to
>> change the subject line of each patch to adequately reflect the affected
>> subsystem.
>
> Just changing the subject lines to be more suitable would help, but

OK, I will repost this patch set as you and Jason suggested soon.

Thanks
Hanjun

[Catalin Marinas]

On Wed, Jan 14, 2015 at 03:04:54PM +0000, Hanjun Guo wrote:
> Since PCI is not required in ACPI spec and ARM can run without
> it, introduce some stub functions to make PCI optional for ACPI,
> and make ACPI core run without CONFIG_PCI on ARM64.
>
> When PCI is enabled on ARM64, ACPI core will need some PCI functions
> to make it functional, so introduce some empty functions here and
> implement it later.
>
> Since ACPI on X86 and IA64 depends on PCI and this patch only makes
> PCI optional for ARM64, it will not break anything on X86 and IA64.
>

> Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
> Tested-by: Yijing Wang <wangy...@huawei.com>

> Signed-off-by: Hanjun Guo <hanju...@linaro.org>

Is this patch still required, now that we have PCI for arm64? I know the
ACPI spec doesn't require PCI but do we expect any arm64 servers aimed
at ACPI without PCIe?

Anyway, that's not the main point, see more below.

> diff --git a/arch/arm64/include/asm/pci.h b/arch/arm64/include/asm/pci.h
> index 872ba93..fded096 100644
> --- a/arch/arm64/include/asm/pci.h
> +++ b/arch/arm64/include/asm/pci.h
> @@ -24,6 +24,12 @@
> */
> #define PCI_DMA_BUS_IS_PHYS (0)
>
> +static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
> +{
> + /* no legacy IRQ on arm64 */
> + return -ENODEV;
> +}
> +
> extern int isa_dma_bridge_buggy;
>
> #ifdef CONFIG_PCI
> diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c
> index ce5836c..42fb195 100644
> --- a/arch/arm64/kernel/pci.c
> +++ b/arch/arm64/kernel/pci.c
> @@ -10,6 +10,7 @@
> *
> */
>
> +#include <linux/acpi.h>
> #include <linux/init.h>
> #include <linux/io.h>
> #include <linux/kernel.h>
> @@ -68,3 +69,30 @@ void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent)
> bus->domain_nr = domain;
> }
> #endif
> +
> +/*
> + * raw_pci_read/write - Platform-specific PCI config space access.
> + *
> + * Default empty implementation. Replace with an architecture-specific setup
> + * routine, if necessary.
> + */
> +int raw_pci_read(unsigned int domain, unsigned int bus,
> + unsigned int devfn, int reg, int len, u32 *val)
> +{
> + return -EINVAL;
> +}
> +
> +int raw_pci_write(unsigned int domain, unsigned int bus,
> + unsigned int devfn, int reg, int len, u32 val)
> +{
> + return -EINVAL;
> +}
> +
> +#ifdef CONFIG_ACPI
> +/* Root bridge scanning */
> +struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
> +{
> + /* TODO: Should be revisited when implementing PCI on ACPI */
> + return NULL;
> +}
> +#endif

Do these functions have anything to do with the subject? You add them in
arch/arm64/kernel/pci.c which is compiled only when CONFIG_PCI while the
commit log implies that you add them to allow CONFIG_PCI to be off.

When PCI is enabled and the above functions are compiled in, do they
need to return any useful data or just -EINVAL. Are they ever called?

> diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
> index 39f3ec1..c346011 100644
> --- a/drivers/acpi/Makefile
> +++ b/drivers/acpi/Makefile
> @@ -43,7 +43,7 @@ acpi-y += processor_core.o
> acpi-$(CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC) += processor_pdc.o
> acpi-y += ec.o
> acpi-$(CONFIG_ACPI_DOCK) += dock.o
> -acpi-y += pci_root.o pci_link.o pci_irq.o
> +acpi-$(CONFIG_PCI) += pci_root.o pci_link.o pci_irq.o
> acpi-y += acpi_lpss.o
> acpi-y += acpi_platform.o
> acpi-y += acpi_pnp.o
> diff --git a/drivers/acpi/internal.h b/drivers/acpi/internal.h
> index 163e82f..c5ff8ba 100644
> --- a/drivers/acpi/internal.h
> +++ b/drivers/acpi/internal.h
> @@ -26,8 +26,13 @@
> acpi_status acpi_os_initialize1(void);
> int init_acpi_device_notify(void);
> int acpi_scan_init(void);
> +#ifdef CONFIG_PCI
> void acpi_pci_root_init(void);
> void acpi_pci_link_init(void);
> +#else
> +static inline void acpi_pci_root_init(void) {}
> +static inline void acpi_pci_link_init(void) {}
> +#endif
> void acpi_processor_init(void);
> void acpi_platform_init(void);
> void acpi_pnp_init(void);

That's a good clean-up.

> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 360a966..1476a66 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -564,15 +564,6 @@ struct pci_ops {
> int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
> };
>
> -/*
> - * ACPI needs to be able to access PCI config space before we've done a
> - * PCI bus scan and created pci_bus structures.
> - */
> -int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
> - int reg, int len, u32 *val);
> -int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
> - int reg, int len, u32 val);
> -
> struct pci_bus_region {
> dma_addr_t start;
> dma_addr_t end;
> @@ -1329,6 +1320,16 @@ typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
> unsigned int command_bits, u32 flags);
> void pci_register_set_vga_state(arch_set_vga_state_t func);
>
> +/*
> + * ACPI needs to be able to access PCI config space before we've done a
> + * PCI bus scan and created pci_bus structures.
> + */
> +int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
> + int reg, int len, u32 *val);
> +int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
> + int reg, int len, u32 val);
> +void pcibios_penalize_isa_irq(int irq, int active);
> +
> #else /* CONFIG_PCI is not enabled */
>
> /*
> @@ -1430,6 +1431,23 @@ static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
> unsigned int devfn)
> { return NULL; }
>
> +static inline struct pci_bus *pci_find_bus(int domain, int busnr)
> +{ return NULL; }
> +
> +static inline int pci_bus_write_config_byte(struct pci_bus *bus,
> + unsigned int devfn, int where, u8 val)
> +{ return -ENOSYS; }
> +
> +static inline int raw_pci_read(unsigned int domain, unsigned int bus,
> + unsigned int devfn, int reg, int len, u32 *val)
> +{ return -ENOSYS; }
> +
> +static inline int raw_pci_write(unsigned int domain, unsigned int bus,
> + unsigned int devfn, int reg, int len, u32 val)
> +{ return -ENOSYS; }

So you implement the !CONFIG_PCI functions here to return -ENOSYS while
the arm64 CONFIG_PCI ones would return -EINVAL. I'm confused.

--
Catalin

[Catalin Marinas]

On Fri, Jan 16, 2015 at 07:17:56AM +0000, Hanjun Guo wrote:
> On 2015年01月16日 02:23, Catalin Marinas wrote:
> > On Thu, Jan 15, 2015 at 04:26:20PM +0000, Grant Likely wrote:
> >> On Wed, Jan 14, 2015 at 3:04 PM, Hanjun Guo <hanju...@linaro.org> wrote:
> >>> This is the v7 of ACPI core patches for ARM64 based on ACPI 5.1
> >>
> >> I'll get right to the point: Can we please have this series queued up
> >> for v3.20?
> >
> > Before you even ask for this, please look at the patches and realise
> > that there is a complete lack of Reviewed-by tags on the code (well,
> > apart from trivial Kconfig changes). In addition, the series touches on
> > other subsystems like clocksource, irqchip, acpi and I don't see any
> > acks from the corresponding maintainers. So even if I wanted to merge
>
> For the ACPI part, Rafael already said that "Having looked at the
> patches recently, I don't see any major problems in them from the ACPI
> core perspective, so to me they are good to go." [1]
> Is that kind of ack for this ?

I guess we can call this an "ack" from the ACPI core perspective. But
it's not just ACPI core that this series touches. You should probably
get a renewed ack for the latest series as the message you quoted is 4
months old.

A question that Rafael asked was how you plan to get these merged. You
(or Grant) chose the arm64 maintainers and that's fine by me but it
doesn't mean you don't need acks/reviews for the patches in this series.

--
Catalin

[Catalin Marinas]

On Thu, Jan 15, 2015 at 08:04:37PM +0000, Jason Cooper wrote:
> On Thu, Jan 15, 2015 at 07:02:20PM +0000, Mark Brown wrote:
> > On Thu, Jan 15, 2015 at 06:23:47PM +0000, Catalin Marinas wrote:
> > > On Thu, Jan 15, 2015 at 04:26:20PM +0000, Grant Likely wrote:
> >
> > > > I'll get right to the point: Can we please have this series queued up
> > > > for v3.20?
> >
> > > Before you even ask for this, please look at the patches and realise
> > > that there is a complete lack of Reviewed-by tags on the code (well,
> > > apart from trivial Kconfig changes). In addition, the series touches on
> > > other subsystems like clocksource, irqchip, acpi and I don't see any
> > > acks from the corresponding maintainers. So even if I wanted to merge
> > > the series, there is no way it can be done without additional
> > > reviews/acks. On the document (last patch), I'd like to see a statement
> >
> > There's probably a bit of a process problem here - these patches are all
> > being posted as part of big and apparently controversial threads with
> > subject lines in the form "ARM / ACPI:" so people could be forgiven for
> > just not even reading the e-mails enough to notice changes to their
> > subsystems. Is it worth posting those patches separately more directly
> > to the relevant maintainers?
>
> I think it's beneficial to post the entire series as one thread, but to
> change the subject line of each patch to adequately reflect the affected
> subsystem.

Indeed, keeping the series as one thread is better. Apart from a
slightly less misleading subject, I suggest Hanjun that he passes each
patch via get_maintainer.pl and adds the corresponding Cc: lines to the
commit log. I think that's a clearer way keep track of who needs to
ack/review the patches.

--
Catalin

[Catalin Marinas]

Do you have some simple branch against mainline with just the ACPI core
patches and what's required for AMD Seattle? I have no plans to dig
through the Fedora kernels.

--
Catalin

[Marc Zyngier]

On 14/01/15 15:05, Hanjun Guo wrote:
> Introduce ACPI_IRQ_MODEL_GIC which is needed for ARM64 as GIC is
> used, and then register device's gsi with the core IRQ subsystem.
>
> acpi_register_gsi() is similar to DT based irq_of_parse_and_map(),
> since gsi is unique in the system, so use hwirq number directly
> for the mapping.
>
> Originally-by: Amit Daniel Kachhap <amit....@samsung.com>

> Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
> Tested-by: Yijing Wang <wangy...@huawei.com>
> Signed-off-by: Hanjun Guo <hanju...@linaro.org>

> ---
> arch/arm64/kernel/acpi.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++
> drivers/acpi/bus.c | 3 ++
> include/linux/acpi.h | 1 +
> 3 files changed, 77 insertions(+)
>
> diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
> index 0b7c3a6..c3e24c4 100644
> --- a/arch/arm64/kernel/acpi.c
> +++ b/arch/arm64/kernel/acpi.c
> @@ -37,6 +37,12 @@ EXPORT_SYMBOL(acpi_pci_disabled);
> static int enabled_cpus; /* Processors (GICC) with enabled flag in MADT */
>
> /*
> + * Since we're on ARM, the default interrupt routing model
> + * clearly has to be GIC.
> + */
> +enum acpi_irq_model_id acpi_irq_model = ACPI_IRQ_MODEL_GIC;
> +
> +/*
> * __acpi_map_table() will be called before page_init(), so early_ioremap()
> * or early_memremap() should be called here to for ACPI table mapping.
> */
> @@ -184,6 +190,73 @@ void __init acpi_smp_init_cpus(void)
> pr_info("%d CPUs enabled, %d CPUs total\n", enabled_cpus, total_cpus);
> }
>
> +int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
> +{
> + *irq = irq_find_mapping(NULL, gsi);

Is the ACPI implementation really expecting to only deal with a single
domain for interrupts?

This is likely to lead to a number of issues as we're now implementing
stacked domains (GICv2m, GICv3 ITS are already using that model, and
"wire-to MSI translators" will certainly do the same).

This means that, despite having a single GIC described in ACPI, you may
end-up with multiple domains. I expect you'll be safe with MSI (assuming
you never describe them in ACPI), but any form of wire-to-MSI
translation won't work at all.

Thanks,

M.
--
Jazz is not dead. It just smells funny...

[Marc Zyngier]

On 14/01/15 15:05, Hanjun Guo wrote:

> From: Tomasz Nowicki <tomasz....@linaro.org>
>
> ACPI kernel uses MADT table for proper GIC initialization. It needs to
> parse GIC related subtables, collect CPU interface and distributor
> addresses and call driver initialization function (which is hardware
> abstraction agnostic). In a similar way, FDT initialize GICv1/2.
>
> NOTE: This commit allow to initialize GICv1/2 basic functionality.
> GICv2 vitalization extension, GICv3/4 and ITS are considered as next
> steps.

And so is GICv2m, apparently (see below).

>
> Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
> Tested-by: Yijing Wang <wangy...@huawei.com>

> Signed-off-by: Tomasz Nowicki <tomasz....@linaro.org>

> Signed-off-by: Hanjun Guo <hanju...@linaro.org>
> ---

> arch/arm64/kernel/acpi.c | 26 +++++++++
> drivers/irqchip/irq-gic.c | 108 +++++++++++++++++++++++++++++++++++
> drivers/irqchip/irqchip.c | 3 +
> include/linux/irqchip/arm-gic-acpi.h | 31 ++++++++++
> 4 files changed, 168 insertions(+)
> create mode 100644 include/linux/irqchip/arm-gic-acpi.h
>
> diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
> index c3e24c4..ea3c9fc 100644
> --- a/arch/arm64/kernel/acpi.c
> +++ b/arch/arm64/kernel/acpi.c
> @@ -23,6 +23,7 @@
> #include <linux/irqdomain.h>
> #include <linux/bootmem.h>
> #include <linux/smp.h>
> +#include <linux/irqchip/arm-gic-acpi.h>
>
> #include <asm/cputype.h>
> #include <asm/cpu_ops.h>
> @@ -315,6 +316,31 @@ void __init acpi_boot_table_init(void)
> pr_err("Can't find FADT or error happened during parsing FADT\n");
> }
>
> +void __init acpi_gic_init(void)
> +{
> + struct acpi_table_header *table;
> + acpi_status status;
> + acpi_size tbl_size;
> + int err;
> +
> + if (acpi_disabled)
> + return;
> +
> + status = acpi_get_table_with_size(ACPI_SIG_MADT, 0, &table, &tbl_size);
> + if (ACPI_FAILURE(status)) {
> + const char *msg = acpi_format_exception(status);
> +
> + pr_err("Failed to get MADT table, %s\n", msg);
> + return;
> + }
> +
> + err = gic_v2_acpi_init(table);
> + if (err)
> + pr_err("Failed to initialize GIC IRQ controller");
> +
> + early_acpi_os_unmap_memory((char *)table, tbl_size);
> +}
> +
> static int __init parse_acpi(char *arg)
> {
> if (!arg)
> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> index d617ee5..89a8120 100644
> --- a/drivers/irqchip/irq-gic.c
> +++ b/drivers/irqchip/irq-gic.c
> @@ -33,12 +33,14 @@
> #include <linux/of.h>
> #include <linux/of_address.h>
> #include <linux/of_irq.h>
> +#include <linux/acpi.h>
> #include <linux/irqdomain.h>
> #include <linux/interrupt.h>
> #include <linux/percpu.h>
> #include <linux/slab.h>
> #include <linux/irqchip/chained_irq.h>
> #include <linux/irqchip/arm-gic.h>
> +#include <linux/irqchip/arm-gic-acpi.h>
>
> #include <asm/cputype.h>
> #include <asm/irq.h>
> @@ -1083,3 +1085,109 @@ IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
>
> #endif
> +
> +#ifdef CONFIG_ACPI
> +static phys_addr_t dist_phy_base, cpu_phy_base;
> +static int cpu_base_assigned;
> +
> +static int __init
> +gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header,
> + const unsigned long end)
> +{
> + struct acpi_madt_generic_interrupt *processor;
> + phys_addr_t gic_cpu_base;
> +
> + processor = (struct acpi_madt_generic_interrupt *)header;
> +
> + if (BAD_MADT_ENTRY(processor, end))
> + return -EINVAL;
> +
> + /*
> + * There is no support for non-banked GICv1/2 register in ACPI spec.
> + * All CPU interface addresses have to be the same.
> + */
> + gic_cpu_base = processor->base_address;
> + if (cpu_base_assigned && gic_cpu_base != cpu_phy_base)
> + return -EFAULT;

EFAULT? That feels weird. This error code should be returned if an
access would generate (or has actually generated) a fault, but this is
not the case here. Same for the other cases below.

> +
> + cpu_phy_base = gic_cpu_base;
> + cpu_base_assigned = 1;
> + return 0;
> +}
> +
> +static int __init
> +gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header,
> + const unsigned long end)
> +{
> + struct acpi_madt_generic_distributor *dist;
> +
> + dist = (struct acpi_madt_generic_distributor *)header;
> +
> + if (BAD_MADT_ENTRY(dist, end))
> + return -EINVAL;
> +
> + dist_phy_base = dist->base_address;
> + return 0;
> +}
> +
> +int __init
> +gic_v2_acpi_init(struct acpi_table_header *table)
> +{
> + void __iomem *cpu_base, *dist_base;
> + int count;
> +
> + /* Collect CPU base addresses */
> + count = acpi_parse_entries(ACPI_SIG_MADT,
> + sizeof(struct acpi_table_madt),
> + gic_acpi_parse_madt_cpu, table,
> + ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0);
> + if (count < 0) {
> + pr_err("Error during GICC entries parsing\n");
> + return -EFAULT;
> + } else if (!count) {
> + pr_err("No valid GICC entries exist\n");

> + return -EINVAL;
> + }
> +

> + /*
> + * Find distributor base address. We expect one distributor entry since
> + * ACPI 5.1 spec neither support multi-GIC instances nor GIC cascade.
> + */
> + count = acpi_parse_entries(ACPI_SIG_MADT,
> + sizeof(struct acpi_table_madt),
> + gic_acpi_parse_madt_distributor, table,
> + ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0);
> + if (count <= 0) {
> + pr_err("Error during GICD entries parsing\n");
> + return -EFAULT;
> + } else if (!count) {
> + pr_err("No valid GICD entries exist\n");
> + return -EINVAL;
> + } else if (count > 1) {
> + pr_err("More than one GICD entry detected\n");

> + return -EINVAL;
> + }
> +

> + cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE);
> + if (!cpu_base) {
> + pr_err("Unable to map GICC registers\n");
> + return -ENOMEM;
> + }
> +
> + dist_base = ioremap(dist_phy_base, ACPI_GICV2_DIST_MEM_SIZE);
> + if (!dist_base) {
> + pr_err("Unable to map GICD registers\n");
> + iounmap(cpu_base);
> + return -ENOMEM;
> + }
> +
> + /*
> + * Initialize zero GIC instance (no multi-GIC support). Also, set GIC
> + * as default IRQ domain to allow for GSI registration and GSI to IRQ
> + * number translation (see acpi_register_gsi() and acpi_gsi_to_irq()).
> + */
> + gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL);

I assume you never tried to port the GICv2m driver to ACPI, right?
Because the above code actively prevents the GIC domain to be defined as
a stacked domain, making it impossible for the v2m widget to be
implemented on top of GIC. But maybe legacy interrupts are enough?

> + irq_set_default_host(gic_data[0].domain);
> + return 0;
> +}
> +#endif
> diff --git a/drivers/irqchip/irqchip.c b/drivers/irqchip/irqchip.c
> index 0fe2f71..9106c6d 100644
> --- a/drivers/irqchip/irqchip.c
> +++ b/drivers/irqchip/irqchip.c
> @@ -11,6 +11,7 @@
> #include <linux/init.h>
> #include <linux/of_irq.h>
> #include <linux/irqchip.h>
> +#include <linux/irqchip/arm-gic-acpi.h>
>
> /*
> * This special of_device_id is the sentinel at the end of the
> @@ -26,4 +27,6 @@ extern struct of_device_id __irqchip_of_table[];
> void __init irqchip_init(void)
> {
> of_irq_init(__irqchip_of_table);
> +
> + acpi_gic_init();

Have you realised that this file is probably compiled on multiple
architecture, none of which particularly cares about ACPI or the GIC?
This is (still) very ugly.

I still think this should be implemented properly, following the path
shown by the line just above. Even if we only have two interrupt
controllers until the end of times (which moderately likely unlikely to
be true). But I'm tired of sounding like a stuck record, so I'll STFU.

Thanks,

M.

> }
> diff --git a/include/linux/irqchip/arm-gic-acpi.h b/include/linux/irqchip/arm-gic-acpi.h
> new file mode 100644
> index 0000000..ad5b577
> --- /dev/null
> +++ b/include/linux/irqchip/arm-gic-acpi.h
> @@ -0,0 +1,31 @@
> +/*
> + * Copyright (C) 2014, Linaro Ltd.
> + * Author: Tomasz Nowicki <tomasz....@linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef ARM_GIC_ACPI_H_
> +#define ARM_GIC_ACPI_H_
> +
> +#ifdef CONFIG_ACPI
> +
> +/*
> + * Hard code here, we can not get memory size from MADT (but FDT does),
> + * Actually no need to do that, because this size can be inferred
> + * from GIC spec.
> + */
> +#define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K)
> +#define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
> +
> +struct acpi_table_header;
> +
> +void acpi_gic_init(void);
> +int gic_v2_acpi_init(struct acpi_table_header *table);
> +#else
> +static inline void acpi_gic_init(void) { }
> +#endif
> +
> +#endif /* ARM_GIC_ACPI_H_ */

[Mark Brown]

On Thu, Jan 15, 2015 at 03:51:39PM -0500, Jason Cooper wrote:
> On Thu, Jan 15, 2015 at 08:31:59PM +0000, Mark Brown wrote:

> > Just changing the subject lines to be more suitable would help, but
> > given the painful thread it's probably worth going the extra step if
> > the lack of these reviews is a causing problems - I know that even with
> > a suitable subject line if I'm busy then I'm fairly likely to zone out
> > something in the middle a big series that doesn't seem to be going
> > anywhere.

> True, I was merely expressing a preference. A lot of series containing
> irqchip changes tend to have build dependencies outside of
> drivers/irqchip. So I like to see the whole picture to decide how best
> to handle the patches.

Right, I didn't mean stop sending things as part of this series but
rather send them separately as well.

[Mark Brown]

On Fri, Jan 16, 2015 at 10:10:34AM +0000, Catalin Marinas wrote:

> Indeed, keeping the series as one thread is better. Apart from a
> slightly less misleading subject, I suggest Hanjun that he passes each
> patch via get_maintainer.pl and adds the corresponding Cc: lines to the
> commit log. I think that's a clearer way keep track of who needs to
> ack/review the patches.

I'm not saying stop sending them as part of this series, I'm saying it
might help to get people to look at them if they were also sent
disassociated from it - in the situations where I end up ignoring things
that look controversial but unexciting for my bit of it I know I won't
even bother opening the e-mails since I know it's just going to get
resent anyway quite often with revisions from whatever makes the rest of
the series controversial, I expect others will do the same.

Actually, another thing that might help would be if you and/or Will were
to prod the relevant people for review, letting them know that the
controversy isn't likely to affect their bits.

[Will Deacon]

Hmm, we *could*, but having maintainers go round poking other people to
review patches feels like the wrong way round to me. The authors should
be taking ownership of this series and that's half of the problem we
had in previous versions.

It needs to be clear that Hanjun/Al/Graeme are the ones running the show,
not just now, but (even more importantly) when people start building on
top of the base support. If Catalin and I have to go around asking for
review, it sets us off on the wrong foot imo.

Will

[Grant Likely]

On Fri, Jan 16, 2015 at 11:15 AM, Marc Zyngier <marc.z...@arm.com> wrote:
> On 14/01/15 15:05, Hanjun Guo wrote:
>> From: Tomasz Nowicki <tomasz....@linaro.org>
>>
>> ACPI kernel uses MADT table for proper GIC initialization. It needs to
>> parse GIC related subtables, collect CPU interface and distributor
>> addresses and call driver initialization function (which is hardware
>> abstraction agnostic). In a similar way, FDT initialize GICv1/2.
>>
>> NOTE: This commit allow to initialize GICv1/2 basic functionality.
>> GICv2 vitalization extension, GICv3/4 and ITS are considered as next
>> steps.
>
> And so is GICv2m, apparently (see below).
>
>>
>> Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
>> Tested-by: Yijing Wang <wangy...@huawei.com>
>> Signed-off-by: Tomasz Nowicki <tomasz....@linaro.org>
>> Signed-off-by: Hanjun Guo <hanju...@linaro.org>
>> ---

>> + /*
>> + * Initialize zero GIC instance (no multi-GIC support). Also, set GIC
>> + * as default IRQ domain to allow for GSI registration and GSI to IRQ
>> + * number translation (see acpi_register_gsi() and acpi_gsi_to_irq()).
>> + */
>> + gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL);
>
> I assume you never tried to port the GICv2m driver to ACPI, right?
> Because the above code actively prevents the GIC domain to be defined as
> a stacked domain, making it impossible for the v2m widget to be
> implemented on top of GIC. But maybe legacy interrupts are enough?

It's sufficient for what is supported right now, and easily changed in
a patch series to add GICv2m support. This shouldn't be a blocking
issue as it isn't actively dangerous. It is merely limited, and that
is okay.

>> @@ -26,4 +27,6 @@ extern struct of_device_id __irqchip_of_table[];
>> void __init irqchip_init(void)
>> {
>> of_irq_init(__irqchip_of_table);
>> +
>> + acpi_gic_init();
>
> Have you realised that this file is probably compiled on multiple
> architecture, none of which particularly cares about ACPI or the GIC?
> This is (still) very ugly.

"very ugly?" That's overstating things a bit. We may quibble about the
name, but we're just talking about a setup hook function that may or
may not be implemented. How about we put acpi_irq_init() here and make
it an inline macro that directly calls acpi_gic_init() when ACPI is
enabled on AARCH64? Then the function can be extended by architectures
as needed, and default to an empty inline otherwise. When (if) we have
more than one hook that needs to be called from it, then we can
refactor it to be more like of_irq_init().

As for other architectures calling this function, but not caring about
ACPI, I believe it was your suggestion to put it here! :-)

On Mon, 01 Sep 2014 18:35:18 +0100^M, Marc Zyngier <marc.z...@arm.com> wrote:
> On 01/09/14 15:57, Hanjun Guo wrote:
> > @@ -78,6 +79,10 @@ void __init set_handle_irq(void (*handle_irq)(struct pt_regs *))
> > void __init init_IRQ(void)
> > {
> > irqchip_init();
> > +
> > + if (!handle_arch_irq)
> > + acpi_gic_init();
> > +
>
> Why isn't this called from irqchip_init? It would seem like the logical
> spot to probe an interrupt controller.

What has been done here isn't an unusual choice. We've got stuff all
over the kernel that may or may not be implemented depending on what
the architecture supports. If the function call is renamed to
acpi_init_irq(), are you content?

g.

[Lorenzo Pieralisi]

On Wed, Jan 14, 2015 at 03:04:55PM +0000, Hanjun Guo wrote:
> FADT Major.Minor version was introduced in ACPI 5.1, it is the same
> as ACPI version.
>
> In ACPI 5.1, some major gaps are fixed for ARM, such as updates in
> MADT table for GIC and SMP init, without those updates, we can not
> get the MPIDR for SMP init, and GICv2/3 related init information, so
> we can't boot arm64 ACPI properly with table versions predating 5.1.
>
> If firmware provides ACPI tables with ACPI version less than 5.1,
> OS will be messed up with those information and have no way to init

Nit: "that information"

or

"...OS has no way to retrieve the configuration data that is necessary
to init SMP boot protocol and the GIC properly, so.."

> smp and GIC, so disable ACPI if we get an FADT table with version
> less that 5.1.
>

Patch should be reordered in the series and must be sequenced before
patch 5 for bisectability (that patch implements DT unflattening if ACPI
is disabled), or squashed with previous patches.

Lorenzo

> Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
> Tested-by: Yijing Wang <wangy...@huawei.com>

> Signed-off-by: Hanjun Guo <hanju...@linaro.org>
> ---

> arch/arm64/kernel/acpi.c | 31 ++++++++++++++++++++++++++++++-
> 1 file changed, 30 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
> index 39a1655..4177758 100644
> --- a/arch/arm64/kernel/acpi.c
> +++ b/arch/arm64/kernel/acpi.c
> @@ -13,6 +13,8 @@

> * published by the Free Software Foundation.

> */
>
> +#define pr_fmt(fmt) "ACPI: " fmt
> +
> #include <linux/init.h>
> #include <linux/acpi.h>
> #include <linux/cpumask.h>
> @@ -49,10 +51,32 @@ void __init __acpi_unmap_table(char *map, unsigned long size)
> early_memunmap(map, size);
> }
>
> +static int __init acpi_parse_fadt(struct acpi_table_header *table)
> +{
> + struct acpi_table_fadt *fadt = (struct acpi_table_fadt *)table;
> +
> + /*
> + * Revision in table header is the FADT Major revision,
> + * and there is a minor revision of FADT which was introduced
> + * by ACPI 5.1, we only deal with ACPI 5.1 or newer revision
> + * to get arm boot flags, or we will disable ACPI.
> + */
> + if (table->revision > 5 ||
> + (table->revision == 5 && fadt->minor_revision >= 1))
> + return 0;
> +
> + pr_warn("Unsupported FADT revision %d.%d, should be 5.1+, will disable ACPI\n",
> + table->revision, fadt->minor_revision);
> + disable_acpi();
> +

> + return -EINVAL;
> +}
> +
> /*

> * acpi_boot_table_init() called from setup_arch(), always.
> * 1. find RSDP and get its address, and then find XSDT
> * 2. extract all tables and checksums them all
> + * 3. check ACPI FADT revision
> *
> * We can parse ACPI boot-time tables such as MADT after
> * this function is called.
> @@ -64,8 +88,13 @@ void __init acpi_boot_table_init(void)
> return;
>
> /* Initialize the ACPI boot-time table parser. */
> - if (acpi_table_init())
> + if (acpi_table_init()) {
> disable_acpi();
> + return;
> + }
> +
> + if (acpi_table_parse(ACPI_SIG_FADT, acpi_parse_fadt))
> + pr_err("Can't find FADT or error happened during parsing FADT\n");

> }
>
> static int __init parse_acpi(char *arg)

> --
> 1.9.1

[Marc Zyngier]

My (full) suggestion was to do it like we've done it for DT, and I don't
think I varied much from this point of view. Yes, calling it
acpi_irq_init() would be a good start, and having the ACPI-compatible
irqchips to be self-probable even better.

<lack-of-sleep-rant>

Hell, if nobody beats me to it, maybe I'll just write that code, with
proper entry points in the various GIC drivers. Yes, this is
infrastructure. Maybe it is grossly overdesigned. But I really spend too
much time dealing with the crap that people are happy to pile on top of
the GIC code to be madly enthusiastic about the general "good enough"
attitude.

</lack-of-sleep-rant>

Or to put it in a slightly more diplomatic way: If ACPI is to be our
future, can we please make the future look a bit better?

Thanks,

M.

--
Jazz is not dead. It just smells funny...

[Tom Lendacky]

On 01/16/2015 01:17 AM, Hanjun Guo wrote:
> On 2015年01月16日 02:23, Catalin Marinas wrote:
>> Hi Grant,
>>
>> On Thu, Jan 15, 2015 at 04:26:20PM +0000, Grant Likely wrote:
>>> On Wed, Jan 14, 2015 at 3:04 PM, Hanjun Guo <hanju...@linaro.org>
>>> wrote:
>>>> This is the v7 of ACPI core patches for ARM64 based on ACPI 5.1
>>>
>>> I'll get right to the point: Can we please have this series queued up
>>> for v3.20?
>>
>> Before you even ask for this, please look at the patches and realise
>> that there is a complete lack of Reviewed-by tags on the code (well,
>> apart from trivial Kconfig changes). In addition, the series touches on
>> other subsystems like clocksource, irqchip, acpi and I don't see any
>> acks from the corresponding maintainers. So even if I wanted to merge
>
> For the ACPI part, Rafael already said that "Having looked at the
> patches recently, I don't see any major problems in them from the ACPI
> core perspective, so to me they are good to go." [1]
> Is that kind of ack for this ?
>
> Thanks
> Hanjun
>
> [1]:
> http://lkml.iu.edu/hypermail/linux/kernel/1409.1/03363.html
>

I have tested ACPI-enablement patches for the amd-xgbe/amd-xgbe-phy
drivers that I'm about to submit upstream with the V7 patch series
on the AMD Seattle server platform. There does not appear to be support
for the _CCA attribute in this patch series. The amd-xgbe driver will
setup the device domain and cache attributes based on the presence of
this attribute, but it requires the arch support to assign the proper
DMA operations in order for it to all work correctly.

Overriding the _CCA attribute in the driver, I was able to successfully
test the driver and this patch series.

Thanks,
Tom


> _______________________________________________
> linux-arm-kernel mailing list
> linux-ar...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[Will Deacon]

Hi Tom,

On Fri, Jan 16, 2015 at 02:45:30PM +0000, Tom Lendacky wrote:
> I have tested ACPI-enablement patches for the amd-xgbe/amd-xgbe-phy
> drivers that I'm about to submit upstream with the V7 patch series
> on the AMD Seattle server platform. There does not appear to be support
> for the _CCA attribute in this patch series. The amd-xgbe driver will
> setup the device domain and cache attributes based on the presence of
> this attribute, but it requires the arch support to assign the proper
> DMA operations in order for it to all work correctly.
>
> Overriding the _CCA attribute in the driver, I was able to successfully
> test the driver and this patch series.

Hopefully this will all be addressed when the IORT parts of ACPI have
settled down (the current proposal allows for these attributes to be
described as well as their interaction with things like IOMMUs).

In the meantime, are you falling back to non-coherent DMA? If so, what
attributes have you settled on? We need to be really careful not to
corrupt data during cache invalidatation when mapping a non-coherent
buffer for the CPU.

Will

[Arnd Bergmann]

On Friday 16 January 2015 14:55:45 Will Deacon wrote:
> Hi Tom,
>
> On Fri, Jan 16, 2015 at 02:45:30PM +0000, Tom Lendacky wrote:
> > I have tested ACPI-enablement patches for the amd-xgbe/amd-xgbe-phy
> > drivers that I'm about to submit upstream with the V7 patch series
> > on the AMD Seattle server platform. There does not appear to be support
> > for the _CCA attribute in this patch series. The amd-xgbe driver will
> > setup the device domain and cache attributes based on the presence of
> > this attribute, but it requires the arch support to assign the proper
> > DMA operations in order for it to all work correctly.
> >
> > Overriding the _CCA attribute in the driver, I was able to successfully
> > test the driver and this patch series.
>
> Hopefully this will all be addressed when the IORT parts of ACPI have
> settled down (the current proposal allows for these attributes to be
> described as well as their interaction with things like IOMMUs).
>
> In the meantime, are you falling back to non-coherent DMA? If so, what
> attributes have you settled on? We need to be really careful not to
> corrupt data during cache invalidatation when mapping a non-coherent
> buffer for the CPU.

I think in case of ACPI we should use cache-coherent as the default,
as this is what all servers will use for DMA masters.

Arnd

[Al Stone]

Nor was I expecting you to; I only added it as additional reference
material, should one be interested.

The version of patches sent to the linaro-acpi list are from the Linaro
acpi.git tree, and are precisely what you describe; those are the ones
being updated.

--
ciao,
al
-----------------------------------
Al Stone
Software Engineer

Linaro Enterprise Group
al.s...@linaro.org
-----------------------------------

[Al Stone]

My bad, not enough coffee yet. The Linaro acpi.git tree is at:

https://git.linaro.org/leg/acpi/acpi.git

--
ciao,
al
-----------------------------------
Al Stone
Software Engineer

Red Hat, Inc.
ah...@redhat.com

[Catalin Marinas]

On Fri, Jan 16, 2015 at 03:14:13PM +0000, Arnd Bergmann wrote:
> On Friday 16 January 2015 14:55:45 Will Deacon wrote:
> > On Fri, Jan 16, 2015 at 02:45:30PM +0000, Tom Lendacky wrote:
> > > I have tested ACPI-enablement patches for the amd-xgbe/amd-xgbe-phy
> > > drivers that I'm about to submit upstream with the V7 patch series
> > > on the AMD Seattle server platform. There does not appear to be support
> > > for the _CCA attribute in this patch series. The amd-xgbe driver will
> > > setup the device domain and cache attributes based on the presence of
> > > this attribute, but it requires the arch support to assign the proper
> > > DMA operations in order for it to all work correctly.
> > >
> > > Overriding the _CCA attribute in the driver, I was able to successfully
> > > test the driver and this patch series.
> >
> > Hopefully this will all be addressed when the IORT parts of ACPI have
> > settled down (the current proposal allows for these attributes to be
> > described as well as their interaction with things like IOMMUs).
> >
> > In the meantime, are you falling back to non-coherent DMA? If so, what
> > attributes have you settled on? We need to be really careful not to
> > corrupt data during cache invalidatation when mapping a non-coherent
> > buffer for the CPU.
>
> I think in case of ACPI we should use cache-coherent as the default,
> as this is what all servers will use for DMA masters.

Last time I heard in some call, it was agreed that _CCA properties
should always be present and Linux should not make any assumption (there
is no safe assumption here). While better options may appear in ACPI,
_CCA is what we currently have.

--
Catalin

[Tom Lendacky]

Hi Will,

On 01/16/2015 08:55 AM, Will Deacon wrote:
> Hi Tom,
>
> On Fri, Jan 16, 2015 at 02:45:30PM +0000, Tom Lendacky wrote:
>> I have tested ACPI-enablement patches for the amd-xgbe/amd-xgbe-phy
>> drivers that I'm about to submit upstream with the V7 patch series
>> on the AMD Seattle server platform. There does not appear to be support
>> for the _CCA attribute in this patch series. The amd-xgbe driver will
>> setup the device domain and cache attributes based on the presence of
>> this attribute, but it requires the arch support to assign the proper
>> DMA operations in order for it to all work correctly.
>>
>> Overriding the _CCA attribute in the driver, I was able to successfully
>> test the driver and this patch series.
>
> Hopefully this will all be addressed when the IORT parts of ACPI have
> settled down (the current proposal allows for these attributes to be
> described as well as their interaction with things like IOMMUs).
>
> In the meantime, are you falling back to non-coherent DMA? If so, what
> attributes have you settled on? We need to be really careful not to
> corrupt data during cache invalidatation when mapping a non-coherent
> buffer for the CPU.
>

The override I used in the driver was to set the device to use AxDOMAIN
of 3 and AxCACHE of 0 so that the caches are not accessed.

Tom

[Will Deacon]

On Fri, Jan 16, 2015 at 03:14:13PM +0000, Arnd Bergmann wrote:

> On Friday 16 January 2015 14:55:45 Will Deacon wrote:
> > On Fri, Jan 16, 2015 at 02:45:30PM +0000, Tom Lendacky wrote:
> > > I have tested ACPI-enablement patches for the amd-xgbe/amd-xgbe-phy
> > > drivers that I'm about to submit upstream with the V7 patch series
> > > on the AMD Seattle server platform. There does not appear to be support
> > > for the _CCA attribute in this patch series. The amd-xgbe driver will
> > > setup the device domain and cache attributes based on the presence of
> > > this attribute, but it requires the arch support to assign the proper
> > > DMA operations in order for it to all work correctly.
> > >
> > > Overriding the _CCA attribute in the driver, I was able to successfully
> > > test the driver and this patch series.
> >
> > Hopefully this will all be addressed when the IORT parts of ACPI have
> > settled down (the current proposal allows for these attributes to be
> > described as well as their interaction with things like IOMMUs).
> >
> > In the meantime, are you falling back to non-coherent DMA? If so, what
> > attributes have you settled on? We need to be really careful not to
> > corrupt data during cache invalidatation when mapping a non-coherent
> > buffer for the CPU.
>
> I think in case of ACPI we should use cache-coherent as the default,
> as this is what all servers will use for DMA masters.

I don't agree. The dma-coherent we have for device-tree isn't nearly
expressive enough for the kind of things we want to describe and there's
no reason to make the same mistake in ACPI, especially as it *is* being
addressed by IORT. If we run with _CCA, then we're going to be stuck
supporting something that isn't fit for purpose and which will likely be
abused to describe both fixed features of the system and software
configuration preferences. It also opens up a can of worms if we have to
support a mixture of _CCA and IORT in the future.

Or are you suggesting that we ignore _CCA and just assume cache-coherency?
In that case, how do we support systems that aren't cache coherent, where
not being cache coherent includes devices that require either device or
IOMMU configuration to enable cacheable transactions?

Will

[Will Deacon]

On Fri, Jan 16, 2015 at 03:40:28PM +0000, Arnd Bergmann wrote:

> I was thinking we'd ignore _CCA because as you say a simple on/off flag
> would not be enough to describe what we have to do for noncoherent
> devices. I can't think of any reason why a server hardware would include
> noncoherent devices, so if they are configurable they should be configured
> into coherent mode by the firmware.

The on-board ethernet on Seattle requires the driver to program its AXI
attributes, so configuring it to be a coherent master actually means
"program the same cacheable AXI settings as you have on the CPU". That
sounds like Linux should be doing it to me, but even if the firmware takes
a guess at "normal cacheable WBRWA", it's not clear to me whether that
register persists across things like adapter reset.

Tom?

There's also the situation where the firmware hasn't initialised the
register and Linux realises this during probe. What should it do then?

[Arnd Bergmann]

I was thinking we'd ignore _CCA because as you say a simple on/off flag
would not be enough to describe what we have to do for noncoherent
devices. I can't think of any reason why a server hardware would include
noncoherent devices, so if they are configurable they should be configured
into coherent mode by the firmware.

Arnd

[Arnd Bergmann]

To clarify: I don't think we should just ignore _CCA in Linux, but instead
see if it lists the device as coherent and warn loudly if it's configured
as noncoherent, then set the dma-mask pointer to NULL to prevent DMA from
being started on it.

[Suravee Suthikulpanit]

Catalin,

For Seattle, you could use the https://git.linaro.org/leg/acpi/acpi.git
acpi-5.1-v7, and it would also need the AHCI ACPI patch here
(https://lkml.org/lkml/2015/1/5/662).

Thanks,
Suravee

[Arnd Bergmann]

On Friday 16 January 2015 15:49:13 Will Deacon wrote:
>
> The on-board ethernet on Seattle requires the driver to program its AXI
> attributes, so configuring it to be a coherent master actually means
> "program the same cacheable AXI settings as you have on the CPU". That
> sounds like Linux should be doing it to me, but even if the firmware takes
> a guess at "normal cacheable WBRWA", it's not clear to me whether that
> register persists across things like adapter reset.
>
> Tom?
>
> There's also the situation where the firmware hasn't initialised the
> register and Linux realises this during probe. What should it do then?

In case of a 10gbit ethernet adapter, there really should be no question
regarding whether to set it coherent or not. Can't Linux just always
set this AXI attribute in the driver?

Arnd

[Grant Likely]

On Thu, 15 Jan 2015 18:23:47 +0000
, Catalin Marinas <catalin...@arm.com>
wrote:
> Hi Grant,

>
> On Thu, Jan 15, 2015 at 04:26:20PM +0000, Grant Likely wrote:
> > On Wed, Jan 14, 2015 at 3:04 PM, Hanjun Guo <hanju...@linaro.org> wrote:
> > > This is the v7 of ACPI core patches for ARM64 based on ACPI 5.1
> >
> > I'll get right to the point: Can we please have this series queued up
> > for v3.20?
>

> Before you even ask for this, please look at the patches and realise
> that there is a complete lack of Reviewed-by tags on the code (well,
> apart from trivial Kconfig changes). In addition, the series touches on
> other subsystems like clocksource, irqchip, acpi and I don't see any
> acks from the corresponding maintainers. So even if I wanted to merge

> the series, there is no way it can be done without additional
> reviews/acks. On the document (last patch), I'd like to see a statement

> from HP as they've been vocal in private but no public endorsement of
> this doc.

I have to ask. We've got no idea what you are thinking in terms of merge
timeline. The ToDo list is part of the question, certainly, but if I
have to ask flat-out to get some progress, then I will. Up to this
point, the primary objections have been coming from you and other ARM
maintainers, not the ACPI maintainer, and not other subsystem
maintainers, so of course I'm going to address my arguments to you and
Will.


> I also have trouble seeing the full picture. Is there a git repository
> somewhere with this series and any additional patches required for a
> real hardware platform?

I believe Al has sent you a git URL by now.

>
> > I really think we've hit the point where it is more valuable to merge
> > it (or at least prepare to merge it) rather than keeping it out of
> > mainline.
>
> That's pretty subjective.

You and I are both maintainers; an awful lot of our job is subjective
opinion on whether something is ready or not! That's why I said "I
really think" rather than "We have". :-)

The rest of my email is laying out my argument for why I think it is
time to start queuing these patches up.

> > Continuing to keep the patches out I think is having the opposite
> > effect from what is desired. Catalin, you've told me a few times that
> > saying "no" is the only leverage you have to keeping crap drivers out
> > of the kernel until things mature, and by extension influence how
> > firmware gets implemented. However, as far as drivers are concerned,
> > there is nothing stopping maintainers from picking up ACPI drivers for
> > ARM hardware regardless of whether or not the core ARM code is merged.
> > If a driver depends on CONFIG_ACPI, and if the code seems to look
> > good, there is nothing preventing it from being merged. There are
> > already ARM related ACPI patches going into mainline.
> >
> > For example: https://lkml.org/lkml/2014/12/25/120
>
> I wasn't really referring to simple driver changes like the above but to
> whole subsystems like clocks done in ACPI. My point was that before we
> enable arm64 ACPI, we need to have some clear guidelines to firmware and
> hardware vendors, otherwise if we don't know how to do it properly, we
> shouldn't even bother (or we may end up re-creating the DT support in
> ACPI; I'm not convinced that's sorted yet).

Whole subsystem changes aren't the big risk. Saying yes to this series
does not commit us to also picking up badly formed ACPI infrastructure.
Changes to subsystems get a lot more scrutiny than drivers do.

As for clocks, pinctrl, and regulators, the answer has been simple and
clear for a long time. No. We won't do anything automatic with any of
those in mainline until there is an ACPI specification that addresses
them. Until that time they are out-of-spec and won't be supported.

Also, my point still stands. Subsystem changes do not hinge on whether
or not arch/arm64 has ACPI support. Changes have been merged to add ACPI
support to platform_bus, i2c and spi subsystems well over a year ago.

> > Instead, keeping these patches out means that hardware is getting
> > developed and tested against Fedora, early access RHEL and Linaro
> > kernels. It means that we're abdicating on any influence mainline has
> > over how those platforms are developed. The longer these patches stay
> > out of mainline, the greater the potential for delta between what is
> > in the vendor kernels and what we accept into mainline.
>
> I'm not buying this argument. Putting pressure on maintainers to merge
> something because Fedora or some other distro has merged them is not the
> right approach. If such Linux vendors ignore arguments on the list just
> for the sake of providing ACPI support, there is a high chance that they
> will accept non-standard code any other time when the kernel community
> disagrees.

It's not like I'm arguing for stuff that isn't ready to be merged. Even
back last October there was broad agreement from all of us (Will, Olof,
Marc Z. Mark R., myself) that these patches are correct and that the
remaining objections are related to larger questions of ecosystem. My
argument is that for all the outstanding issues, we've either got a
solution, or a process for working it out with hardware vendors. Keeping
things out of mainline now I think has hit the point of actively hurting
development. We're still having to dicker about with the core patches
that aren't supposed to be contentious anymore, and we're making the
hardware vendors work out of tree unnecessarily.

> Just to be clear, I don't block the ACPI patches for fun, reading these
> long threads is not fun anymore. I don't have any religious arguments
> against ACPI, longer term I see it as a first class citizen alongside
> DT, but I want to make sure we do it properly and have a clear vision on
> how we support it in the future. You can call this "delayed
> gratification" if you want.
>
> And it's not about code going into arch/arm64 and not even small driver
> changes to enable ACPI but the longer term plans on how we reduce
> (rather than eliminate) future kernel quirks because we didn't first get
> to an agreement on how kernel and firmware interact. Things are getting
> better and Al's to-do list is a good benchmark (more comments below).
>
> (I have my concerns with DT as well but the requirement of compatibility
> between older/newer kernels/firmware is not as strict)
>
> > Finally, keeping them out has the practical effect of causing extra
> > work to continually rebase them, while potentially running into new
> > conflicts and bugs, for little if any real benefit. Whereas getting
> > them into linux-next starts giving us some feedback on conflicts with
> > other things that are being queued up for mainline. Not to mention
> > reviewer fatigue having to go over the same set of patches again and
> > again.
>
> 17 patches is really not too hard and it looks like the number is slowly
> decreasing as they are picked by the corresponding maintainers.
>
> > Right now we're at -rc4. We'll be at -rc5 this weekend, and quite
> > possibly have a new merge window right at the start of Connect.
> > Queuing these patches up now isn't even a 100% commitment for you to
> > ask Linus to pull them. We can have further discussions at Connect. If
> > you're still not satisfied then drop them out again for another cycle.
> > However, if they aren't queued up now, then we're looking at mid-June
> > before they show up in a mainline kernel release.
>
> See the beginning of the email about the prerequisites for queuing
> something up into linux-next.
>
> > As promised earlier, I said that I'd go through the todo list items.
> > Here they are with discussion:
> > 1. Define how Aarch64 OS identifies itself to firmware
> > - We've pretty much settled on dropping the _OSI interface entirely,
> > which is trivial to do. All of the current platforms can adapt to
> > this. There are still some discussions around _OSC, but given that
> > this is the first release there isn't anything for the platform to
> > differentiate on regarding features. This isn't going to affect
> > current platforms, but rather will be important with the release of
> > the next version of the ACPI spec. It shouldn't affect our ability to
> > merge core support
>
> I'm fine with this.
>
> > 2. Linux must choose DT booting by default when offered both ACPI and
> > * Status: DONE, but being revisited for possible algorithmic change
>
> OK.
>
> > 3. Linux UEFI/ACPI testing tools must be made available
> > * Done. We're implementing more tests of course, but that is expected.
>
> OK.
>
> > 4. Set clear expectations for those providing ACPI for use with Linux
> > * We have a document that covers what we know so far, and will
> > continue to expand it. Also talking with the SBBR folks to move
> > relevant requirements into the SBBR doc.
>
> Moving bits of it into SBBR is a good long term plan but it should not
> prevent the merging. However, I'd like to see more vendors ok'ing the
> kernel document.

>
> > 5. Platform support patches need verification and review
> > * ACPI core works on at least the Foundation model, Juno, APM
> > Mustang, and AMD Seattle
> > * There still are driver patches being discussed. See Al's summary
> > for details
> > * As I argued above, the state of driver patches isn't going to be
>
> We are still lacking here. To quote Al, "First version for AMD Seattle
> has been posted to the public linaro-acpi mailing list for initial
> review". Sorry but I don't follow linaro-acpi list. I don't know what's
> in those patches and I can't tell which subsystems they touch, whether
> maintainers agree with them. So in conclusion, I'm not confident the
> arm64 hardware ACPI story looks that great yet.
>

> As for Juno and foundation models, I don't consider them server
> platforms.
>
> > 6. How does the kernel handle_DSD usage?
> > While important, these issues are separate from whether or not to
> > merge the core aarch64 code. This work was defined and driven by Intel
> > for their embedded platforms, and it is already in mainline. Keeping
> > aarch64 support out isn't going to prevent drivers using it from being
> > merged. I don't think this should be a reason for blocking this
> > series.
>
> Intel folk is coming from the other direction, relatively standard
> hardware getting slightly more non-standard and they need a few bits
> added in _DSD. On ARM, we have completely non-standard hardware with DT
> used to describe complex topology (clocks, pin controls, voltage
> regulators etc.) with a high risk that vendors see _DSD as a work around
> standardising hardware or doing it properly in ACPI (whatever that
> means, AML?).

Doing it properly in ACPI merely means giving the drivers the data
and/or methods that it needs. The ACPI spec does define some methods to
be used by OSPM, but everything else is completely arbitrary, and always
has been.

The *only* thing that _DSD does new is to define a specific format for
adding key-value properties to an ACPI object that follow the rules of
properties. Apple Mac hardware has done exactly the same thing for
years, except it stuffed that stuff into the _DSM method.

So, _DSD is no less "doing it property in ACPI" than AML methods would
be. In either case it is the responsibility of the driver to know what
extra properties/methods might be attached to the device, and to know
what to do with those properties/methods. The core OS doesn't care, and
won't touch them.

*so what* if vendor toss odd data into a _DSD property. It still won't
wire up to the automatic clock/pinctrl/voltage infrastructure that we
use for DT because none of those things will be there. It won't make a
non-standard ARM machine suddenly behave.

However, what we do have is a rule that bindings must be documented,
whether they be DT or ACPI. So, regardless of what vendors try to shove
into ACPI, the rule is that driver support shouldn't be merged without
documented bindings (either in the kernel tree, or UEFI forum's repo),
and that gives us some leverage.

What we can also do is create a least-effort path for driver authors.
There are helper functions for parsing _DSD that are easier than doing
something custom. It is less effort to use existing DT bindings with the
device properties API than to try and have a separate set of ACPI
bindings.

But, still, I strongly contend that this is a sideshow when looking at
the core ARM patches. _DSD code is happening right now, with or without
aarch64.

> > 7. Why is ACPI required?
> > I hope I've addressed this[1], but discussion continues.
> >
> > [1] http://www.spinics.net/lists/arm-kernel/msg389955.html
>
> That's great. I see this as a good reference for the future.
>
> To complete the picture, we probably need a "Why *not* ACPI on ARM" blog
> as well explaining when ACPI is *not* suitable (e.g. no SBSA
> compliance). The arm-acpi.txt covers the ACPI requirements from the
> kernel perspective and, by contrast, DT would be better suited for
> certain platforms. The way you present it is that ACPI solves lots of
> problems that DT doesn't but not necessarily where the ACPI limitations
> are (vs DT).

I thought I was pretty clear in that document that ACPI is only
preferred for the general purpose ecosystem (OS vendor and HW vendor are
separate companies, and selected by the end user). Everywhere else the
preference is DT. However, I can write more on this topic and make it
clear that I'm talking about SBSA hardware. It will probably take me a
week or so to get that written. Certainly before we're in Hong Kong for
Connect.

g.

[Mark Brown]

On Fri, Jan 16, 2015 at 12:29:22PM +0000, Will Deacon wrote:
> On Fri, Jan 16, 2015 at 12:05:18PM +0000, Mark Brown wrote:

> > Actually, another thing that might help would be if you and/or Will were
> > to prod the relevant people for review, letting them know that the
> > controversy isn't likely to affect their bits.

> Hmm, we *could*, but having maintainers go round poking other people to
> review patches feels like the wrong way round to me. The authors should
> be taking ownership of this series and that's half of the problem we
> had in previous versions.

> It needs to be clear that Hanjun/Al/Graeme are the ones running the show,
> not just now, but (even more importantly) when people start building on
> top of the base support. If Catalin and I have to go around asking for
> review, it sets us off on the wrong foot imo.

That's true in general but equally right now it's also fairly clear that
this isn't going anywhere immediately (and one might assume potentially
may end up needing substantial rework) for arm64 related reasons which
creates a bit of stop energy that's more easily unblocked by the arm64
maintainers than others. From that point of view I guess just giving
the ACPI folks something to point at to indicate that the remaining
issues on the architecture side aren't likely to affect the relevant
code would probably help also.

[Tom Lendacky]

The registers that contain the AxDOMAIN and AxCACHE settings do not
persist across an adapter reset.

Tom

[Arnd Bergmann]

On Friday 16 January 2015 16:29:44 Grant Likely wrote:
> > > Instead, keeping these patches out means that hardware is getting
> > > developed and tested against Fedora, early access RHEL and Linaro
> > > kernels. It means that we're abdicating on any influence mainline has
> > > over how those platforms are developed. The longer these patches stay
> > > out of mainline, the greater the potential for delta between what is
> > > in the vendor kernels and what we accept into mainline.
> >
> > I'm not buying this argument. Putting pressure on maintainers to merge
> > something because Fedora or some other distro has merged them is not the
> > right approach. If such Linux vendors ignore arguments on the list just
> > for the sake of providing ACPI support, there is a high chance that they
> > will accept non-standard code any other time when the kernel community
> > disagrees.

Actually there is strong precedence for merging things because distros
felt it was necessary. That's how we ended up with drivers/staging
in the first place.

It's not the nicest way to merge stuff, but it's something we cannot
ignore. Unfortunately it seems we already have the nonstandard code,
as Fedora includes the APM Mustang support that in previous reviews
we have concluded would not be suitable for upstream because it (in
particular the PCI support) is too far from SBSA.

> > > 4. Set clear expectations for those providing ACPI for use with Linux
> > > * We have a document that covers what we know so far, and will
> > > continue to expand it. Also talking with the SBBR folks to move
> > > relevant requirements into the SBBR doc.
> >
> > Moving bits of it into SBBR is a good long term plan but it should not
> > prevent the merging. However, I'd like to see more vendors ok'ing the
> > kernel document.

Agreed.

> > > 5. Platform support patches need verification and review
> > > * ACPI core works on at least the Foundation model, Juno, APM
> > > Mustang, and AMD Seattle
> > > * There still are driver patches being discussed. See Al's summary
> > > for details
> > > * As I argued above, the state of driver patches isn't going to be
> >
> > We are still lacking here. To quote Al, "First version for AMD Seattle
> > has been posted to the public linaro-acpi mailing list for initial
> > review". Sorry but I don't follow linaro-acpi list. I don't know what's
> > in those patches and I can't tell which subsystems they touch, whether
> > maintainers agree with them. So in conclusion, I'm not confident the
> > arm64 hardware ACPI story looks that great yet.
> >
> > As for Juno and foundation models, I don't consider them server
> > platforms.

I did a large part of the review. I raised some important concerns about
the Seattle port, and addressing those will result in incompatible
changes, but I did not see any show-stoppers there.

To summarize, the main concerns were:

- AMD specific bindings for generic devices (ARM pl061, pl022, ...)
- network driver using _DSD with a binding that is incompatible with
the existing DT binding. I believe this one was getting addressed,
but I have not seen an update.

What about PRP0001? Do we recommend against using it or should we try
to get everyone to use it for devices that already have a DT binding?

One result of the Seattle review was a patch to use class codes for
standard devices like AHCI. This is great and I think it's being merged
now, but we still have to figure out how to do this for standard
licensed IP blocks that don't already have a PCI class code, and whose
responsibility it should be to define a binding for such devices.

> > > 7. Why is ACPI required?
> > > I hope I've addressed this[1], but discussion continues.
> > >
> > > [1] http://www.spinics.net/lists/arm-kernel/msg389955.html
> >
> > That's great. I see this as a good reference for the future.
> >
> > To complete the picture, we probably need a "Why *not* ACPI on ARM" blog
> > as well explaining when ACPI is *not* suitable (e.g. no SBSA
> > compliance). The arm-acpi.txt covers the ACPI requirements from the
> > kernel perspective and, by contrast, DT would be better suited for
> > certain platforms. The way you present it is that ACPI solves lots of
> > problems that DT doesn't but not necessarily where the ACPI limitations
> > are (vs DT).
>
> I thought I was pretty clear in that document that ACPI is only
> preferred for the general purpose ecosystem (OS vendor and HW vendor are
> separate companies, and selected by the end user). Everywhere else the
> preference is DT. However, I can write more on this topic and make it
> clear that I'm talking about SBSA hardware. It will probably take me a
> week or so to get that written. Certainly before we're in Hong Kong for
> Connect.

I think it would be helpful for the purpose of merging the patches if
that statement can be stronger and say that DT is required for devices
other than SBSA hardware, rather than recommended. We can always relax
the rule later if there is a good reason, but it's hard to make it
stricter after the fact.

Arnd

[Lorenzo Pieralisi]

Hi Hanjun,

On Wed, Jan 14, 2015 at 03:04:58PM +0000, Hanjun Guo wrote:

[...]

> diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h
> index 780f82c..bf22650 100644
> --- a/arch/arm64/include/asm/smp.h
> +++ b/arch/arm64/include/asm/smp.h
> @@ -39,9 +39,10 @@ extern void show_ipi_list(struct seq_file *p, int prec);
> extern void handle_IPI(int ipinr, struct pt_regs *regs);
>
> /*
> - * Setup the set of possible CPUs (via set_cpu_possible)
> + * Discover the set of possible CPUs and determine their
> + * SMP operations.
> */
> -extern void smp_init_cpus(void);
> +extern void of_smp_init_cpus(void);
>
> /*
> * Provide a function to raise an IPI cross call on CPUs in callmap.
> diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
> index 4177758..55d99d9 100644
> --- a/arch/arm64/kernel/acpi.c
> +++ b/arch/arm64/kernel/acpi.c
> @@ -24,6 +24,10 @@
> #include <linux/bootmem.h>
> #include <linux/smp.h>
>
> +#include <asm/smp_plat.h>
> +#include <asm/cputype.h>
> +#include <asm/cpu_ops.h>

Alphabetical order please.

> +
> int acpi_noirq; /* skip ACPI IRQ initialization */
> int acpi_disabled;
> EXPORT_SYMBOL(acpi_disabled);
> @@ -31,6 +35,8 @@ EXPORT_SYMBOL(acpi_disabled);
> int acpi_pci_disabled; /* skip ACPI PCI scan and IRQ initialization */
> EXPORT_SYMBOL(acpi_pci_disabled);
>
> +static int enabled_cpus; /* Processors (GICC) with enabled flag in MADT */

Needed for hotplug ? Remember that each patch must be self-contained.

This patch is clearly not, if I did not know you need to carry this
stuff over after boot for physical cpu hotplugging it would be hard to
understand most of this code.

Think about that for anyone looking at your commit-log as a stand alone
entity in the kernel history.

> +

> /*
> * __acpi_map_table() will be called before page_init(), so early_ioremap()
> * or early_memremap() should be called here to for ACPI table mapping.

> @@ -51,6 +57,134 @@ void __init __acpi_unmap_table(char *map, unsigned long size)
> early_memunmap(map, size);
> }
>
> +/**
> + * acpi_map_gic_cpu_interface - generates a logical cpu number
> + * and map to MPIDR represented by GICC structure
> + * @mpidr: CPU's hardware id to register, MPIDR represented in MADT
> + * @enabled: this cpu is enabled or not
> + *
> + * Returns the logical cpu number which maps to MPIDR
> + */
> +static int acpi_map_gic_cpu_interface(u64 mpidr, u8 enabled)

It would be __init, except that you might need it after boot for
hotplug, correct ?

> +{
> + int cpu;
> +
> + if (mpidr == INVALID_HWID) {
> + pr_info("Skip MADT cpu entry with invalid MPIDR\n");

> + return -EINVAL;
> + }
> +

> + total_cpus++;
> + if (!enabled)
> + return -EINVAL;
> +
> + if (enabled_cpus >= NR_CPUS) {
> + pr_warn("NR_CPUS limit of %d reached, Processor %d/0x%llx ignored.\n",
> + NR_CPUS, total_cpus, mpidr);

> + return -EINVAL;
> + }
> +

> + /* No need to check duplicate MPIDRs for the first CPU */
> + if (enabled_cpus) {
> + /*
> + * Duplicate MPIDRs are a recipe for disaster. Scan
> + * all initialized entries and check for
> + * duplicates. If any is found just ignore the CPU.
> + */
> + for_each_possible_cpu(cpu) {
> + if (cpu_logical_map(cpu) == mpidr) {
> + pr_err("Firmware bug, duplicate CPU MPIDR: 0x%llx in MADT\n",
> + mpidr);

> + return -EINVAL;
> + }
> + }

> +
> + /* allocate a logical cpu id for the new comer */
> + cpu = cpumask_next_zero(-1, cpu_possible_mask);
> + } else {
> + /*
> + * First GICC entry must be BSP as ACPI spec said
> + * in section 5.2.12.15
> + */
> + if (cpu_logical_map(0) != mpidr) {
> + pr_err("First GICC entry with MPIDR 0x%llx is not BSP\n",
> + mpidr);

> + return -EINVAL;
> + }
> +

> + /*
> + * boot_cpu_init() already hold bit 0 in cpu_present_mask

You mean cpu_possible_mask ? That's what you allocate from above.

> + * for BSP, no need to allocate again.
> + */
> + cpu = 0;
> + }
> +
> + /* CPU 0 was already initialized */
> + if (cpu) {
> + cpu_ops[cpu] = cpu_get_ops(acpi_psci_present() ? "psci" : NULL);
> + if (!cpu_ops[cpu])
> + return -EINVAL;
> +
> + if (cpu_ops[cpu]->cpu_init(NULL, cpu))
> + return -EOPNOTSUPP;
> +
> + /* map the logical cpu id to cpu MPIDR */
> + cpu_logical_map(cpu) = mpidr;
> +
> + set_cpu_possible(cpu, true);
> + } else {
> + /* get cpu0's ops, no need to return if ops is null */
> + cpu_ops[0] = cpu_get_ops(acpi_psci_present() ? "psci" : NULL);
> + }

I do not see much point in calling cpu_get_ops with NULL, and adding
the check in it to return NULL when the parameter is NULL.

What would you expect from cpu_get_ops when called with NULL other than
a NULL pointer ?

You could move:

cpu_ops[cpu] = cpu_get_ops(acpi_psci_present() ? "psci" : NULL);

out of the if and remove the else, do not know if it makes code clearer,
shorter for certain.

> +
> + enabled_cpus++;
> + return cpu;

> +}
> +
> +static int __init

> +acpi_parse_gic_cpu_interface(struct acpi_subtable_header *header,

> + const unsigned long end)
> +{
> + struct acpi_madt_generic_interrupt *processor;
> +

> + processor = (struct acpi_madt_generic_interrupt *)header;
> +
> + if (BAD_MADT_ENTRY(processor, end))

> + return -EINVAL;
> +
> + acpi_table_print_madt_entry(header);
> +
> + acpi_map_gic_cpu_interface(processor->arm_mpidr & MPIDR_HWID_BITMASK,
> + processor->flags & ACPI_MADT_ENABLED);
> +

> + return 0;
> +}
> +

> +/* Parse GIC cpu interface entries in MADT for SMP init */
> +void __init acpi_smp_init_cpus(void)
> +{
> + int count;
> +
> + /*
> + * do a partial walk of MADT to determine how many CPUs
> + * we have including disabled CPUs, and get information
> + * we need for SMP init
> + */
> + count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
> + acpi_parse_gic_cpu_interface, 0);
> +
> + if (!count) {
> + pr_err("No GIC CPU interface entries present\n");
> + return;
> + } else if (count < 0) {
> + pr_err("Error parsing GIC CPU interface entry\n");
> + return;
> + }
> +
> + /* Make boot-up look pretty */
> + pr_info("%d CPUs enabled, %d CPUs total\n", enabled_cpus, total_cpus);
> +}
> +

> static int __init acpi_parse_fadt(struct acpi_table_header *table)

> {

> struct acpi_table_fadt *fadt = (struct acpi_table_fadt *)table;

> @@ -62,8 +196,20 @@ static int __init acpi_parse_fadt(struct acpi_table_header *table)

> * to get arm boot flags, or we will disable ACPI.

> */
> if (table->revision > 5 ||
> - (table->revision == 5 && fadt->minor_revision >= 1))
> - return 0;

> + (table->revision == 5 && fadt->minor_revision >= 1)) {

> + /*
> + * ACPI 5.1 only has two explicit methods to boot up SMP,
> + * PSCI and Parking protocol, but the Parking protocol is
> + * only specified for ARMv7 now, so make PSCI as the only
> + * way for the SMP boot protocol before some updates for
> + * the ACPI spec or the Parking protocol spec.
> + */
> + if (acpi_psci_present())
> + return 0;
> +
> + pr_warn("No PSCI support, will not bring up secondary CPUs\n");
> + return -EOPNOTSUPP;

> + }
>
> pr_warn("Unsupported FADT revision %d.%d, should be 5.1+, will disable ACPI\n",

> table->revision, fadt->minor_revision);
> diff --git a/arch/arm64/kernel/cpu_ops.c b/arch/arm64/kernel/cpu_ops.c
> index cce9524..1ea7b9f 100644
> --- a/arch/arm64/kernel/cpu_ops.c
> +++ b/arch/arm64/kernel/cpu_ops.c
> @@ -27,7 +27,7 @@ extern const struct cpu_operations cpu_psci_ops;
>
> const struct cpu_operations *cpu_ops[NR_CPUS];
>
> -static const struct cpu_operations *supported_cpu_ops[] __initconst = {
> +static const struct cpu_operations *supported_cpu_ops[] = {

This __initconst removal should be explained either with code needing
it or through a comment. You can't make changes with future patches
in mind, since they may never get merged and you leave code in this
patch incomplete.

As far as I know if physical CPU hotplug can't/won't be done on ARM64 your
patch would make changes that are not needed, and miss some changes
that are (eg removing enabled_cpus or make it __initdata).

You can't write a patch with assumptions on subsequent patches.

> #ifdef CONFIG_SMP
> &smp_spin_table_ops,
> #endif
> @@ -35,10 +35,13 @@ static const struct cpu_operations *supported_cpu_ops[] __initconst = {
> NULL,
> };
>
> -static const struct cpu_operations * __init cpu_get_ops(const char *name)
> +const struct cpu_operations *cpu_get_ops(const char *name)

Ditto.

> {
> const struct cpu_operations **ops = supported_cpu_ops;
>
> + if (!name)
> + return NULL;
> +

See above.

> while (*ops) {
> if (!strcmp(name, (*ops)->name))
> return *ops;
> diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
> index ef5b1e1..54e39e3 100644
> --- a/arch/arm64/kernel/setup.c
> +++ b/arch/arm64/kernel/setup.c
> @@ -414,13 +414,16 @@ void __init setup_arch(char **cmdline_p)
> if (acpi_disabled) {
> unflatten_device_tree();
> psci_dt_init();
> + cpu_read_bootcpu_ops();
> +#ifdef CONFIG_SMP
> + of_smp_init_cpus();
> +#endif
> } else {
> psci_acpi_init();
> + acpi_smp_init_cpus();

With DT you call cpu_read_bootcpu_ops() and then of_smp_init_cpus()
with acpi you have one function that does both, it is not really
neat.

Thanks,
Lorenzo
> }
>
> - cpu_read_bootcpu_ops();
> #ifdef CONFIG_SMP
> - smp_init_cpus();
> smp_build_mpidr_hash();
> #endif
>
> diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
> index 7ae6ee0..5aaf5a4 100644
> --- a/arch/arm64/kernel/smp.c
> +++ b/arch/arm64/kernel/smp.c
> @@ -323,7 +323,7 @@ void __init smp_prepare_boot_cpu(void)
> * cpu logical map array containing MPIDR values related to logical
> * cpus. Assumes that cpu_logical_map(0) has already been initialized.
> */
> -void __init smp_init_cpus(void)
> +void __init of_smp_init_cpus(void)
> {
> struct device_node *dn = NULL;
> unsigned int i, cpu = 1;
> --
> 1.9.1

[Catalin Marinas]

On Fri, Jan 16, 2015 at 04:29:44PM +0000, Grant Likely wrote:
> On Thu, 15 Jan 2015 18:23:47 +0000, Catalin Marinas <catalin...@arm.com> wrote:
> > On Thu, Jan 15, 2015 at 04:26:20PM +0000, Grant Likely wrote:
> > > On Wed, Jan 14, 2015 at 3:04 PM, Hanjun Guo <hanju...@linaro.org> wrote:
> > > > This is the v7 of ACPI core patches for ARM64 based on ACPI 5.1
> > >
> > > I'll get right to the point: Can we please have this series queued up
> > > for v3.20?
> >
> > Before you even ask for this, please look at the patches and realise
> > that there is a complete lack of Reviewed-by tags on the code (well,
> > apart from trivial Kconfig changes). In addition, the series touches on
> > other subsystems like clocksource, irqchip, acpi and I don't see any
> > acks from the corresponding maintainers. So even if I wanted to merge
> > the series, there is no way it can be done without additional
> > reviews/acks. On the document (last patch), I'd like to see a statement
> > from HP as they've been vocal in private but no public endorsement of
> > this doc.
>
> I have to ask. We've got no idea what you are thinking in terms of merge
> timeline. The ToDo list is part of the question, certainly, but if I
> have to ask flat-out to get some progress, then I will. Up to this
> point, the primary objections have been coming from you and other ARM
> maintainers, not the ACPI maintainer, and not other subsystem
> maintainers, so of course I'm going to address my arguments to you and
> Will.

I'm not entirely sure the other maintainers looked at the patches at
all, mainly because they thought it's all too ARM specific. Pushing to
linux-next is a first step but I wouldn't do it without acks from the
corresponding maintainers.

> > > Instead, keeping these patches out means that hardware is getting
> > > developed and tested against Fedora, early access RHEL and Linaro
> > > kernels. It means that we're abdicating on any influence mainline has
> > > over how those platforms are developed. The longer these patches stay
> > > out of mainline, the greater the potential for delta between what is
> > > in the vendor kernels and what we accept into mainline.
> >
> > I'm not buying this argument. Putting pressure on maintainers to merge
> > something because Fedora or some other distro has merged them is not the
> > right approach. If such Linux vendors ignore arguments on the list just
> > for the sake of providing ACPI support, there is a high chance that they
> > will accept non-standard code any other time when the kernel community
> > disagrees.
>
> It's not like I'm arguing for stuff that isn't ready to be merged. Even
> back last October there was broad agreement from all of us (Will, Olof,
> Marc Z. Mark R., myself) that these patches are correct and that the
> remaining objections are related to larger questions of ecosystem. My
> argument is that for all the outstanding issues, we've either got a
> solution, or a process for working it out with hardware vendors. Keeping
> things out of mainline now I think has hit the point of actively hurting
> development. We're still having to dicker about with the core patches
> that aren't supposed to be contentious anymore, and we're making the
> hardware vendors work out of tree unnecessarily.

Things are getting better but if we didn't have objections starting a
year ago, I don't think as much effort would have been dedicated to
things like arm-acpi.txt, clarifying the ACPI spec around GIC support
etc. From my perspective, pushing a non-working (IOW not fully
functional) implementation in the kernel with a plan to sort things out
later doesn't really work. I wasn't fully convinced that Linaro will
dedicate the same effort once the code goes into mainline. So maybe not
the nicest approach but blocking ACPI merging is a way to see longer
term plans thought out.

Anyway, we now got to a point where the core patches are ok (-ish, there
are some comments to be addressed), we have some documents and guidance
that can evolve in time and we can show this working on real hardware
(well, not fully functional, for example you don't yet have lower CPU
power states). I'll have a look at the branch Al pointed me at (I would
have preferred linux-arm-kernel discussions rather than linaro-acpi
which I don't follow) but in the meantime I trust Arnd to have
scrutinised the Seattle patches ;).

I'll do another review of the ACPI core patches next week but with the
current comments addressed and acks from the subsystem maintainers
affected by these patches, we could try to push them to linux-next (but
no commitment for a specific kernel version). Once in -next, subsequent
fixes would have to go on top to avoid rebasing.

> > > 6. How does the kernel handle_DSD usage?
> > > While important, these issues are separate from whether or not to
> > > merge the core aarch64 code. This work was defined and driven by Intel
> > > for their embedded platforms, and it is already in mainline. Keeping
> > > aarch64 support out isn't going to prevent drivers using it from being
> > > merged. I don't think this should be a reason for blocking this
> > > series.
> >
> > Intel folk is coming from the other direction, relatively standard
> > hardware getting slightly more non-standard and they need a few bits
> > added in _DSD. On ARM, we have completely non-standard hardware with DT
> > used to describe complex topology (clocks, pin controls, voltage
> > regulators etc.) with a high risk that vendors see _DSD as a work around
> > standardising hardware or doing it properly in ACPI (whatever that
> > means, AML?).

[...]

> However, what we do have is a rule that bindings must be documented,
> whether they be DT or ACPI. So, regardless of what vendors try to shove
> into ACPI, the rule is that driver support shouldn't be merged without
> documented bindings (either in the kernel tree, or UEFI forum's repo),
> and that gives us some leverage.

The problem I have with this process is that the _DSD properties would
not be reviewed by the kernel maintainers before they are approved by
the UEFI forum. So the kernel community are just faced with a set of
patches to support approved _DSD bindings and at that point it's late to
push back, especially when such bindings were already implemented in
firmware.

I'd like to see some proper guidance for _DSD bindings rather than some
examples like "linux,trigger" currently on the UEFI website.

--
Catalin

[Rob Herring]

On Fri, Jan 16, 2015 at 9:53 AM, Arnd Bergmann <ar...@arndb.de> wrote:
> On Friday 16 January 2015 15:49:13 Will Deacon wrote:
>>
>> The on-board ethernet on Seattle requires the driver to program its AXI
>> attributes, so configuring it to be a coherent master actually means
>> "program the same cacheable AXI settings as you have on the CPU". That
>> sounds like Linux should be doing it to me, but even if the firmware takes
>> a guess at "normal cacheable WBRWA", it's not clear to me whether that
>> register persists across things like adapter reset.
>>
>> Tom?
>>
>> There's also the situation where the firmware hasn't initialised the
>> register and Linux realises this during probe. What should it do then?
>
> In case of a 10gbit ethernet adapter, there really should be no question
> regarding whether to set it coherent or not. Can't Linux just always
> set this AXI attribute in the driver?

Coherency is easy to get wrong, so the path could be broken. In fact
on highbank, it is the non-coherent path that is broken. You could
find out pretty far down the road that you need to change
configuration. But yes, I agree with your point as you pretty much
have to run coherently for decent performance on high speed
peripherals.

If we are mucking with AXI specifics in the kernel on ACPI systems,
we've already failed to abstract the platform. AXI is not even part of
the architecture.

Rob

[Hanjun Guo]

On 2015年01月16日 22:33, Lorenzo Pieralisi wrote:
> On Wed, Jan 14, 2015 at 03:04:55PM +0000, Hanjun Guo wrote:
>> FADT Major.Minor version was introduced in ACPI 5.1, it is the same
>> as ACPI version.
>>
>> In ACPI 5.1, some major gaps are fixed for ARM, such as updates in
>> MADT table for GIC and SMP init, without those updates, we can not
>> get the MPIDR for SMP init, and GICv2/3 related init information, so
>> we can't boot arm64 ACPI properly with table versions predating 5.1.
>>
>> If firmware provides ACPI tables with ACPI version less than 5.1,
>> OS will be messed up with those information and have no way to init
>
> Nit: "that information"
>
> or
>
> "...OS has no way to retrieve the configuration data that is necessary
> to init SMP boot protocol and the GIC properly, so.."
>
>> smp and GIC, so disable ACPI if we get an FADT table with version
>> less that 5.1.
>>
>
> Patch should be reordered in the series and must be sequenced before
> patch 5 for bisectability (that patch implements DT unflattening if ACPI
> is disabled), or squashed with previous patches.

OK, I will reorder this patch set and update the change log above.

Thanks
Hanjun

[Hanjun Guo]

On 2015年01月16日 17:49, Catalin Marinas wrote:
> On Wed, Jan 14, 2015 at 03:04:54PM +0000, Hanjun Guo wrote:
>> Since PCI is not required in ACPI spec and ARM can run without
>> it, introduce some stub functions to make PCI optional for ACPI,
>> and make ACPI core run without CONFIG_PCI on ARM64.
>>
>> When PCI is enabled on ARM64, ACPI core will need some PCI functions
>> to make it functional, so introduce some empty functions here and
>> implement it later.
>>
>> Since ACPI on X86 and IA64 depends on PCI and this patch only makes
>> PCI optional for ARM64, it will not break anything on X86 and IA64.

>>
>> Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
>> Tested-by: Yijing Wang <wangy...@huawei.com>

>> Signed-off-by: Hanjun Guo <hanju...@linaro.org>
>
> Is this patch still required, now that we have PCI for arm64? I know the
> ACPI spec doesn't require PCI but do we expect any arm64 servers aimed
> at ACPI without PCIe?

I think so, how about make ACPI depends on PCI on ARM64 too?

>
> Anyway, that's not the main point, see more below.
>
>> diff --git a/arch/arm64/include/asm/pci.h b/arch/arm64/include/asm/pci.h
>> index 872ba93..fded096 100644
>> --- a/arch/arm64/include/asm/pci.h
>> +++ b/arch/arm64/include/asm/pci.h
>> @@ -24,6 +24,12 @@
>> */
>> #define PCI_DMA_BUS_IS_PHYS (0)
>>
>> +static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
>> +{
>> + /* no legacy IRQ on arm64 */
>> + return -ENODEV;
>> +}
>> +
>> extern int isa_dma_bridge_buggy;
>>
>> #ifdef CONFIG_PCI
>> diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c
>> index ce5836c..42fb195 100644
>> --- a/arch/arm64/kernel/pci.c
>> +++ b/arch/arm64/kernel/pci.c
>> @@ -10,6 +10,7 @@
>> *
>> */
>>
>> +#include <linux/acpi.h>
>> #include <linux/init.h>
>> #include <linux/io.h>
>> #include <linux/kernel.h>
>> @@ -68,3 +69,30 @@ void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent)
>> bus->domain_nr = domain;
>> }
>> #endif
>> +
>> +/*
>> + * raw_pci_read/write - Platform-specific PCI config space access.
>> + *
>> + * Default empty implementation. Replace with an architecture-specific setup
>> + * routine, if necessary.
>> + */
>> +int raw_pci_read(unsigned int domain, unsigned int bus,
>> + unsigned int devfn, int reg, int len, u32 *val)
>> +{

>> + return -EINVAL;
>> +}
>> +

>> +int raw_pci_write(unsigned int domain, unsigned int bus,
>> + unsigned int devfn, int reg, int len, u32 val)
>> +{

>> + return -EINVAL;
>> +}
>> +

>> +#ifdef CONFIG_ACPI
>> +/* Root bridge scanning */
>> +struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
>> +{
>> + /* TODO: Should be revisited when implementing PCI on ACPI */
>> + return NULL;
>> +}
>> +#endif
>
> Do these functions have anything to do with the subject? You add them in
> arch/arm64/kernel/pci.c which is compiled only when CONFIG_PCI while the
> commit log implies that you add them to allow CONFIG_PCI to be off.

My bad, I can update the change log to make it explicit it is needed
when PCI is enabled.

>
> When PCI is enabled and the above functions are compiled in, do they
> need to return any useful data or just -EINVAL. Are they ever called?

They will be called if PCI root bridge is defined in DSDT, should I
print some warning message before it is implemented?

>
>> diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
>> index 39f3ec1..c346011 100644
>> --- a/drivers/acpi/Makefile
>> +++ b/drivers/acpi/Makefile
>> @@ -43,7 +43,7 @@ acpi-y += processor_core.o
>> acpi-$(CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC) += processor_pdc.o
>> acpi-y += ec.o
>> acpi-$(CONFIG_ACPI_DOCK) += dock.o
>> -acpi-y += pci_root.o pci_link.o pci_irq.o
>> +acpi-$(CONFIG_PCI) += pci_root.o pci_link.o pci_irq.o
>> acpi-y += acpi_lpss.o
>> acpi-y += acpi_platform.o
>> acpi-y += acpi_pnp.o
>> diff --git a/drivers/acpi/internal.h b/drivers/acpi/internal.h
>> index 163e82f..c5ff8ba 100644
>> --- a/drivers/acpi/internal.h
>> +++ b/drivers/acpi/internal.h
>> @@ -26,8 +26,13 @@
>> acpi_status acpi_os_initialize1(void);
>> int init_acpi_device_notify(void);
>> int acpi_scan_init(void);
>> +#ifdef CONFIG_PCI
>> void acpi_pci_root_init(void);
>> void acpi_pci_link_init(void);
>> +#else
>> +static inline void acpi_pci_root_init(void) {}
>> +static inline void acpi_pci_link_init(void) {}
>> +#endif
>> void acpi_processor_init(void);
>> void acpi_platform_init(void);
>> void acpi_pnp_init(void);
>
> That's a good clean-up.

If we make ACPI depends on PCI on ARM64, these two stub functions
are not needed anymore.

>
>> diff --git a/include/linux/pci.h b/include/linux/pci.h
>> index 360a966..1476a66 100644
>> --- a/include/linux/pci.h
>> +++ b/include/linux/pci.h
>> @@ -564,15 +564,6 @@ struct pci_ops {
>> int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
>> };
>>
>> -/*
>> - * ACPI needs to be able to access PCI config space before we've done a
>> - * PCI bus scan and created pci_bus structures.
>> - */
>> -int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
>> - int reg, int len, u32 *val);
>> -int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
>> - int reg, int len, u32 val);
>> -
>> struct pci_bus_region {
>> dma_addr_t start;
>> dma_addr_t end;
>> @@ -1329,6 +1320,16 @@ typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
>> unsigned int command_bits, u32 flags);
>> void pci_register_set_vga_state(arch_set_vga_state_t func);
>>
>> +/*
>> + * ACPI needs to be able to access PCI config space before we've done a
>> + * PCI bus scan and created pci_bus structures.
>> + */
>> +int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
>> + int reg, int len, u32 *val);
>> +int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
>> + int reg, int len, u32 val);
>> +void pcibios_penalize_isa_irq(int irq, int active);
>> +
>> #else /* CONFIG_PCI is not enabled */
>>
>> /*
>> @@ -1430,6 +1431,23 @@ static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
>> unsigned int devfn)
>> { return NULL; }
>>
>> +static inline struct pci_bus *pci_find_bus(int domain, int busnr)
>> +{ return NULL; }
>> +
>> +static inline int pci_bus_write_config_byte(struct pci_bus *bus,
>> + unsigned int devfn, int where, u8 val)
>> +{ return -ENOSYS; }
>> +
>> +static inline int raw_pci_read(unsigned int domain, unsigned int bus,
>> + unsigned int devfn, int reg, int len, u32 *val)
>> +{ return -ENOSYS; }
>> +
>> +static inline int raw_pci_write(unsigned int domain, unsigned int bus,
>> + unsigned int devfn, int reg, int len, u32 val)
>> +{ return -ENOSYS; }
>
> So you implement the !CONFIG_PCI functions here to return -ENOSYS while
> the arm64 CONFIG_PCI ones would return -EINVAL. I'm confused.

return -ENOSYS in the arm64 CONFIG_PCI ones next version :)

[Hanjun Guo]

On 2015年01月16日 18:10, Catalin Marinas wrote:
> On Thu, Jan 15, 2015 at 08:04:37PM +0000, Jason Cooper wrote:
>> On Thu, Jan 15, 2015 at 07:02:20PM +0000, Mark Brown wrote:

>>> On Thu, Jan 15, 2015 at 06:23:47PM +0000, Catalin Marinas wrote:
>>>> On Thu, Jan 15, 2015 at 04:26:20PM +0000, Grant Likely wrote:
>>>
>>>>> I'll get right to the point: Can we please have this series queued up
>>>>> for v3.20?
>>>
>>>> Before you even ask for this, please look at the patches and realise
>>>> that there is a complete lack of Reviewed-by tags on the code (well,
>>>> apart from trivial Kconfig changes). In addition, the series touches on
>>>> other subsystems like clocksource, irqchip, acpi and I don't see any
>>>> acks from the corresponding maintainers. So even if I wanted to merge
>>>> the series, there is no way it can be done without additional
>>>> reviews/acks. On the document (last patch), I'd like to see a statement
>>>

>>> There's probably a bit of a process problem here - these patches are all
>>> being posted as part of big and apparently controversial threads with
>>> subject lines in the form "ARM / ACPI:" so people could be forgiven for
>>> just not even reading the e-mails enough to notice changes to their
>>> subsystems. Is it worth posting those patches separately more directly
>>> to the relevant maintainers?
>>
>> I think it's beneficial to post the entire series as one thread, but to
>> change the subject line of each patch to adequately reflect the affected
>> subsystem.
>
> Indeed, keeping the series as one thread is better. Apart from a
> slightly less misleading subject, I suggest Hanjun that he passes each
> patch via get_maintainer.pl and adds the corresponding Cc: lines to the
> commit log. I think that's a clearer way keep track of who needs to
> ack/review the patches.

I already checked all the patches with get_maintainer.pl, and CC the
maintainers in the CC list, I will add the corresponding Cc: lines in
next version.

[Jon Masters]

Hi Folks,

Sorry for top posting from bed. The mainstream servers will all likely do PCIe but there are several that may not. They should not be excluded. That said, if we booted a previously built kernel on a system without an MCFG and got no ECAM/root then things would probably still work.

I think it'll work out either way but for the record there is no requirement to do PCIe on ARM servers that conform to spec.

Jon.

--
Computer Architect | Sent from my #ARM Powered Mobile Device

On Jan 18, 2015 1:26 AM, Hanjun Guo <hanju...@linaro.org> wrote:
>
> On 2015年01月16日 17:49, Catalin Marinas wrote:
> > On Wed, Jan 14, 2015 at 03:04:54PM +0000, Hanjun Guo wrote:

To unsubscribe from this list: send the line "unsubscribe linux-acpi" in

[Hanjun Guo]

On 2015年01月18日 14:31, Jon Masters wrote:
> Hi Folks,
>
> Sorry for top posting from bed. The mainstream servers will all likely do
> PCIe but there are several that may not. They should not be excluded.
That said,
>if we booted a previously built kernel on a system without an MCFG and
> got no ECAM/root then things would probably still work.
>
> I think it'll work out either way but for the record there is no requirement to do PCIe on ARM servers that conform to spec.

OK, Catalin already said that was not the main point of the
comments for this patch, I think the title and change log
of the patch is inconsistent with the code makes Catalin confused,
I will update them in next version.

Thanks
Hanjun
--

[Graeme Gregory]

On Sun, Jan 18, 2015 at 02:46:35PM +0800, Hanjun Guo wrote:
> On 2015年01月18日 14:31, Jon Masters wrote:
> >Hi Folks,
> >
> >Sorry for top posting from bed. The mainstream servers will all likely do
> > PCIe but there are several that may not. They should not be excluded. That
> said,
> >if we booted a previously built kernel on a system without an MCFG and
> > got no ECAM/root then things would probably still work.
> >
> >I think it'll work out either way but for the record there is no requirement to do PCIe on ARM servers that conform to spec.
>
> OK, Catalin already said that was not the main point of the
> comments for this patch, I think the title and change log
> of the patch is inconsistent with the code makes Catalin confused,
> I will update them in next version.
>

Well what we are talking about is the presence of CONFIG_PCI=y which even
in Jons case will be true as he wants to run the same kernel on both
sets of hardware.

Now the architecture has PCI support I think its safe to remove the make
PCI optional part of the patch as this should be handled runtime not
compile time.

Graeme

[Jon Masters]

On 01/18/2015 04:29 AM, Graeme Gregory wrote:
> On Sun, Jan 18, 2015 at 02:46:35PM +0800, Hanjun Guo wrote:
>> On 2015年01月18日 14:31, Jon Masters wrote:
>>> Hi Folks,
>>>
>>> Sorry for top posting from bed. The mainstream servers will all likely do
>>> PCIe but there are several that may not. They should not be excluded. That
>> said,
>>> if we booted a previously built kernel on a system without an MCFG and
>>> got no ECAM/root then things would probably still work.
>>>
>>> I think it'll work out either way but for the record there is no requirement to do PCIe on ARM servers that conform to spec.
>>
>> OK, Catalin already said that was not the main point of the
>> comments for this patch, I think the title and change log
>> of the patch is inconsistent with the code makes Catalin confused,
>> I will update them in next version.
>>
> Well what we are talking about is the presence of CONFIG_PCI=y which even
> in Jons case will be true as he wants to run the same kernel on both
> sets of hardware.

Yup. And btw, the ACPI+PCI use case works beautifully already today. I
will followup to my other Tested-by with a bit more detail later, but
these patches have successfully been used on a wide range of PCIe based
hardware already (I personally have tried a number of 10G network cards,
SATA, USB, and even a graphics card or two for giggles).

Jon.

[Hanjun Guo]

On 2015年01月18日 17:29, Graeme Gregory wrote:
> On Sun, Jan 18, 2015 at 02:46:35PM +0800, Hanjun Guo wrote:
>> On 2015年01月18日 14:31, Jon Masters wrote:
>>> Hi Folks,
>>>
>>> Sorry for top posting from bed. The mainstream servers will all likely do
>>> PCIe but there are several that may not. They should not be excluded. That
>> said,
>>> if we booted a previously built kernel on a system without an MCFG and
>>> got no ECAM/root then things would probably still work.
>>>
>>> I think it'll work out either way but for the record there is no requirement to do PCIe on ARM servers that conform to spec.
>>
>> OK, Catalin already said that was not the main point of the
>> comments for this patch, I think the title and change log
>> of the patch is inconsistent with the code makes Catalin confused,
>> I will update them in next version.
>>
> Well what we are talking about is the presence of CONFIG_PCI=y which even
> in Jons case will be true as he wants to run the same kernel on both
> sets of hardware.
>
> Now the architecture has PCI support I think its safe to remove the make
> PCI optional part of the patch as this should be handled runtime not
> compile time.

I missed that part, must be something wrong work in Sunday :)
I will update the patch with ACPI depends on PCI, which makes
thing much simpler.

Thanks
Hanjun

[Catalin Marinas]

On Sun, Jan 18, 2015 at 09:29:56AM +0000, Graeme Gregory wrote:
> On Sun, Jan 18, 2015 at 02:46:35PM +0800, Hanjun Guo wrote:
> > On 2015年01月18日 14:31, Jon Masters wrote:
> > >Hi Folks,
> > >
> > >Sorry for top posting from bed. The mainstream servers will all likely do
> > > PCIe but there are several that may not. They should not be excluded. That
> > said,
> > >if we booted a previously built kernel on a system without an MCFG and
> > > got no ECAM/root then things would probably still work.
> > >
> > >I think it'll work out either way but for the record there is no requirement to do PCIe on ARM servers that conform to spec.
> >
> > OK, Catalin already said that was not the main point of the
> > comments for this patch, I think the title and change log
> > of the patch is inconsistent with the code makes Catalin confused,
> > I will update them in next version.
>
> Well what we are talking about is the presence of CONFIG_PCI=y which even
> in Jons case will be true as he wants to run the same kernel on both
> sets of hardware.
>
> Now the architecture has PCI support I think its safe to remove the make
> PCI optional part of the patch as this should be handled runtime not
> compile time.

I agree, if we never see a reason to build a kernel image with
!PCI && ACPI, we can simplify this patch.

--
Catalin

[Catalin Marinas]

[...]

> > When PCI is enabled and the above functions are compiled in, do they
> > need to return any useful data or just -EINVAL. Are they ever called?
>
> They will be called if PCI root bridge is defined in DSDT, should I
> print some warning message before it is implemented?

My point: do they need to return real data when a PCI root bridge is
defined in DSDT or you always expect them to always return some -E*? Can
you explain why?

--
Catalin

[Catalin Marinas]

On Wed, Jan 14, 2015 at 03:04:53PM +0000, Hanjun Guo wrote:
> From: Graeme Gregory <graeme....@linaro.org>
>
> If the early boot methods of acpi are happy that we have valid ACPI
> tables and acpi=force has been passed, then do not unflat devicetree
> effectively disabling further hardware probing from DT.

>
> Tested-by: Suravee Suthikulpanit <Suravee.Su...@amd.com>
> Tested-by: Yijing Wang <wangy...@huawei.com>

> Signed-off-by: Graeme Gregory <graeme....@linaro.org>
> Signed-off-by: Hanjun Guo <hanju...@linaro.org>
> ---
> arch/arm64/kernel/setup.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
> index 4580ed3..5d139e1 100644
> --- a/arch/arm64/kernel/setup.c
> +++ b/arch/arm64/kernel/setup.c
> @@ -411,7 +411,8 @@ void __init setup_arch(char **cmdline_p)
> efi_idmap_init();
> early_ioremap_reset();
>
> - unflatten_device_tree();
> + if (acpi_disabled)
> + unflatten_device_tree();

Nitpick: you could actually squash this patch into the previous one to
keep the acpi disable/enable logic in one place.

[Catalin Marinas]

On Wed, Jan 14, 2015 at 03:04:52PM +0000, Hanjun Guo wrote:
> From: Al Stone <al.s...@linaro.org>
>
> Introduce one early parameters "off" and "force" for "acpi", acpi=off
> will be the default behavior for ARM64, so introduce acpi=force to
> enable ACPI on ARM64.
>
> Disable ACPI before early parameters parsed, and enable it to pass
> "acpi=force" if people want use ACPI on ARM64. This ensures DT be
> the prefer one if ACPI table and DT both are provided at this moment.
[...]
> --- a/arch/arm64/kernel/setup.c
> +++ b/arch/arm64/kernel/setup.c
> @@ -62,6 +62,7 @@
> #include <asm/memblock.h>
> #include <asm/psci.h>
> #include <asm/efi.h>
> +#include <asm/acpi.h>
>
> unsigned int processor_id;
> EXPORT_SYMBOL(processor_id);
> @@ -388,6 +389,8 @@ void __init setup_arch(char **cmdline_p)
> early_fixmap_init();
> early_ioremap_init();
>
> + disable_acpi();
> +
> parse_early_param();
>
> /*

Did we get to any conclusion here? DT being the preferred one is fine
when both DT and ACPI are present but do we still want the kernel to
ignore ACPI altogether if DT is not present? It's a bit harder to detect
the presence of DT at this point since the EFI_STUB added one already. I
guess we could move the "acpi=force" argument passing to EFI_STUB if no
DT is present at boot.

[Ard Biesheuvel]

Since the EFI stub populates the /chosen node in DT, I would prefer
for it to add a property there to indicate whether it created the DT
from scratch rather than adding ACPI specific stuff in there (even if
it is just a string to concatenate)

--
Ard.

[Catalin Marinas]

On Wed, Jan 14, 2015 at 03:04:55PM +0000, Hanjun Guo wrote:
> --- a/arch/arm64/kernel/acpi.c
> +++ b/arch/arm64/kernel/acpi.c
[...]
> @@ -64,8 +88,13 @@ void __init acpi_boot_table_init(void)
> return;
>
> /* Initialize the ACPI boot-time table parser. */
> - if (acpi_table_init())
> + if (acpi_table_init()) {
> disable_acpi();
> + return;
> + }
> +
> + if (acpi_table_parse(ACPI_SIG_FADT, acpi_parse_fadt))
> + pr_err("Can't find FADT or error happened during parsing FADT\n");
> }

Do you need a disable_acpi() call here as well?

--
Catalin

[Catalin Marinas]

This works for me. So we could pass "acpi=force" in EFI stub if it
created the DT from scratch *and* ACPI tables are present (can it detect
the latter? And maybe it could print something if none are available).
If that works, the actual kernel can assume that ACPI needs to be
explicitly enabled via acpi=force, irrespective of how much information
it has in DT.

--
Catalin

[Ard Biesheuvel]

Erm, that is not at all what I meant. What I meant was, that if it is
interesting to the kernel proper to know whether the DT was created
from scratch by the stub rather than received from the firmware, we
can record that particular fact in the /chosen node, and nothing else.
How this is interpreted is up to the kernel proper entirely.

Note that the stub may outlive many subsequent kexec reboots, so
dividing policy like this across the stub/kernel boundary is asking
for trouble imo. For instance, booting with a DT via kexec would be
impossible unless we add special handling for this case, which is
exactly what I tried to avoid with my latest virtmap series.

--
Ard.

[Catalin Marinas]

That works as well and I agree with you that splitting the decision
between EFI stub and the kernel could cause trouble.

Basically what we need is to know whether DT has platform description or
just the chosen node. There could be many ways to achieve this but EFI
stub passing such information is a good place (and acpi=force went a bit
too far ;)).

> Note that the stub may outlive many subsequent kexec reboots, so
> dividing policy like this across the stub/kernel boundary is asking
> for trouble imo. For instance, booting with a DT via kexec would be
> impossible unless we add special handling for this case, which is
> exactly what I tried to avoid with my latest virtmap series.

I haven't paid much attention to the kexec series yet but I assume a
kexec'ed kernel doesn't go through EFI stub again.

--
Catalin

[Grant Likely]

On Mon, 19 Jan 2015 13:51:45 +0000

Ditto for me. I think this is a fine solution. And, yes, the stub can
easily detect the presence of ACPI by looking in the UEFI config table.

g.

[Jon Masters]

I get the point behind doing this, but could we not have it pass in a
different parameter than =force? Perhaps something new? I'd like to
separate out the case that it was enabled automatically vs explicitly
forced on by a user wanting to use ACPI on a system with both tables.

Jon.

[Catalin Marinas]

Ard had a point, so we should probably not pass acpi=force from EFI stub
(especially since a user may explicitly pass acpi=off irrespective of DT
presence). Some other property in the chosen node? It's not even an ABI
since that's a contract between EFI stub and the rest of the kernel, so
an in-kernel only interface.

--
Catalin

[Mark Rutland]

Not strictly true once kexec is in place. Then it becomes a stub ->
kernel -> kernel -> kernel -> ... interface, alnog with the rest of the
properties the stub puts in the DTB.

Having something like /chosen/linux,uefi-stub-generated-dtb sounds sane
regardless.

Mark.