Google Groups no longer supports new Usenet posts or subscriptions. Historical content remains viewable.
Dismiss

[PATCH] x86, quirks: Add workaround for AMD F16h Erratum792

4 views
Skip to first unread message

Aravind Gopalakrishnan

unread,
Jan 17, 2014, 1:30:02 PM1/17/14
to
The workaround for this Erratum is included in AGESA. But BIOSes spun
only after Jan2014 will have the fix (atleast server versions of the
chip). The erratum affects both client and server platforms and since
we cannot say with certainity that ALL BIOSes on systems out in the
field will have the fix, we should probably insulate ourselves in case
BIOS does not do the right thing or someone is using old BIOSes.

Refer Revision Guide for AMD F16h models 00h-0fh, document 51810
Rev. 3.04, November2013 for details on the Erratum.

Tested the patch on Fam16h server platform and works fine.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gop...@amd.com>
---
arch/x86/kernel/quirks.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)

diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c
index 04ee1e2..e55ae02 100644
--- a/arch/x86/kernel/quirks.c
+++ b/arch/x86/kernel/quirks.c
@@ -571,3 +571,34 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F5,
quirk_amd_nb_node);

#endif
+
+#if defined(CONFIG_PCI)
+/*
+ * Apply AMD Fam16h Erratum792
+ * see Revision Guide for AMD F16h models 00h-0fh,
+ * document 51810 rev. 3.04, Nov 2013
+ */
+static void quirk_amd_dram_scrub(struct pci_dev *dev)
+{
+ u32 val;
+
+ /* Suggested workaround:
+ * set D18F3x58[4:0] = 00h and set D18F3x5C[0] = 0b
+ */
+ pci_read_config_dword(dev, 0x58, &val);
+ if (val & 0x1F) {
+ val &= ~(0x1F);
+ pci_write_config_dword(dev, 0x58, val);
+ }
+
+ pci_read_config_dword(dev, 0x5C, &val);
+ if (val & BIT(0)) {
+ val &= ~BIT(0);
+ pci_write_config_dword(dev, 0x5c, val);
+ }
+}
+
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3,
+ quirk_amd_dram_scrub);
+
+#endif
--
1.7.9.5


--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majo...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/

Ingo Molnar

unread,
Jan 20, 2014, 2:10:02 AM1/20/14
to
The reference to the erratum is useful for people who want to see more
details, but at least a short description of the problem being fixed
and systems affected by the quirk is needed. 'DRAM scrub' is not very
informative.

Thanks,

Ingo

Aravind Gopalakrishnan

unread,
Jan 21, 2014, 2:40:02 PM1/21/14
to
On 1/20/2014 1:07 AM, Ingo Molnar wrote:
> * Aravind Gopalakrishnan <Aravind.Gop...@amd.com> wrote:
>
>> +
>> +#if defined(CONFIG_PCI)
>> +/*
>> + * Apply AMD Fam16h Erratum792
>> + * see Revision Guide for AMD F16h models 00h-0fh,
>> + * document 51810 rev. 3.04, Nov 2013
>> + */
>> +static void quirk_amd_dram_scrub(struct pci_dev *dev)
> The reference to the erratum is useful for people who want to see more
> details, but at least a short description of the problem being fixed
> and systems affected by the quirk is needed. 'DRAM scrub' is not very
> informative.
>
>
Ok, I'll reword the comment in a V2.
But there's an internal discussion going on about the erratum, so I'll
hold off spinning a V2 until that's over..

Thanks,
-Aravind.

Aravind Gopalakrishnan

unread,
Jan 23, 2014, 5:00:02 PM1/23/14
to
On 1/21/2014 1:32 PM, Aravind Gopalakrishnan wrote:
> On 1/20/2014 1:07 AM, Ingo Molnar wrote:
>> * Aravind Gopalakrishnan <Aravind.Gop...@amd.com> wrote:
>>
>>> +
>>> +#if defined(CONFIG_PCI)
>>> +/*
>>> + * Apply AMD Fam16h Erratum792
>>> + * see Revision Guide for AMD F16h models 00h-0fh,
>>> + * document 51810 rev. 3.04, Nov 2013
>>> + */
>>> +static void quirk_amd_dram_scrub(struct pci_dev *dev)
>> The reference to the erratum is useful for people who want to see more
>> details, but at least a short description of the problem being fixed
>> and systems affected by the quirk is needed. 'DRAM scrub' is not very
>> informative.
>>
>>
> Ok, I'll reword the comment in a V2.
> But there's an internal discussion going on about the erratum, so I'll
> hold off spinning a V2 until that's over..
>
> Thanks,
> -Aravind.

Addressing hpa and Boris' earlier concern
(http://marc.info/?l=linux-kernel&m=138998314409664&w=2)
I can say with better certainty now that there is a coverage hole:
Initial production parts shipped last year, while fix will be in BIOS
only from now onwards; (at least server platforms..)

I have also reworded the comment and function name per Ingo's suggestion..
Sending V2 of patch (rebased off latest tip/master)

Thanks,
-Aravind

Aravind Gopalakrishnan

unread,
Jan 23, 2014, 5:00:02 PM1/23/14
to
The workaround for this Erratum is included in AGESA. But BIOSes spun
only after Jan2014 will have the fix (atleast server versions of the
chip). The erratum affects both embedded and server platforms and since
we cannot say with certainity that ALL BIOSes on systems out in the
field will have the fix, we should probably insulate ourselves in case
BIOS does not do the right thing or someone is using old BIOSes.

Refer Revision Guide for AMD F16h models 00h-0fh, document 51810
Rev. 3.04, November2013 for details on the Erratum.

Tested the patch on Fam16h server platform and works fine.

Changes from V1:
- modify commit msg to say it affects embedded and server
systems..
- per Ingo's suggestion: reword comment, function name
- rebase off latest tip/master

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gop...@amd.com>
---
arch/x86/kernel/quirks.c | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)

diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c
index 04ee1e2..50ce52f 100644
--- a/arch/x86/kernel/quirks.c
+++ b/arch/x86/kernel/quirks.c
@@ -571,3 +571,39 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F5,
quirk_amd_nb_node);

#endif
+
+#if defined(CONFIG_PCI)
+/*
+ * Processor does not ensure DRAM scrub read/write sequence
+ * is atomic wrt accesses to CC6 save state area. Therefore
+ * if a concurrent scrub read/write access is to same address
+ * the entry may appear as if it is not written. This quirk
+ * applies to Fam16h models 00h-0Fh
+ *
+ * see Revision Guide for AMD F16h models 00h-0fh,
+ * document 51810 rev. 3.04, Nov 2013
+ */
+static void amd_disable_seq_and_redirect_scrub(struct pci_dev *dev)
+{
+ u32 val;
+
+ /* Suggested workaround:
+ * set D18F3x58[4:0] = 00h and set D18F3x5C[0] = 0b
+ */
+ pci_read_config_dword(dev, 0x58, &val);
+ if (val & 0x1F) {
+ val &= ~(0x1F);
+ pci_write_config_dword(dev, 0x58, val);
+ }
+
+ pci_read_config_dword(dev, 0x5C, &val);
+ if (val & BIT(0)) {
+ val &= ~BIT(0);
+ pci_write_config_dword(dev, 0x5c, val);
+ }
+}
+
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3,
+ amd_disable_seq_and_redirect_scrub);
+
+#endif
--
1.7.9.5

tip-bot for Aravind Gopalakrishnan

unread,
Jan 25, 2014, 9:30:03 AM1/25/14
to
Commit-ID: fb53a1ab88d14848dc292842e35c3bda3a665997
Gitweb: http://git.kernel.org/tip/fb53a1ab88d14848dc292842e35c3bda3a665997
Author: Aravind Gopalakrishnan <Aravind.Gop...@amd.com>
AuthorDate: Thu, 23 Jan 2014 16:13:32 -0600
Committer: Ingo Molnar <mi...@kernel.org>
CommitDate: Sat, 25 Jan 2014 08:44:19 +0100

x86/quirks: Add workaround for AMD F16h Erratum792

The workaround for this Erratum is included in AGESA. But BIOSes
spun only after Jan2014 will have the fix (atleast server
versions of the chip). The erratum affects both embedded and
server platforms and since we cannot say with certainity that
ALL BIOSes on systems out in the field will have the fix, we
should probably insulate ourselves in case BIOS does not do the
right thing or someone is using old BIOSes.

Refer to Revision Guide for AMD F16h models 00h-0fh, document 51810
Rev. 3.04, November2013 for details on the Erratum.

Tested the patch on Fam16h server platform and it works fine.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gop...@amd.com>
Cc: <h...@hmh.eng.br>
Cc: <Kim....@amd.com>
Cc: <Suravee.Su...@amd.com>
Cc: <b...@suse.de>
Cc: <sherry....@amd.com>
Link: http://lkml.kernel.org/r/1390515212-1824-1-git-send-...@amd.com
[ Minor edits. ]
Signed-off-by: Ingo Molnar <mi...@kernel.org>
---
arch/x86/kernel/quirks.c | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)

diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c
index 04ee1e2..7c6acd4 100644
--- a/arch/x86/kernel/quirks.c
+++ b/arch/x86/kernel/quirks.c
@@ -571,3 +571,40 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F5,
quirk_amd_nb_node);

#endif
+
+#ifdef CONFIG_PCI
+/*
+ * Processor does not ensure DRAM scrub read/write sequence
+ * is atomic wrt accesses to CC6 save state area. Therefore
+ * if a concurrent scrub read/write access is to same address
+ * the entry may appear as if it is not written. This quirk
+ * applies to Fam16h models 00h-0Fh
+ *
+ * See "Revision Guide" for AMD F16h models 00h-0fh,
+ * document 51810 rev. 3.04, Nov 2013
+ */
+static void amd_disable_seq_and_redirect_scrub(struct pci_dev *dev)
+{
+ u32 val;
+
+ /*
+ * Suggested workaround:
+ * set D18F3x58[4:0] = 00h and set D18F3x5C[0] = 0b
+ */
+ pci_read_config_dword(dev, 0x58, &val);
+ if (val & 0x1F) {
+ val &= ~(0x1F);
+ pci_write_config_dword(dev, 0x58, val);
+ }
+
+ pci_read_config_dword(dev, 0x5C, &val);
+ if (val & BIT(0)) {
+ val &= ~BIT(0);
+ pci_write_config_dword(dev, 0x5c, val);
+ }
+}
+
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3,
+ amd_disable_seq_and_redirect_scrub);
+
+#endif
--
0 new messages