[PATCH 00/13] Allwinner H3 DE2 basical support

[Icenowy Zheng]

Allwinner H3 features a "Display Engine 2.0", which needs some support
to be present in the DRM driver.

This patchset is now a basical version, which dropped some features I
used to submitted:
- TVE support (not so high priority now)
- Multi-pipeline support (also not so high priority now due to no TVE)

The last 6 patches are only used for testing this patchset, and they're
going to be sent by Jernej Skrabec after this patchset is applied.

Icenowy Zheng (9):
dt-bindings: update the binding for Allwinner H3 DE2 support
drm: sun4i: add support for H3 mixers
drm: sun4i: add support for H3's TCON
drm: sun4i: add compatible for H3 display engine
clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3
clk: sunxi-ng: export CLK_PLL_DE for H3
ARM: sun8i: h3: add display engine pipeline barebone
[NOT FOR REVIEW NOW] ARM: sun8i: h3: enable DesignWare HDMI controller
[NOT FOR REVIEW NOW] ARM: sun8i: h3: enable HDMI output on Orange Pi
PC

Jernej Skrabec (4):
[NOT FOR REVIEW NOW] drm: bridge: Enable polling hpd event in dw_hdmi
[NOT FOR REVIEW NOW] drm: bridge: Add a pre_init function for the
dw_hdmi driver
[NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3
HDMI clock
[NOT FOR REVIEW NOW] drm: sun4i: Add a glue for the DesignWare HDMI
controller in H3

.../bindings/display/sunxi/sun4i-drm.txt | 25 +-
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 16 +
arch/arm/boot/dts/sun8i-h3.dtsi | 205 +++++++++
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 4 +-
drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 3 +-
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 9 +-
drivers/gpu/drm/sun4i/Kconfig | 9 +
drivers/gpu/drm/sun4i/Makefile | 1 +
drivers/gpu/drm/sun4i/sun4i_drv.c | 2 +
drivers/gpu/drm/sun4i/sun4i_tcon.c | 43 +-
drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 +
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 462 +++++++++++++++++++++
drivers/gpu/drm/sun4i/sun8i_mixer.c | 18 +
include/drm/bridge/dw_hdmi.h | 2 +
include/dt-bindings/clock/sun8i-h3-ccu.h | 2 +
15 files changed, 781 insertions(+), 21 deletions(-)
create mode 100644 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c

--
2.13.0

[Icenowy Zheng]

Allwinner H3 features a "Display Engine 2.0".

Add device tree bindings for the following parts:
- H3 TCONs
- H3 Mixers
- H3 Display engine

Signed-off-by: Icenowy Zheng <ice...@aosc.io>
---
.../bindings/display/sunxi/sun4i-drm.txt | 25 ++++++++++++++++++----
1 file changed, 21 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 2ee6ff0ef98e..92512953943e 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -87,18 +87,17 @@ Required properties:
* allwinner,sun6i-a31-tcon
* allwinner,sun6i-a31s-tcon
* allwinner,sun8i-a33-tcon
+ * allwinner,sun8i-h3-tcon
* allwinner,sun8i-v3s-tcon
- reg: base address and size of memory-mapped region
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the TCON. Three are needed:
- 'ahb': the interface clocks
- - 'tcon-ch0': The clock driving the TCON channel 0
- resets: phandles to the reset controllers driving the encoder
- "lcd": the reset line for the TCON channel 0

- clock-names: the clock names mentioned above
- reset-names: the reset names mentioned above
- - clock-output-names: Name of the pixel clock created

- ports: A ports node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. The
@@ -112,7 +111,23 @@ Required properties:
channel the endpoint is associated to. If that property is not
present, the endpoint number will be used as the channel number.

-On SoCs other than the A33 and V3s, there is one more clock required:
+For the following compatibles:
+ * allwinner,sun5i-a13-tcon
+ * allwinner,sun6i-a31-tcon
+ * allwinner,sun6i-a31s-tcon
+ * allwinner,sun8i-a33-tcon
+ * allwinner,sun8i-v3s-tcon
+there is one more clock and one more property required:
+ - clocks:
+ - 'tcon-ch0': The clock driving the TCON channel 0
+ - clock-output-names: Name of the pixel clock created
+
+For the following compatibles:
+ * allwinner,sun5i-a13-tcon
+ * allwinner,sun6i-a31-tcon
+ * allwinner,sun6i-a31s-tcon
+ * allwinner,sun8i-h3-tcon
+there is one more clock required:
- 'tcon-ch1': The clock driving the TCON channel 1

DRC
@@ -207,6 +222,8 @@ supported.
Required properties:
- compatible: value must be one of:
* allwinner,sun8i-v3s-de2-mixer
+ * allwinner,sun8i-h3-de2-mixer0
+ * allwinner,sun8i-h3-de2-mixer1
- reg: base address and size of the memory-mapped region.
- clocks: phandles to the clocks feeding the mixer
* bus: the mixer interface clock
@@ -218,7 +235,6 @@ Required properties:
Documentation/devicetree/bindings/media/video-interfaces.txt. The
first port should be the input endpoints, the second one the output

-
Display Engine Pipeline
-----------------------

@@ -233,6 +249,7 @@ Required properties:
* allwinner,sun6i-a31-display-engine
* allwinner,sun6i-a31s-display-engine
* allwinner,sun8i-a33-display-engine
+ * allwinner,sun8i-h3-display-engine
* allwinner,sun8i-v3s-display-engine

- allwinner,pipelines: list of phandle to the display engine
--
2.13.0

[Icenowy Zheng]

From: Icenowy Zheng <ice...@aosc.xyz>

Allwinner H3 has two special TCONs without channel 0.

Add support for this kind of TCON.

Signed-off-by: Icenowy Zheng <ice...@aosc.io>
---

drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
drivers/gpu/drm/sun4i/sun4i_tcon.c | 43 +++++++++++++++++++++++++++-----------
drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 +
3 files changed, 33 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index ace59651892f..fd99fe8a4df7 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -188,6 +188,7 @@ static bool sun4i_drv_node_is_tcon(struct device_node *node)
of_device_is_compatible(node, "allwinner,sun6i-a31-tcon") ||
of_device_is_compatible(node, "allwinner,sun6i-a31s-tcon") ||
of_device_is_compatible(node, "allwinner,sun8i-a33-tcon") ||
+ of_device_is_compatible(node, "allwinner,sun8i-h3-tcon") ||
of_device_is_compatible(node, "allwinner,sun8i-v3s-tcon");
}

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index d9791292553e..270f09e381a5 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -59,6 +59,7 @@ void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int channel)

/* Disable the TCON's channel */
if (channel == 0) {
+ WARN_ON(!tcon->quirks->has_channel_0);
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
SUN4I_TCON0_CTL_TCON_ENABLE, 0);
clk_disable_unprepare(tcon->dclk);
@@ -78,6 +79,7 @@ void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int channel)

/* Enable the TCON's channel */
if (channel == 0) {
+ WARN_ON(!tcon->quirks->has_channel_0);
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
SUN4I_TCON0_CTL_TCON_ENABLE,
SUN4I_TCON0_CTL_TCON_ENABLE);
@@ -157,6 +159,8 @@ void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
u8 clk_delay;
u32 val = 0;

+ WARN_ON(!tcon->quirks->has_channel_0);
+
/* Configure the dot clock */
clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);

@@ -366,10 +370,12 @@ static int sun4i_tcon_init_clocks(struct device *dev,
}
clk_prepare_enable(tcon->clk);

- tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
- if (IS_ERR(tcon->sclk0)) {
- dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
- return PTR_ERR(tcon->sclk0);
+ if (tcon->quirks->has_channel_0) {
+ tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
+ if (IS_ERR(tcon->sclk0)) {
+ dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
+ return PTR_ERR(tcon->sclk0);
+ }
}

if (tcon->quirks->has_channel_1) {
@@ -551,10 +557,12 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
goto err_free_clocks;
}

- ret = sun4i_dclk_create(dev, tcon);
- if (ret) {
- dev_err(dev, "Couldn't create our TCON dot clock\n");
- goto err_free_clocks;
+ if (tcon->quirks->has_channel_0) {
+ ret = sun4i_dclk_create(dev, tcon);
+ if (ret) {
+ dev_err(dev, "Couldn't create our TCON dot clock\n");
+ goto err_free_clocks;
+ }
}

ret = sun4i_tcon_init_irq(dev, tcon);
@@ -579,7 +587,8 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
return 0;

err_free_dotclock:
- sun4i_dclk_free(tcon);
+ if (tcon->quirks->has_channel_0)
+ sun4i_dclk_free(tcon);
err_free_clocks:
sun4i_tcon_free_clocks(tcon);
err_assert_reset:
@@ -593,7 +602,9 @@ static void sun4i_tcon_unbind(struct device *dev, struct device *master,
struct sun4i_tcon *tcon = dev_get_drvdata(dev);

list_del(&tcon->list);
- sun4i_dclk_free(tcon);
+
+ if (tcon->quirks->has_channel_0)
+ sun4i_dclk_free(tcon);
sun4i_tcon_free_clocks(tcon);
}

@@ -625,23 +636,30 @@ static int sun4i_tcon_remove(struct platform_device *pdev)

static const struct sun4i_tcon_quirks sun5i_a13_quirks = {
.has_unknown_mux = true,
+ .has_channel_0 = true,
.has_channel_1 = true,
};

static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
+ .has_channel_0 = true,
.has_channel_1 = true,
};

static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
+ .has_channel_0 = true,
.has_channel_1 = true,
};

static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
- /* nothing is supported */
+ .has_channel_0 = true,
};

static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
- /* nothing is supported */
+ .has_channel_0 = true,
+};
+
+static const struct sun4i_tcon_quirks sun8i_h3_quirks = {
+ .has_channel_1 = true,
};

static const struct of_device_id sun4i_tcon_of_table[] = {
@@ -649,6 +667,7 @@ static const struct of_device_id sun4i_tcon_of_table[] = {
{ .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
{ .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
{ .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
+ { .compatible = "allwinner,sun8i-h3-tcon", .data = &sun8i_h3_quirks },
{ .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
{ }
};
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index 552c88ec16be..de035e598129 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -145,6 +145,7 @@

struct sun4i_tcon_quirks {
bool has_unknown_mux; /* sun5i has undocumented mux */
+ bool has_channel_0; /* some A83T+ TCONs don't have channel 0*/
bool has_channel_1; /* a33 does not have channel 1 */
};

--
2.13.0

[Icenowy Zheng]

From: Jernej Skrabec <jernej....@siol.net>

When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be set.

Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>

Signed-off-by: Icenowy Zheng <ice...@aosc.io>
---

drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index b1127e8629d9..2ebb3d865b01 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -474,7 +474,7 @@ static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",

static const char * const hdmi_parents[] = { "pll-video" };
static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
- 0x150, 0, 4, 24, 2, BIT(31), 0);
+ 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);

static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
0x154, BIT(31), 0);
--
2.13.0

[Icenowy Zheng]

As we have already the support for the DE2 on Allwinner H3, add the
display engine pipeline device tree nodes to its DTSI file.

The H5 pipeline has some differences and will be enabled later.

Signed-off-by: Icenowy Zheng <ice...@aosc.io>
---

arch/arm/boot/dts/sun8i-h3.dtsi | 170 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 170 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index b36f9f423c39..75ad7b65a7fc 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -41,6 +41,8 @@
*/

#include "sunxi-h3-h5.dtsi"
+#include <dt-bindings/clock/sun8i-de2.h>
+#include <dt-bindings/reset/sun8i-de2.h>

/ {
cpus {
@@ -72,6 +74,174 @@
};
};

+ de: display-engine {
+ compatible = "allwinner,sun8i-h3-display-engine";
+ allwinner,pipelines = <&mixer0>,
+ <&mixer1>;
+ status = "disabled";
+ };
+
+ soc {
+ display_clocks: clock@1000000 {
+ compatible = "allwinner,sun8i-a83t-de2-clk";
+ reg = <0x01000000 0x100000>;
+ clocks = <&ccu CLK_BUS_DE>,
+ <&ccu CLK_DE>;
+ clock-names = "bus",
+ "mod";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ assigned-clocks = <&ccu CLK_DE>;
+ assigned-clock-parents = <&ccu CLK_PLL_DE>;
+ assigned-clock-rates = <432000000>;
+ };
+
+ mixer0: mixer@1100000 {
+ compatible = "allwinner,sun8i-h3-de2-mixer0";
+ reg = <0x01100000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER0>,
+ <&display_clocks CLK_MIXER0>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_MIXER0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mixer0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_mixer0>;
+ };
+
+ mixer0_out_tcon1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon1_in_mixer0>;
+ };
+ };
+ };
+ };
+
+ mixer1: mixer@1200000 {
+ compatible = "allwinner,sun8i-h3-de2-mixer1";
+ reg = <0x01200000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER1>,
+ <&display_clocks CLK_MIXER1>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_WB>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mixer1_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_mixer1>;
+ };
+
+ mixer1_out_tcon1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon1_in_mixer1>;
+ };
+ };
+ };
+ };
+
+ tcon0: lcd-controller@1c0c000 {
+ compatible = "allwinner,sun8i-h3-tcon";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON0>,
+ <&ccu CLK_TCON0>;
+ clock-names = "ahb",
+ "tcon-ch1";
+ resets = <&ccu RST_BUS_TCON0>;
+ reset-names = "lcd";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mixer0_out_tcon0>;
+ };
+
+ tcon0_in_mixer1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mixer1_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
+ tcon1: lcd-controller@1c0d000 {
+ compatible = "allwinner,sun8i-h3-tcon";
+ reg = <0x01c0d000 0x1000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON1>,
+ <&ccu CLK_TVE>;
+ clock-names = "ahb",
+ "tcon-ch1";
+ resets = <&ccu RST_BUS_TCON1>;
+ reset-names = "lcd";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon1_in_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mixer0_out_tcon1>;
+ };
+
+ tcon1_in_mixer1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mixer1_out_tcon1>;
+ };
+ };
+
+ tcon1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
--
2.13.0

[Icenowy Zheng]

From: Jernej Skrabec <jernej....@siol.net>

Some platform glues of DesignWare HDMI controller require some
initialization to be performed before probing the main HDMI controller.

Add a pre_init function for this kind of work.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 3 +++
include/drm/bridge/dw_hdmi.h | 2 ++
2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 6c6466c6297c..1e69b7631cae 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -2343,6 +2343,9 @@ __dw_hdmi_probe(struct platform_device *pdev,
goto err_isfr;
}

+ if (plat_data->pre_init)
+ plat_data->pre_init(plat_data->pre_init_data);
+
/* Product and revision IDs */
hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
| (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
index 182f83283e24..6e109c336ca1 100644
--- a/include/drm/bridge/dw_hdmi.h
+++ b/include/drm/bridge/dw_hdmi.h
@@ -128,6 +128,8 @@ struct dw_hdmi_plat_data {
const struct drm_display_mode *mode);
unsigned long input_bus_format;
unsigned long input_bus_encoding;
+ void (*pre_init)(void *data);
+ void *pre_init_data;

/* Vendor PHY support */
const struct dw_hdmi_phy_ops *phy_ops;
--
2.13.0

[Icenowy Zheng]

Add a compatible string for H3 display engine in sun4i_drv code.

Signed-off-by: Icenowy Zheng <ice...@aosc.io>
---

drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index fd99fe8a4df7..02c80bb7b385 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -314,6 +314,7 @@ static const struct of_device_id sun4i_drv_of_table[] = {
{ .compatible = "allwinner,sun6i-a31-display-engine" },
{ .compatible = "allwinner,sun6i-a31s-display-engine" },
{ .compatible = "allwinner,sun8i-a33-display-engine" },
+ { .compatible = "allwinner,sun8i-h3-display-engine" },
{ .compatible = "allwinner,sun8i-v3s-display-engine" },
{ }
};
--
2.13.0

[Icenowy Zheng]

Allwinner H3 features a PLL named CLK_PLL_DE, and a mod clock for the
"Display Engine 2.0" named CLK_DE. As the name indicated, the CLK_PLL_DE
is a PLL for CLK_DE.

Only CLK_DE and CLK_TVE have a parent of CLK_PLL_DE, and CLK_TVE is also
one part of the display clocks.

So allow CLK_DE to set CLK_PLL_DE (add CLK_SET_RATE_PARENT to it).

Signed-off-by: Icenowy Zheng <ice...@aosc.io>
---

drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c

index d1ab0d713fa6..b1127e8629d9 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -439,7 +439,7 @@ static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",

static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
- 0x104, 0, 4, 24, 3, BIT(31), 0);
+ 0x104, 0, 4, 24, 3, BIT(31), CLK_SET_RATE_PARENT);

static const char * const tcon_parents[] = { "pll-video" };
static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
--
2.13.0

[Icenowy Zheng]

The CLK_PLL_DE is needed to be referenced in device tree for H3, for
both forcing the parent of PLL_DE.

So export it to the device tree binding header.

Signed-off-by: Icenowy Zheng <ice...@aosc.io>
---

drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 3 +--
include/dt-bindings/clock/sun8i-h3-ccu.h | 2 ++
2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
index 1b4baea37d81..add3a7c18212 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
@@ -35,9 +35,8 @@
#define CLK_PLL_PERIPH0_2X 10
#define CLK_PLL_GPU 11
#define CLK_PLL_PERIPH1 12
-#define CLK_PLL_DE 13

-/* The CPUX clock is exported */
+/* The PLL_DE and CPUX clocks is exported */

#define CLK_AXI 15
#define CLK_AHB1 16
diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h
index e139fe5c62ec..5345957a8c2e 100644
--- a/include/dt-bindings/clock/sun8i-h3-ccu.h
+++ b/include/dt-bindings/clock/sun8i-h3-ccu.h
@@ -45,6 +45,8 @@

#define CLK_PLL_PERIPH0 9

+#define CLK_PLL_DE 13
+
#define CLK_CPUX 14

#define CLK_BUS_CE 20
--
2.13.0

[Icenowy Zheng]

From: Jernej Skrabec <jernej....@siol.net>

Some custom phys don't support hpd interrupts. Add support for polling
such events.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>
---

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 60faf2d2bc6b..6c6466c6297c 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1942,7 +1942,11 @@ static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
struct drm_connector *connector = &hdmi->connector;

connector->interlace_allowed = 1;
- connector->polled = DRM_CONNECTOR_POLL_HPD;
+ if (hdmi->phy.ops->setup_hpd)
+ connector->polled = DRM_CONNECTOR_POLL_HPD;
+ else
+ connector->polled = DRM_CONNECTOR_POLL_CONNECT |
+ DRM_CONNECTOR_POLL_DISCONNECT;

drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);

--
2.13.0

[Icenowy Zheng]

The H3 SoC has a DesignWare HDMI controller with some Allwinner-specific
glues.

Add the related device nodes.

Signed-off-by: Icenowy Zheng <ice...@aosc.io>
---

arch/arm/boot/dts/sun8i-h3.dtsi | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 75ad7b65a7fc..cd38d7e04606 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -197,6 +197,11 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
+
+ tcon0_out_hdmi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&hdmi_in_tcon0>;
+ };
};
};
};
@@ -240,6 +245,36 @@
};
};
};
+
+ hdmi: hdmi@1ee0000 {
+ compatible = "allwinner,h3-dw-hdmi";
+ reg = <0x01ee0000 0x10000>,
+ <0x01ef0000 0x10000>;
+ reg-io-width = <1>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI>,
+ <&ccu CLK_HDMI_DDC>;
+ clock-names = "iahb", "isfr", "iddc";
+ resets = <&ccu RST_BUS_HDMI0>, <&ccu RST_BUS_HDMI1>;
+ reset-names = "hdmi", "ddc";

+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+

+ hdmi_in: port@0 {

+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+

+ hdmi_in_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_out_hdmi>;

+ };
+ };
+ };
+ };
};

timer {

--
2.13.0

[Icenowy Zheng]

From: Jernej Skrabec <jernej....@siol.net>

Allwinner H3 features DesignWare HDMI Transmitter paired with custom
PHY.

For now, only video is supported by the driver. However, audio and CEC
are also supported by the hardware.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>
---

drivers/gpu/drm/sun4i/Kconfig | 9 +
drivers/gpu/drm/sun4i/Makefile | 1 +

drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 462 ++++++++++++++++++++++++++++++++++
3 files changed, 472 insertions(+)
create mode 100644 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c

diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
index 06f05302ee75..589502ffe31a 100644
--- a/drivers/gpu/drm/sun4i/Kconfig
+++ b/drivers/gpu/drm/sun4i/Kconfig
@@ -40,6 +40,15 @@ config DRM_SUN4I_BACKEND
do some alpha blending and feed graphics to TCON. If M is
selected the module will be called sun4i-backend.

+config DRM_SUN8I_DW_HDMI
+ tristate "Support for Allwinner version of DesignWare HDMI"
+ depends on DRM_SUN4I
+ select DRM_DW_HDMI
+ help
+ Choose this option if you have an Allwinner SoC with the
+ DesignWare HDMI controller with custom HDMI PHY. If M is
+ selected the module will be called sun8i_dw_hdmi.
+
config DRM_SUN8I_MIXER
tristate "Support for Allwinner Display Engine 2.0 Mixer"
default MACH_SUN8I
diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index 43c753cafc88..9c56173bf140 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_DRM_SUN4I) += sun4i_tv.o
obj-$(CONFIG_DRM_SUN4I_BACKEND) += sun4i-backend.o
obj-$(CONFIG_DRM_SUN4I_HDMI) += sun4i-drm-hdmi.o
obj-$(CONFIG_DRM_SUN8I_MIXER) += sun8i-mixer.o
+obj-$(CONFIG_DRM_SUN8I_DW_HDMI) += sun8i_dw_hdmi.o
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
new file mode 100644
index 000000000000..fa1ecbcf08b8
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
@@ -0,0 +1,462 @@
+/*
+ * Copyright (c) 2017, Jernej Skrabec <jernej....@siol.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+#include <drm/drm_of.h>
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_edid.h>
+#include <drm/bridge/dw_hdmi.h>
+
+#include "sun4i_crtc.h"
+#include "sun4i_tcon.h"
+
+#define SUN8I_HDMI_PHY_REG_POL 0x0000
+
+#define SUN8I_HDMI_PHY_REG_READ_EN 0x0010
+#define SUN8I_HDMI_PHY_REG_READ_EN_MAGIC 0x54524545
+
+#define SUN8I_HDMI_PHY_REG_UNSCRAMBLE 0x0014
+#define SUN8I_HDMI_PHY_REG_UNSCRAMBLE_MAGIC 0x42494E47
+
+#define SUN8I_HDMI_PHY_REG_CTRL 0x0020
+#define SUN8I_HDMI_PHY_REG_UNK1 0x0024
+#define SUN8I_HDMI_PHY_REG_UNK2 0x0028
+#define SUN8I_HDMI_PHY_REG_PLL 0x002c
+#define SUN8I_HDMI_PHY_REG_CLK 0x0030
+#define SUN8I_HDMI_PHY_REG_UNK3 0x0034
+
+#define SUN8I_HDMI_PHY_REG_STATUS 0x0038
+#define SUN8I_HDMI_PHY_REG_STATUS_READY BIT(7)
+#define SUN8I_HDMI_PHY_REG_STATUS_HPD BIT(19)
+
+#define to_sun8i_dw_hdmi(x) container_of(x, struct sun8i_dw_hdmi, x)
+#define set_bits(p, v) writel(readl(p) | (v), p)
+
+struct sun8i_dw_hdmi {
+ struct clk *clk_ddc;
+ struct clk *clk_hdmi;
+ struct device *dev;
+ struct drm_encoder encoder;
+ void __iomem *phy_base;
+ struct dw_hdmi_plat_data plat_data;
+ struct reset_control *rst_ddc;
+ struct reset_control *rst_hdmi;
+};
+
+static u32 sun8i_dw_hdmi_get_divider(int clk_khz)
+{
+ /*
+ * Due to missing documentaion of HDMI PHY, we know correct
+ * settings only for following four PHY dividers. Select one
+ * based on clock speed.
+ */
+ if (clk_khz <= 27000)
+ return 11;
+ else if (clk_khz <= 74250)
+ return 4;
+ else if (clk_khz <= 148500)
+ return 2;
+ else
+ return 1;
+}
+
+static void sun8i_dw_hdmi_encoder_disable(struct drm_encoder *encoder)
+{
+ struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
+ struct sun4i_tcon *tcon = crtc->tcon;
+
+ DRM_DEBUG_DRIVER("Disabling HDMI Output\n");
+
+ sun4i_tcon_channel_disable(tcon, 1);
+}
+
+static void sun8i_dw_hdmi_encoder_enable(struct drm_encoder *encoder)
+{
+ struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
+ struct sun4i_tcon *tcon = crtc->tcon;
+
+ DRM_DEBUG_DRIVER("Enabling HDMI Output\n");
+
+ sun4i_tcon_channel_enable(tcon, 1);
+}
+
+static void sun8i_dw_hdmi_encoder_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adj_mode)
+{
+ struct sun8i_dw_hdmi *hdmi = to_sun8i_dw_hdmi(encoder);
+ struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
+ struct sun4i_tcon *tcon = crtc->tcon;
+ u32 div;
+
+ sun4i_tcon1_mode_set(tcon, mode);
+
+ div = sun8i_dw_hdmi_get_divider(mode->crtc_clock);
+ clk_set_rate(hdmi->clk_hdmi, mode->crtc_clock * 1000 * div);
+ clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
+}
+
+static const struct drm_encoder_helper_funcs sun8i_dw_hdmi_encoder_helper_funcs = {
+ .mode_set = sun8i_dw_hdmi_encoder_mode_set,
+ .enable = sun8i_dw_hdmi_encoder_enable,
+ .disable = sun8i_dw_hdmi_encoder_disable,
+};
+
+static int sun8i_dw_hdmi_phy_init(struct dw_hdmi *hdmi_data, void *data,
+ struct drm_display_mode *mode)
+{
+ struct sun8i_dw_hdmi *hdmi = (struct sun8i_dw_hdmi *)data;
+ u32 div = sun8i_dw_hdmi_get_divider(mode->crtc_clock);
+ u32 val;
+
+ /*
+ * Unfortunately, we don't know much about those magic
+ * numbers. They are taken from Allwinner BSP driver.
+ */
+
+ val = readl(hdmi->phy_base + SUN8I_HDMI_PHY_REG_CTRL);
+ writel(val & ~0xf000, hdmi->phy_base + SUN8I_HDMI_PHY_REG_CTRL);
+
+ switch (div) {
+ case 1:
+ writel(0x30dc5fc0, hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL);
+ writel(0x800863C0, hdmi->phy_base + SUN8I_HDMI_PHY_REG_CLK);
+ mdelay(10);
+ writel(1, hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNK3);
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL, BIT(25));
+ mdelay(200);
+ val = readl(hdmi->phy_base + SUN8I_HDMI_PHY_REG_STATUS);
+ val = (val & 0x1f800) >> 11;
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL,
+ BIT(31) | BIT(30));
+ if (val < 0x3d)
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL,
+ val + 2);
+ else
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL,
+ 0x3f);
+ mdelay(100);
+ writel(0x01FFFF7F, hdmi->phy_base + SUN8I_HDMI_PHY_REG_CTRL);
+ writel(0x8063b000, hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNK1);
+ writel(0x0F8246B5, hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNK2);
+ break;
+ case 2:
+ writel(0x39dc5040, hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL);
+ writel(0x80084381, hdmi->phy_base + SUN8I_HDMI_PHY_REG_CLK);
+ mdelay(10);
+ writel(1, hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNK3);
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL, BIT(25));
+ mdelay(100);
+ val = readl(hdmi->phy_base + SUN8I_HDMI_PHY_REG_STATUS);
+ val = (val & 0x1f800) >> 11;
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL,
+ BIT(31) | BIT(30));
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL, val);
+ writel(0x01FFFF7F, hdmi->phy_base + SUN8I_HDMI_PHY_REG_CTRL);
+ writel(0x8063a800, hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNK1);
+ writel(0x0F81C485, hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNK2);
+ break;
+ case 4:
+ writel(0x39dc5040, hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL);
+ writel(0x80084343, hdmi->phy_base + SUN8I_HDMI_PHY_REG_CLK);
+ mdelay(10);
+ writel(1, hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNK3);
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL, BIT(25));
+ mdelay(100);
+ val = readl(hdmi->phy_base + SUN8I_HDMI_PHY_REG_STATUS);
+ val = (val & 0x1f800) >> 11;
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL,
+ BIT(31) | BIT(30));
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL, val);
+ writel(0x01FFFF7F, hdmi->phy_base + SUN8I_HDMI_PHY_REG_CTRL);
+ writel(0x8063b000, hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNK1);
+ writel(0x0F81C405, hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNK2);
+ break;
+ case 11:
+ writel(0x39dc5040, hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL);
+ writel(0x8008430a, hdmi->phy_base + SUN8I_HDMI_PHY_REG_CLK);
+ mdelay(10);
+ writel(1, hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNK3);
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL, BIT(25));
+ mdelay(100);
+ val = readl(hdmi->phy_base + SUN8I_HDMI_PHY_REG_STATUS);
+ val = (val & 0x1f800) >> 11;
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL,
+ BIT(31) | BIT(30));
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL, val);
+ writel(0x01FFFF7F, hdmi->phy_base + SUN8I_HDMI_PHY_REG_CTRL);
+ writel(0x8063b000, hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNK1);
+ writel(0x0F81C405, hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNK2);
+ break;
+ }
+
+ /*
+ * Condition in original code is a bit weird. This is attempt
+ * to make it more reasonable and it works. It could be that
+ * bits and conditions are related and should be separated.
+ */
+ if (!((mode->flags & DRM_MODE_FLAG_PHSYNC) &&
+ (mode->flags & DRM_MODE_FLAG_PVSYNC))) {
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_POL, 0x300);
+ }
+
+ return 0;
+}
+
+static void sun8i_dw_hdmi_phy_disable(struct dw_hdmi *hdmi_data, void *data)
+{
+ struct sun8i_dw_hdmi *hdmi = (struct sun8i_dw_hdmi *)data;
+
+ writel(7, hdmi->phy_base + SUN8I_HDMI_PHY_REG_CTRL);
+ writel(0, hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL);
+}
+
+static enum drm_connector_status sun8i_dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi_data,
+ void *data)
+{
+ struct sun8i_dw_hdmi *hdmi = (struct sun8i_dw_hdmi *)data;
+ u32 reg_val = readl(hdmi->phy_base + SUN8I_HDMI_PHY_REG_STATUS);
+
+ return !!(reg_val & SUN8I_HDMI_PHY_REG_STATUS_HPD) ?
+ connector_status_connected : connector_status_disconnected;
+}
+
+static const struct dw_hdmi_phy_ops sun8i_dw_hdmi_phy_ops = {
+ .init = &sun8i_dw_hdmi_phy_init,
+ .disable = &sun8i_dw_hdmi_phy_disable,
+ .read_hpd = &sun8i_dw_hdmi_phy_read_hpd,
+};
+
+static void sun8i_dw_hdmi_pre_init(void *data)
+{
+ struct sun8i_dw_hdmi *hdmi = (struct sun8i_dw_hdmi *)data;
+ u32 timeout = 20;
+ u32 val;
+
+ /*
+ * HDMI PHY settings are taken as-is from Allwinner BSP code.
+ * There is no documentation.
+ */
+ writel(0, hdmi->phy_base + SUN8I_HDMI_PHY_REG_CTRL);
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_CTRL, BIT(0));
+ udelay(5);
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_CTRL, BIT(16));
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_CTRL, BIT(1));
+ udelay(10);
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_CTRL, BIT(2));
+ udelay(5);
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_CTRL, BIT(3));
+ udelay(40);
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_CTRL, BIT(19));
+ udelay(100);
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_CTRL, BIT(18));
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_CTRL, 7 << 4);
+
+ /* Note that Allwinner code doesn't fail in case of timeout */
+ while (!(readl(hdmi->phy_base + SUN8I_HDMI_PHY_REG_STATUS) &
+ SUN8I_HDMI_PHY_REG_STATUS_READY)) {
+ if (!timeout--) {
+ dev_warn(hdmi->dev, "HDMI PHY init timeout!\n");
+ break;
+ }
+ udelay(100);
+ }
+
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_CTRL, 0xf << 8);
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_CTRL, BIT(7));
+
+ writel(0x39dc5040, hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL);
+ writel(0x80084343, hdmi->phy_base + SUN8I_HDMI_PHY_REG_CLK);
+ mdelay(10);
+ writel(1, hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNK3);
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL, BIT(25));
+ mdelay(100);
+ val = readl(hdmi->phy_base + SUN8I_HDMI_PHY_REG_STATUS);
+ val = (val & 0x1f800) >> 11;
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL, BIT(31) | BIT(30));
+ set_bits(hdmi->phy_base + SUN8I_HDMI_PHY_REG_PLL, val);
+ writel(0x01FF0F7F, hdmi->phy_base + SUN8I_HDMI_PHY_REG_CTRL);
+ writel(0x80639000, hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNK1);
+ writel(0x0F81C405, hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNK2);
+
+ /* enable read access to HDMI controller */
+ writel(SUN8I_HDMI_PHY_REG_READ_EN_MAGIC,
+ hdmi->phy_base + SUN8I_HDMI_PHY_REG_READ_EN);
+
+ /* descramble register offsets */
+ writel(SUN8I_HDMI_PHY_REG_UNSCRAMBLE_MAGIC,
+ hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNSCRAMBLE);
+}
+
+static const struct drm_encoder_funcs sun8i_dw_hdmi_encoder_funcs = {
+ .destroy = drm_encoder_cleanup,
+};
+
+static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct dw_hdmi_plat_data *plat_data;
+ struct drm_device *drm = data;
+ struct drm_encoder *encoder;
+ struct sun8i_dw_hdmi *hdmi;
+ struct resource *res;
+ int ret;
+
+ if (!pdev->dev.of_node)
+ return -ENODEV;
+
+ hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
+ if (!hdmi)
+ return -ENOMEM;
+
+ plat_data = &hdmi->plat_data;
+ hdmi->dev = &pdev->dev;
+ encoder = &hdmi->encoder;
+
+ encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
+ dev->of_node);
+ /*
+ * If we failed to find the CRTC(s) which this encoder is
+ * supposed to be connected to, it's because the CRTC has
+ * not been registered yet. Defer probing, and hope that
+ * the required CRTC is added later.
+ */
+ if (encoder->possible_crtcs == 0)
+ return -EPROBE_DEFER;
+
+ /* resource 0 is the memory region for the core controller */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ hdmi->phy_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(hdmi->phy_base))
+ return PTR_ERR(hdmi->phy_base);
+
+ hdmi->clk_hdmi = devm_clk_get(dev, "isfr");
+ if (IS_ERR(hdmi->clk_hdmi)) {
+ dev_err(dev, "Could not get hdmi clock\n");
+ return PTR_ERR(hdmi->clk_hdmi);
+ }
+
+ hdmi->clk_ddc = devm_clk_get(dev, "iddc");
+ if (IS_ERR(hdmi->clk_ddc)) {
+ dev_err(dev, "Could not get ddc clock\n");
+ return PTR_ERR(hdmi->clk_ddc);
+ }
+
+ hdmi->rst_hdmi = devm_reset_control_get(dev, "hdmi");
+ if (IS_ERR(hdmi->rst_hdmi)) {
+ dev_err(dev, "Could not get hdmi reset control\n");
+ return PTR_ERR(hdmi->rst_hdmi);
+ }
+
+ hdmi->rst_ddc = devm_reset_control_get(dev, "ddc");
+ if (IS_ERR(hdmi->rst_ddc)) {
+ dev_err(dev, "Could not get dw-hdmi reset control\n");
+ return PTR_ERR(hdmi->rst_ddc);
+ }
+
+ ret = clk_prepare_enable(hdmi->clk_ddc);
+ if (ret) {
+ dev_err(dev, "Cannot enable DDC clock: %d\n", ret);
+ return ret;
+ }
+
+ ret = reset_control_deassert(hdmi->rst_hdmi);
+ if (ret) {
+ dev_err(dev, "Could not deassert hdmi reset control\n");
+ goto err_ddc_clk;
+ }
+
+ ret = reset_control_deassert(hdmi->rst_ddc);
+ if (ret) {
+ dev_err(dev, "Could not deassert ddc reset control\n");
+ goto err_assert_hdmi_reset;
+ }
+
+ drm_encoder_helper_add(encoder, &sun8i_dw_hdmi_encoder_helper_funcs);
+ drm_encoder_init(drm, encoder, &sun8i_dw_hdmi_encoder_funcs,
+ DRM_MODE_ENCODER_TMDS, NULL);
+
+ plat_data->pre_init = &sun8i_dw_hdmi_pre_init,
+ plat_data->pre_init_data = hdmi;
+ plat_data->phy_ops = &sun8i_dw_hdmi_phy_ops,
+ plat_data->phy_name = "sun8i_dw_hdmi_phy",
+ plat_data->phy_data = hdmi;
+
+ ret = dw_hdmi_bind(pdev, encoder, plat_data);
+
+ /*
+ * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
+ * which would have called the encoder cleanup. Do it manually.
+ */
+ if (ret)
+ goto cleanup_encoder;
+
+ return 0;
+
+cleanup_encoder:
+ drm_encoder_cleanup(encoder);
+ reset_control_assert(hdmi->rst_ddc);
+err_assert_hdmi_reset:
+ reset_control_assert(hdmi->rst_hdmi);
+err_ddc_clk:
+ clk_disable_unprepare(hdmi->clk_ddc);
+
+ return ret;
+}
+
+static void sun8i_dw_hdmi_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+ return dw_hdmi_unbind(dev);
+}
+
+static const struct component_ops sun8i_dw_hdmi_ops = {
+ .bind = sun8i_dw_hdmi_bind,
+ .unbind = sun8i_dw_hdmi_unbind,
+};
+
+static int sun8i_dw_hdmi_probe(struct platform_device *pdev)
+{
+ return component_add(&pdev->dev, &sun8i_dw_hdmi_ops);
+}
+
+static int sun8i_dw_hdmi_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &sun8i_dw_hdmi_ops);
+
+ return 0;
+}
+
+static const struct of_device_id sun8i_dw_hdmi_dt_ids[] = {
+ { .compatible = "allwinner,h3-dw-hdmi" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, sun8i_dw_hdmi_dt_ids);
+
+struct platform_driver sun8i_dw_hdmi_pltfm_driver = {
+ .probe = sun8i_dw_hdmi_probe,
+ .remove = sun8i_dw_hdmi_remove,
+ .driver = {
+ .name = "sun8i-dw-hdmi",
+ .of_match_table = sun8i_dw_hdmi_dt_ids,
+ },
+};
+module_platform_driver(sun8i_dw_hdmi_pltfm_driver);
+
+MODULE_AUTHOR("Jernej Skrabec <jernej....@siol.net>");
+MODULE_DESCRIPTION("Allwinner H3 DW HDMI bridge");
+MODULE_LICENSE("GPL");
--
2.13.0

[Icenowy Zheng]

Orange Pi PC board has a HDMI-A port connected to the HDMI controller of
Allwinner H3 SoC.

Enable the HDMI output in Orange Pi PC device tree.

Signed-off-by: Icenowy Zheng <ice...@aosc.io>
---

arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index 998b60f8d295..0e3326399590 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -98,6 +98,10 @@
status = "okay";
};

+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -121,12 +125,20 @@
status = "okay";
};

+&hdmi {
+ status = "okay";
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
status = "okay";
};

+&mixer0 {
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
@@ -177,6 +189,10 @@
status = "okay";
};

+&tcon0 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
--
2.13.0

[Chen-Yu Tsai]

On Tue, Aug 1, 2017 at 9:12 PM, Icenowy Zheng <ice...@aosc.io> wrote:
> Allwinner H3 features a "Display Engine 2.0", which needs some support
> to be present in the DRM driver.
>
> This patchset is now a basical version, which dropped some features I
> used to submitted:
> - TVE support (not so high priority now)
> - Multi-pipeline support (also not so high priority now due to no TVE)

Even though you dropped some patches, this is still v3.

What has changed since v2?

>
> The last 6 patches are only used for testing this patchset, and they're
> going to be sent by Jernej Skrabec after this patchset is applied.
>
> Icenowy Zheng (9):
> dt-bindings: update the binding for Allwinner H3 DE2 support
> drm: sun4i: add support for H3 mixers
> drm: sun4i: add support for H3's TCON
> drm: sun4i: add compatible for H3 display engine
> clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3
> clk: sunxi-ng: export CLK_PLL_DE for H3
> ARM: sun8i: h3: add display engine pipeline barebone
> [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable DesignWare HDMI controller
> [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable HDMI output on Orange Pi
> PC
>
> Jernej Skrabec (4):
> [NOT FOR REVIEW NOW] drm: bridge: Enable polling hpd event in dw_hdmi
> [NOT FOR REVIEW NOW] drm: bridge: Add a pre_init function for the
> dw_hdmi driver
> [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3
> HDMI clock

This one looks trivial enough that I can pick it up regardless of the tag.

ChenYu

> [NOT FOR REVIEW NOW] drm: sun4i: Add a glue for the DesignWare HDMI
> controller in H3
>
> .../bindings/display/sunxi/sun4i-drm.txt | 25 +-
> arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 16 +
> arch/arm/boot/dts/sun8i-h3.dtsi | 205 +++++++++
> drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 4 +-
> drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 3 +-
> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 9 +-
> drivers/gpu/drm/sun4i/Kconfig | 9 +
> drivers/gpu/drm/sun4i/Makefile | 1 +
> drivers/gpu/drm/sun4i/sun4i_drv.c | 2 +
> drivers/gpu/drm/sun4i/sun4i_tcon.c | 43 +-
> drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 +
> drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 462 +++++++++++++++++++++
> drivers/gpu/drm/sun4i/sun8i_mixer.c | 18 +
> include/drm/bridge/dw_hdmi.h | 2 +
> include/dt-bindings/clock/sun8i-h3-ccu.h | 2 +
> 15 files changed, 781 insertions(+), 21 deletions(-)
> create mode 100644 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
>
> --
> 2.13.0
>

> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi...@googlegroups.com.
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[Jernej Škrabec]

Hi Icenowy,

Dne torek, 01. avgust 2017 ob 15:12:58 CEST je Icenowy Zheng napisal(a):

I believe Maxime ask you to use clk_set_rate() in the past:
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-June/512909.html

Regards,
Jernej

[Jernej Škrabec]

Hi Icenowy,

Dne torek, 01. avgust 2017 ob 15:12:52 CEST je Icenowy Zheng napisal(a):

About that, I concur with Maxime here, plane number properties would be
better. If we don't do this now, we will never have it.

Reference:
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-June/512902.html

Regards,
Jernej

> - reg: base address and size of the memory-mapped region.
> - clocks: phandles to the clocks feeding the mixer
> * bus: the mixer interface clock
> @@ -218,7 +235,6 @@ Required properties:
> Documentation/devicetree/bindings/media/video-interfaces.txt. The
> first port should be the input endpoints, the second one the output
>
> -
> Display Engine Pipeline
> -----------------------
>
> @@ -233,6 +249,7 @@ Required properties:
> * allwinner,sun6i-a31-display-engine
> * allwinner,sun6i-a31s-display-engine
> * allwinner,sun8i-a33-display-engine
> + * allwinner,sun8i-h3-display-engine
> * allwinner,sun8i-v3s-display-engine
>
> - allwinner,pipelines: list of phandle to the display engine
> --
> 2.13.0
>

[ice...@aosc.io]

But I still prefer different compatibles, as the capabilities are
already
proven to be different between mixer0 and mixer1, and furtherly we
cannot
promise Allwinner won't add more functions only available at mixer0.

Then we will be trapped into a situation that we describe more and more
functions via properties, but they should be encoded into the
compatible.

[ice...@aosc.io]

Yes, but I think the frequency is still part of our configuration, not
forced
by the hardware.

If we set it in the driver, why don't we set it to 300MHz?

(In fact for pipelines without TVE we can really use 300MHz for CLK_DE,
and if
we do not want 4K we can even use lower frequency)

>
> Regards,
> Jernej

[Jernej Škrabec]

Hi,

Dne sreda, 02. avgust 2017 ob 07:02:39 CEST je ice...@aosc.io napisal(a):

It is either multiple compatibles or multiple properties. I prefer the later,
but it is up to maintainers to decide.

Anyway, I think DE2 will not evolve much since DE3 is almost ready (H6). At
least basics seems to be similar according to a BSP code drop.

Regards,
Jernej

>
> > Reference:
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2017-June/512902.htm
> > l
> >
> > Regards,
> > Jernej

[Icenowy Zheng]

于 2017年8月3日 GMT+08:00 上午3:06:26, "Jernej Škrabec" <jernej....@siol.net> 写到:

According to what I heard from TL Lim, DE3 is just an evolution
to DE2.

[Chen-Yu Tsai]

On Tue, Aug 1, 2017 at 9:12 PM, Icenowy Zheng <ice...@aosc.io> wrote:

> From: Icenowy Zheng <ice...@aosc.xyz>
>
> Allwinner H3 has two special TCONs without channel 0.
>
> Add support for this kind of TCON.
>
> Signed-off-by: Icenowy Zheng <ice...@aosc.io>

Ideally you would split this into two patches. The first one would add
the quirks support for TCONs without channel 0. I can also use this for
the A80. The second would add the H3 TCON.

ChenYu

[Icenowy Zheng]

于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai <we...@csie.org> 写到:
>Hi,

>Line is longer than 80 characters.
>
>This looks independent enough so I've merged this for 4.14 with the
>offending line wrapped and the following tag added:
>
>Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")

Please don't merge this now until Jernej send it.

>
>ChenYu

>
>>
>> static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
>> 0x154, BIT(31), 0);
>> --
>> 2.13.0
>>

[Chen-Yu Tsai]

Hi,

On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng <ice...@aosc.io> wrote:

Line is longer than 80 characters.

This looks independent enough so I've merged this for 4.14 with the
offending line wrapped and the following tag added:

Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")

ChenYu

>
> static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
> 0x154, BIT(31), 0);
> --
> 2.13.0
>

[Chen-Yu Tsai]

(Dropped Rob, devicetree and dri mailing lists)

Hi Jernej,

Is it OK if we take this patch for the next release? Or rather,
if there anything blocking this patch?

Thanks
ChenYu

[Jernej Škrabec]

Hi Chen-Yu,

Dne petek, 04. avgust 2017 ob 06:29:50 CEST je Chen-Yu Tsai napisal(a):

I just made last check now and this patch is indeed OK. Before merging, please
read explanation below.

Background:
According to H3 datasheet and BSP driver, HDMI clock has M factor (divider) to
correctly set pixel clock to desired value. However, Jens Kuske discovered
that this factor doesn't play any role whatsoever and instead, division factor
set in PHY registers is the important one. I confirmed that on BSP kernel by
tying M factor to 0. Both, HDMI video and audio, still worked correctly.

So that flag is necessary to set pll-video to pixel clock * div factor. I can
also change HDMI clock type to SUNXI_CCU_GATE (without M factor) and document
discrepancy with datasheet in ccu-sun8i-h3.c. Alternatively to this patch,
just in case, to be on the safe side, I can add pll-video clock phandle to the
dt node. However, as far as I know, that might prevent selecting another
parent on SoCs where HDMI clock has multiple parents.

Regards,
Jernej

[Icenowy Zheng]

于 2017年8月4日 GMT+08:00 下午4:59:03, "Jernej Škrabec" <jernej....@siol.net> 写到:

Unfortunately A64 is this situation -- A64 TCON1/HDMI clocks can
use pll-video0/1 as parent, but TCON0 can only use pll-video0 or
pll-mipi (also a downstream clock of pll-video0), and by default
TCON1/HDMI also uses pll-video0.

Because of this I have never succeeded in multihead (LCD+HDMI)
on Pinebook.

[Chen-Yu Tsai]

Ack.

>
> Background:
> According to H3 datasheet and BSP driver, HDMI clock has M factor (divider) to
> correctly set pixel clock to desired value. However, Jens Kuske discovered
> that this factor doesn't play any role whatsoever and instead, division factor
> set in PHY registers is the important one. I confirmed that on BSP kernel by
> tying M factor to 0. Both, HDMI video and audio, still worked correctly.

Great. Sounds like what we have on A31 and earlier SoCs.

>
> So that flag is necessary to set pll-video to pixel clock * div factor. I can
> also change HDMI clock type to SUNXI_CCU_GATE (without M factor) and document
> discrepancy with datasheet in ccu-sun8i-h3.c. Alternatively to this patch,
> just in case, to be on the safe side, I can add pll-video clock phandle to the
> dt node. However, as far as I know, that might prevent selecting another
> parent on SoCs where HDMI clock has multiple parents.

It could be that the HDMI clock only drives the DW-HDMI sampler and other
internal logic, while the PHY takes the PLL input directly for the TMDS
clock? I'm not sure how you could verify this though. Maybe increase M
to the maximum, and see if there is any tearing or other artifacts?
Ideally we could just ask Allwinner...

You should change it to SUNXI_CCU_MUX_WITH_GATE if you want to change it.
If there are mux bits, even if there's only one valid setting, you should
still have the mux, so the kernel can actually correct any invalid settings
that may be incorrectly programmed into the hardware by the bootloader or
user. This would be a separate patch.

How we support other SoCs really depends on whether the TMDS clock bits
have a mux or not, or whether they are connected to the HDMI mod clock
in any way.

Regards
ChenYu

[Chen-Yu Tsai]

Multihead support hasn't been tested, despite all the patches I've
done to try and support it. I had to do some more to get HDMI and
LCD working together on the A31. And even then there are still
issues.

The current (as of Maxime's sunxi-drm/for-next branch) issues are

- Two outputs with incompatible dot clocks will step on each
other, instead of switching to another PLL. Maxime seems to
have some patches to prevent this.

- Engine and TCON pairing in a fully connected display system
is (still) broken. You will end up tying both TCON with the
same engine. I have patches to fix this in my a31-hdmi-v2
branch.

You can work around both issues, the first one by adding
CLK_SET_RATE_NO_REPARENT to the TCON clocks, and forcing the
TCON parents at ccu probe time. The second one can be worked
around by removing the extra unused connections between mixer0
and TCON1, and vice versa.

This should at least allow you to test your hardware.

Regards
ChenYu

[Jernej Škrabec]

Hi Chen-Yu,

Dne petek, 04. avgust 2017 ob 11:27:33 CEST je Chen-Yu Tsai napisal(a):

I just made quick test with maximum divider and everything seems to be ok.
Unfortunately, I don't have time to do extensive test.

I will forward the question to Tl Lim and let's see if he can get the answer,
since the situation for A64 is completely the same.

>
> You should change it to SUNXI_CCU_MUX_WITH_GATE if you want to change it.
> If there are mux bits, even if there's only one valid setting, you should
> still have the mux, so the kernel can actually correct any invalid settings
> that may be incorrectly programmed into the hardware by the bootloader or
> user. This would be a separate patch.

I will leave it as it is for now. Will you still merge the patch?

Regards,
Jernej

>
> How we support other SoCs really depends on whether the TMDS clock bits
> have a mux or not, or whether they are connected to the HDMI mod clock
> in any way.
>
> Regards
> ChenYu
>
> > Regards,
> > Jernej
> >
> >> Thanks
> >> ChenYu
> >>
> >> >>ChenYu
> >> >>
> >> >>> static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
> >> >>>
> >> >>> 0x154, BIT(31), 0);
>

[Chen-Yu Tsai]

That would be much appreciated.

>>
>> You should change it to SUNXI_CCU_MUX_WITH_GATE if you want to change it.
>> If there are mux bits, even if there's only one valid setting, you should
>> still have the mux, so the kernel can actually correct any invalid settings
>> that may be incorrectly programmed into the hardware by the bootloader or
>> user. This would be a separate patch.
>
> I will leave it as it is for now. Will you still merge the patch?

I'll drop it for now. Although we have this how A10s and A31, the hardware
is not wired to actually use, as I mentioned above. We can do something
about it once we have a better understanding of the hardware.

Thanks for all the explanation and testing.

Regards
ChenYu

[Rob Herring]

On Tue, Aug 01, 2017 at 09:12:52PM +0800, Icenowy Zheng wrote:
> Allwinner H3 features a "Display Engine 2.0".
>
> Add device tree bindings for the following parts:
> - H3 TCONs
> - H3 Mixers
> - H3 Display engine
>

> Signed-off-by: Icenowy Zheng <ice...@aosc.io>
> ---

> .../bindings/display/sunxi/sun4i-drm.txt | 25 ++++++++++++++++++----
> 1 file changed, 21 insertions(+), 4 deletions(-)

Acked-by: Rob Herring <ro...@kernel.org>

[Rob Herring]

It's not the same. A compatible can imply an infinite number of
properties. I'm fine with properties too, but with only 2 instances I
don't think it makes much sense.

Rob

[Jernej Škrabec]

Hi,

Dne četrtek, 10. avgust 2017 ob 02:21:21 CEST je Rob Herring napisal(a):

Actually, there are more combinations since different SoCs have also different
capabilities regarding mixer0 or mixer1.

For example, mixer0 on H3 has different capabilities than mixer0 on A83T (max.
plane size and number and type of planes, etc.).

Best regards,
Jernej

[Maxime Ripard]

You should ask yourself another question. Do you absolutely need that
rate and parent to operate properly?

If the answer is yes, the DT is not what you're looking for, it
provides no guarantee on the changes to the clock rate and parenthood,
and doesn't allow you to act upon those changes either.

If you want to make it work, you need to have some code to do that.

Maxime

--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com