Oleg Verych
unread,Jan 16, 2023, 6:26:35 PM1/16/23Sign in to reply to author
Sign in to forward
You do not have permission to delete messages in this group
Sign in to report message
Either email addresses are anonymous for this group or you need the view member email addresses permission to view the original message
to open list:ARM/Allwinner sunXi SoC support, Oleg Verych, Emilio López, Maxime Ripard, Chen-Yu Tsai, Jernej Skrabec, linux-sunxi
Update wiki page link to the Allwinner sunXi SoC Clock Control Module.
Signed-off-by: Oleg Verych <
ole...@gmail.com>
---
Hi!
Can I ask additional question to those in the file?
How is it possible to setup PLL7 to particular frequency and select
it as a source to CSI0 via CCM_CSI0_CLK[1]?
Is it possible to put such device tree example in documentation?
Thanks!
[1]
https://linux-sunxi.org/Clock_Control_Module#CCM_CSI0_CLK
Documentation/arm/sunxi/clocks.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/arm/sunxi/clocks.rst b/Documentation/arm/sunxi/clocks.rst
index 23bd03f3e..f435bdd70 100644
--- a/Documentation/arm/sunxi/clocks.rst
+++ b/Documentation/arm/sunxi/clocks.rst
@@ -49,7 +49,7 @@ Q: Were can I learn more about the sunxi clocks?
A: The linux-sunxi wiki contains a page documenting the clock registers,
you can find it at
-
http://linux-sunxi.org/A10/CCM
+
https://linux-sunxi.org/Clock_Control_Module
The authoritative source for information at this time is the ccmu driver
released by Allwinner, you can find it at
--
2.20.1