[PATCH] media: sun6i-csi: Fix incorrect HSYNC/VSYNC/PCLK polarity configuration

[Ondrej Jirman]

This was discovered by writing a new camera driver and wondering, why
hsync/vsync polarity setting behaves in reverse to what would be
expected. Verified by looking at the actual signals and the SoC
user manual.

Fixes: 5cc7522d8965 ("media: sun6i: Add support for Allwinner CSI V3s")
Signed-off-by: Ondrej Jirman <meg...@megous.com>
---
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index f17e5550602d..98bbcca59a90 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
@@ -417,12 +417,12 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
if (flags & V4L2_MBUS_FIELD_EVEN_LOW)
cfg |= CSI_IF_CFG_FIELD_POSITIVE;

- if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
+ if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
cfg |= CSI_IF_CFG_VREF_POL_POSITIVE;
- if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
+ if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
cfg |= CSI_IF_CFG_HREF_POL_POSITIVE;

- if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
+ if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
cfg |= CSI_IF_CFG_CLK_POL_FALLING_EDGE;
break;
case V4L2_MBUS_BT656:
--
2.24.0

[Yong]

Hi Ondrej,

This has been discussed.
And Maxime sent a patch for this:
https://www.mail-archive.com/linux...@vger.kernel.org/msg127149.html

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Thanks,
Yong

[Ondřej Jirman]

Hi,

On Thu, Nov 28, 2019 at 10:26:08AM +0800, Yong wrote:
> Hi Ondrej,
>
> This has been discussed.
> And Maxime sent a patch for this:
> https://www.mail-archive.com/linux...@vger.kernel.org/msg127149.html

Thanks for pointing to the previous patch. But that patch doesn't make any
sense, and breaks things for me, and doesn't even match BSP code, which
has no such reversal, and works fine with about 30 cam drivers.

Also how do you explain my findings?

My camera is sending correct signals, verified by looking at them actually (see
below), and CSI is not receiving the image. I have to flip HSYNC/VSYNC to be
oposite of that what CSI driver expects and I get a noisy image and if I fix
PCLK polarity too, the noise goes away, which means now I'm also sampling when
the data are stable and not when they're changing.

Here: (output from my cam, that I configured to have VSYNC ACTIVE LOW, HSYNC
ACTIVE LOW) And the signal is clearly that, as you can see yourself:

https://megous.com/dl/tmp/98df81b7ed0126ec.png

The above signals are received with CSI driver configured with
V4L2_MBUS_VSYNC_ACTIVE_HIGH V4L2_MBUS_HSYNC_ACTIVE_HIGH. So CSI driver is
clearly wrong.

I think this is pretty clear the driver is buggy. At least for A83T SoC.

I'm not sure what Maxime found out, but he should probably re-check his
findings. Maxime, can you comment on this?

regards,
o.

[Chen-Yu Tsai]

On Thu, Nov 28, 2019 at 11:06 AM Ondřej Jirman <meg...@megous.com> wrote:
>
> Hi,
>
> On Thu, Nov 28, 2019 at 10:26:08AM +0800, Yong wrote:
> > Hi Ondrej,
> >
> > This has been discussed.
> > And Maxime sent a patch for this:
> > https://www.mail-archive.com/linux...@vger.kernel.org/msg127149.html
>
> Thanks for pointing to the previous patch. But that patch doesn't make any
> sense, and breaks things for me, and doesn't even match BSP code, which
> has no such reversal, and works fine with about 30 cam drivers.
>
> Also how do you explain my findings?
>
> My camera is sending correct signals, verified by looking at them actually (see
> below), and CSI is not receiving the image. I have to flip HSYNC/VSYNC to be
> oposite of that what CSI driver expects and I get a noisy image and if I fix
> PCLK polarity too, the noise goes away, which means now I'm also sampling when
> the data are stable and not when they're changing.
>
> Here: (output from my cam, that I configured to have VSYNC ACTIVE LOW, HSYNC
> ACTIVE LOW) And the signal is clearly that, as you can see yourself:
>
> https://megous.com/dl/tmp/98df81b7ed0126ec.png

From the looks of things you have active-high VSYNC with active-low HREF.
HREF is not the same as HSYNC, in fact quite the opposite. V/H SYNC are
pulses, active only when there should be no data and the line/frame switch
happens, while V/H REF are held active when there is data. I personally
find these terms very confusing. :(

Now the timing diagrams in the Allwinner manuals would suggest that when
they are talking about H/V SYNC, they are actually referring to H/V REF.
The HSYNC line is high/active when there is valid data, and the VSYNC line
is high/active for the duration of the frame.

I think both sides need to be checked that they are using the correct
polarity, and maybe also have the media maintainers clarify how the
polarity should be interpreted when the hardware uses H/V ref instead
of H/V sync.


ChenYu

> To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20191128030653.5fhcolvib6tzf4zc%40core.my.home.

[Ondřej Jirman]

Oh my, so it's just a terminology issue? :)

This probably should be docummented somewhere. I just thought xSYNC_ACTIVE_HIGH
meant the respective signals are supposed to be HIGH during active phase of data
transmission: that is VSYNC HIGH during entire frame, and HSYNC high during row.

DT bindings documentation doesn't help much either.

And obviously manufacturers are confused too.

https://megous.com/dl/tmp/fae07dfb4897bbb3.png

HSYNC/VSYNC "low valid" produces what you see on the previous signal capture
I posted. ;)

regards,
o.

[Chen-Yu Tsai]

Unfortunately I'm having a hard time finding a definitive source for this. My
rationale is that since the sync signal is a pulse, the active part would refer
to the pulsing part, not the at rest part.

> DT bindings documentation doesn't help much either.

Yeah. I think this should be sorted out for the whole subsystem, as this not
only affects platform drivers, but the sensor drivers as well.

> And obviously manufacturers are confused too.
>
> https://megous.com/dl/tmp/fae07dfb4897bbb3.png

It seems at least OmniVision uses VSYNC + HREF. GalaxyCore seems to use VSYNC +
HREF as well, but they call it HSYNC, and VSYNC polarity is inverted. :(

The OV7670 sensor I was testing had an option to switch from HREF to HSYNC,
and another one to invert HREF. Talk about confusing. And HSYNC != inverted
HREF. They will be some PCLK cycles apart.

> HSYNC/VSYNC "low valid" produces what you see on the previous signal capture
> I posted. ;)

Thanks. I don't have a scope or logic analyzer. I'll wait for the people who
do to figure this out.


Regards
ChenYu

> To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20191128035056.77554jav3eo6h7su%40core.my.home.