[PATCH] sunxi: spl: Fix H616 clock initialization

[Jernej Skrabec]

It turns out that there is a magic bit in PRCM region which seemingly
makes PLLs work if it's enabled. Sadly, there is no documentation what
it does exactly, so we'll just mimick BSP boot0 behaviour and enable it
before any clock is set up.

Fixes: b18bd53d6cde ("sunxi: introduce support for H616 clocks")
Signed-off-by: Jernej Skrabec <jernej....@siol.net>
---
arch/arm/mach-sunxi/clock_sun50i_h6.c | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index 06d84eb158d7..68c8e7f2afbe 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -9,6 +9,12 @@ void clock_init_safe(void)
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+#ifdef CONFIG_MACH_SUN50I_H616
+ /* this seems to enable PLLs */
+ setbits_le32(SUNXI_PRCM_BASE + 0x250, 0x10);
+#endif
+
clock_set_pll1(408000000);

writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg);
--
2.30.0

[Andre Przywara]

On Sun, 31 Jan 2021 21:25:39 +0100
Jernej Skrabec <jernej....@siol.net> wrote:

Hi Jernej,

> It turns out that there is a magic bit in PRCM region which seemingly
> makes PLLs work if it's enabled. Sadly, there is no documentation what
> it does exactly, so we'll just mimick BSP boot0 behaviour and enable it
> before any clock is set up.

Good job of figuring this out!

> Fixes: b18bd53d6cde ("sunxi: introduce support for H616 clocks")
> Signed-off-by: Jernej Skrabec <jernej....@siol.net>
> ---
> arch/arm/mach-sunxi/clock_sun50i_h6.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
> index 06d84eb158d7..68c8e7f2afbe 100644
> --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
> +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
> @@ -9,6 +9,12 @@ void clock_init_safe(void)
> {
> struct sunxi_ccm_reg *const ccm =
> (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> +
> +#ifdef CONFIG_MACH_SUN50I_H616

Can you change this to: if (IS_ENABLED())?

> + /* this seems to enable PLLs */

Out of curiosity, what makes you think it's PLL related? At least the
PERIPH0 and CPU PLLs seem to work without it?

Cheers,
Andre

[Jernej Škrabec]

Dne ponedeljek, 01. februar 2021 ob 01:46:22 CET je Andre Przywara napisal(a):

> On Sun, 31 Jan 2021 21:25:39 +0100
> Jernej Skrabec <jernej....@siol.net> wrote:
>
> Hi Jernej,
>
> > It turns out that there is a magic bit in PRCM region which seemingly
> > makes PLLs work if it's enabled. Sadly, there is no documentation what
> > it does exactly, so we'll just mimick BSP boot0 behaviour and enable it
> > before any clock is set up.
>
> Good job of figuring this out!
>
> > Fixes: b18bd53d6cde ("sunxi: introduce support for H616 clocks")
> > Signed-off-by: Jernej Skrabec <jernej....@siol.net>
> > ---
> >
> > arch/arm/mach-sunxi/clock_sun50i_h6.c | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c
> > b/arch/arm/mach-sunxi/clock_sun50i_h6.c index 06d84eb158d7..68c8e7f2afbe
> > 100644
> > --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
> > +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
> > @@ -9,6 +9,12 @@ void clock_init_safe(void)
> >
> > {
> >
> > struct sunxi_ccm_reg *const ccm =
> >
> > (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> >
> > +
> > +#ifdef CONFIG_MACH_SUN50I_H616
>
> Can you change this to: if (IS_ENABLED())?

ok.

>
> > + /* this seems to enable PLLs */
>
> Out of curiosity, what makes you think it's PLL related? At least the
> PERIPH0 and CPU PLLs seem to work without it?

Because I was able to configure TCON TOP -> TCON TV0 -> HDMI chain just fine,
but nothing would be shown on screen, not even test patterns from TCON. HDMI
itself worked ok (EDID could be read). I noticed that vblank interrupts were
not genereted. This and no image is consisted with disabling bus clock to TCON
and HDMI. I checked several times that clock configuration matches to that in
BSP... I also moved both to another PLL without success. Also, this bit was
discovered in function, which does clock initialization.

PLL cpu is always special case, otherwise nothing would work at boot. I have
no real explanation for PLL periph...

Best regards,
Jernej

[Jernej Skrabec]

It turns out that there is a magic bit in PRCM region which seemingly
makes PLLs work if it's enabled. Sadly, there is no documentation what
it does exactly, so we'll just mimick BSP boot0 behaviour and enable it
before any clock is set up.

Fixes: b18bd53d6cde ("sunxi: introduce support for H616 clocks")
Signed-off-by: Jernej Skrabec <jernej....@siol.net>
---

Changes from v1:
- use if (IS_ENABLED()) instead of #ifdef #endif

arch/arm/mach-sunxi/clock_sun50i_h6.c | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index 06d84eb158d7..492fc4a3fca8 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -9,6 +9,11 @@ void clock_init_safe(void)

{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+

+ /* this seems to enable PLLs on H616 */
+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))

+ setbits_le32(SUNXI_PRCM_BASE + 0x250, 0x10);

+
clock_set_pll1(408000000);

writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg);

--
2.30.0