[PATCH 00/10] arm64: dts: allwinner: h5: Enable CPU DVFS (cpufreq)

[Chen-Yu Tsai]

Hi everyone,

This series enables DVFS for the CPU cores (aka cpufreq) on the
Allwinner H5 SoC. The OPP table was taken from Armbian, with minor
tweaks to the maximum voltage to account for slightly increased voltage
on some of the boards.

This has been tested on the Bananapi M2+ v1.2 and Libre Computer
ALL-H3-CC H5 ver.. I do not have the remaining boards so I've CC-ed
people who did the original submission or have modified the board
specifically later on.

Patch 1 fixes the voltages specified for the GPIO-controlled regulator
on the Bananapi M2+ v1.2. The voltages are slightly higher than what
was originally written.

Patch 2 adds a fixed regulator for the CPU on the original Bananapi M2+.
This is for the retail version, not the engineering samples that had an
even higher voltage setting.

Patch 3 hooks up the CPU regulator supply for H5 boards that already
define the regulator, but were missing the property to tie it to the
CPUs.

Patch 4 ~ 8 adds the CPU regulator for boards that don't have it
defined. This is based on each vendor's schematics. I need people
to test each of these specifically and the whole series.

Patch 9 ties the CPU clock to the CPU cores.

Patch 10 adds the OPP table, based on the one from Armbian.

Please have a look and please help test this.


Regards
ChenYu


Chen-Yu Tsai (10):
ARM: dts: sunxi: bananapi-m2-plus-v1.2: Fix CPU supply voltages
ARM: dts: bananapi-m2-plus: Add CPU supply regulator
arm64: dts: allwinner: h5: Hook up cpu regulator supplies
arm64: dts: allwinner: h5: nanopi-neo2: Add CPU regulator supply
arm64: dts: allwinner: h5: orange-pi-zero-plus: Add CPU regulator
supply
arm64: dts: allwinner: h5: orange-pi-zero-plus2: Add CPU regulator
supply
arm64: dts: allwinner: h5: orange-pi-pc2: Add CPU regulator supply
arm64: dts: allwinner: h5: orange-pi-prime: Add CPU regulator supply
arm64: dts: allwinner: h5: Add clock to CPU cores
arm64: dts: allwinner: h5: Add CPU Operating Performance Points table

.../boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi | 30 +++-----
arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi | 14 ++++
.../sun50i-h5-emlid-neutis-n5-devboard.dts | 4 +
.../allwinner/sun50i-h5-nanopi-neo-plus2.dts | 4 +
.../dts/allwinner/sun50i-h5-nanopi-neo2.dts | 20 +++++
.../dts/allwinner/sun50i-h5-orangepi-pc2.dts | 28 +++++++
.../allwinner/sun50i-h5-orangepi-prime.dts | 28 +++++++
.../sun50i-h5-orangepi-zero-plus.dts | 20 +++++
.../sun50i-h5-orangepi-zero-plus2.dts | 20 +++++
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 75 +++++++++++++++++++
10 files changed, 224 insertions(+), 19 deletions(-)

--
2.20.1

[Chen-Yu Tsai]

Add an OPP (Operating Performance Points) table for the CPU cores to
enable DVFS (Dynamic Voltage & Frequency Scaling) on the H5. The table
originates from Armbian, but the maximum voltage is raised slightly to
account for boards using slightly higher voltages.

This has been tested on the Libre Computer ALL-H3-CC-H5 and the Bananapi
M2+ v1.2 H5, both with adequate cooling. The former has a fixed 1.2V
regulator, while the latter has a GPIO controlled regulator switchable
between 1.1V and 1.3V.

Signed-off-by: Chen-Yu Tsai <we...@csie.org>
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 67 ++++++++++++++++++++
1 file changed, 67 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index 25bb8227a6fd..0e83b8a25f9c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -54,6 +54,8 @@
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
};

cpu@1 {
@@ -63,6 +65,8 @@
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
};

cpu@2 {
@@ -72,6 +76,8 @@
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
};

cpu@3 {
@@ -81,6 +87,67 @@
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ cpu_opp_table: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <1000000 1000000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@648000000 {
+ opp-hz = /bits/ 64 <648000000>;
+ opp-microvolt = <1040000 1040000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1080000 1080000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@912000000 {
+ opp-hz = /bits/ 64 <912000000>;
+ opp-microvolt = <1120000 1120000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@960000000 {
+ opp-hz = /bits/ 64 <960000000>;
+ opp-microvolt = <1160000 1160000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1200000 1200000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <1240000 1240000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1104000000 {
+ opp-hz = /bits/ 64 <1104000000>;
+ opp-microvolt = <1260000 1260000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1152000000 {
+ opp-hz = /bits/ 64 <1152000000>;
+ opp-microvolt = <1300000 1300000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
};
};

--
2.20.1

[Chen-Yu Tsai]

The OrangePi PC 2 uses a Silergy SY8106A regulator to supply the CPU
cores. The fixed voltage when I2C programmed regulation is not in action
is slightly higher than 1.1V. The value in the device tree description
is based on calculations of the resistor values from the schematics.

Cc: Andre Przywara <andre.p...@arm.com>
Cc: Icenowy Zheng <ice...@aosc.io>
Cc: Emmanuel Vadot <ma...@freebsd.org>

Signed-off-by: Chen-Yu Tsai <we...@csie.org>

---

This patch is based on the schematics and has not been tested on an
actual board.
---
.../dts/allwinner/sun50i-h5-orangepi-pc2.dts | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
index 3e0d5a9c096d..23cfad7c78f4 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
@@ -132,6 +132,10 @@
status = "okay";
};

+&cpu0 {
+ cpu-supply = <&reg_vdd_cpux>;
+};
+
&de {
status = "okay";
};
@@ -207,6 +211,30 @@
status = "okay";
};

+&r_i2c {
+ status = "okay";
+
+ reg_vdd_cpux: regulator@65 {
+ compatible = "silergy,sy8106a";
+ reg = <0x65>;
+ regulator-name = "vdd-cpux";
+ silergy,fixed-microvolt = <1108474>;
+ /*
+ * The datasheet uses 1.1V as the minimum value of VDD-CPUX,
+ * however both the Armbian DVFS table and the official one
+ * have operating points with voltage under 1.1V, and both
+ * DVFS table are known to work properly at the lowest
+ * operating point.
+ *
+ * Use 1.0V as the minimum voltage instead.
+ */
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
&spi0 {
status = "okay";

--
2.20.1

[Chen-Yu Tsai]

The OrangePi Prime uses a Silergy SY8106A regulator to supply the CPU

cores. The fixed voltage when I2C programmed regulation is not in action
is slightly higher than 1.1V. The value in the device tree description
is based on calculations of the resistor values from the schematics.

Cc: Icenowy Zheng <ice...@aosc.io>

Signed-off-by: Chen-Yu Tsai <we...@csie.org>

---

This patch is based on the schematics and has not been tested on an
actual board.
---

.../allwinner/sun50i-h5-orangepi-prime.dts | 28 +++++++++++++++++++

1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
index b75ca4d7d001..e866a0734bb3 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
@@ -139,6 +139,10 @@

status = "okay";
};

+&cpu0 {
+ cpu-supply = <&reg_vdd_cpux>;
+};
+
&de {
status = "okay";
};

@@ -222,6 +226,30 @@

&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
--
2.20.1

[Chen-Yu Tsai]

The ARM CPU cores are fed by the CPU clock from the CCU. Add a
reference to the clock for each CPU core, along with the clock
transition latency.

Signed-off-by: Chen-Yu Tsai <we...@csie.org>
---

arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index c22621b4b8e9..25bb8227a6fd 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -52,6 +52,8 @@
device_type = "cpu";
reg = <0>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;

+ clock-latency-ns = <244144>; /* 8 32k periods */

};

cpu@1 {
@@ -59,6 +61,8 @@
device_type = "cpu";
reg = <1>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;

+ clock-latency-ns = <244144>; /* 8 32k periods */

};

cpu@2 {
@@ -66,6 +70,8 @@
device_type = "cpu";
reg = <2>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;

+ clock-latency-ns = <244144>; /* 8 32k periods */

};

cpu@3 {
@@ -73,6 +79,8 @@
device_type = "cpu";
reg = <3>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;

[Maxime Ripard]

What is the frequency and voltage that U-Boot sets up?

We've had the issue with the A33 that it's started at 1008MHz, with
the matching voltage, and ramping up the frequency to 1.2GHz on boards
without PMIC support would increase the frequency but not the voltage,
resulting in a brownout.

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

[Chen-Yu Tsai]

1008 MHz, and whatever voltage the board design defaults to (typically
the higher setting).

> We've had the issue with the A33 that it's started at 1008MHz, with
> the matching voltage, and ramping up the frequency to 1.2GHz on boards
> without PMIC support would increase the frequency but not the voltage,
> resulting in a brownout.

Which is why I added the regulator to all boards before this patch. At
least for Linux, once the regulator supply is described in the device
tree, if the driver is missing, regulator_get_* and thus cpufreq should
fail with -EPROBE_DEFER.

Or we could drop the extra OPPs.


ChenYu

[Maxime Ripard]

Ok, if you covered all of them then fine by me. For the whole series,
Acked-by: Maxime Ripard <maxime...@bootlin.com>

[Chen-Yu Tsai]

FYI I got this wrong. U-boot's default is 816 MHz. However it seems even
this is misleading, as cpufreq in Linux reports:

cpufreq: cpufreq_online: CPU0: Running at unlisted freq: 792000 KHz
cpufreq: cpufreq_online: CPU0: Unlisted initial frequency changed
to: 816000 KHz

So there seems tp be an off-by-1 error in some multiplier calculation.

>
> > We've had the issue with the A33 that it's started at 1008MHz, with
> > the matching voltage, and ramping up the frequency to 1.2GHz on boards
> > without PMIC support would increase the frequency but not the voltage,
> > resulting in a brownout.
>
> Which is why I added the regulator to all boards before this patch. At
> least for Linux, once the regulator supply is described in the device
> tree, if the driver is missing, regulator_get_* and thus cpufreq should
> fail with -EPROBE_DEFER.

I believe despite the above, this still stands. So we should be OK.

[Ondřej Jirman]

Hi,

Looks like this patch series got forgotten. Or is it waiting for some
user testing?

regards,
o.

> _______________________________________________
> linux-arm-kernel mailing list
> linux-ar...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[Georgii Staroselskii]

Hello, guys!

I wanted to bump this old thread and ask about its fate.
I can confirm that this patchset works on Neutis N5.

I do however see

> cpufreq: cpufreq_online: CPU0: Running at unlisted freq: 792000 KHz
> cpufreq: cpufreq_online: CPU0: Unlisted initial frequency changed

as mentioned above.

What should be done in order to see these patched applied?

P.S. I also tested https://github.com/megous/linux/tree/ths-5.2 alongside this
patchset and haven't found any issues that stand out.