DDR3 Layout Constraints for Allwinner R16

[Craig Swanson]

I am creating the schematics that are similar to the BPi-M2M board.

1) Bypass Caps - I see values in the schematic that are 22uF, 4.7uF, 1.0uF, and then 104.  What value is 104????

2) I am using an average dielectric like FR-4.  Routing topology for DDR3 has critical length matching for Point-to-Point:

      a) I am surprised there there are no termination resistors - is that taken care of by ODT?

      b) I am assuming 40ohms for DDR3 Single Ended and 80 ohms for the Differential clocks?

      c) Delay match are DQ/DM to DQS_P/N in data group, and Address/Control to CK_P/N?

      d) Could you provide the pin delays for the R16? (wire delays inside chip from bare die to package pins)

Regards,

Craig