andrew g <goha...@yahoo.com>: Apr 24 10:45PM -0700
hi Andre Przywara,
Thanks for your response.
According to this thread, the author who has worked on the H616 and H618
dram codes including that '1.5G issue'
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andrew g <goha...@yahoo.com>: Apr 24 10:49PM -0700
oops the 1st link should be
https://forum.armbian.com/topic/29202-orange-pi-zero-3/page/20/#comment-188030
with the spoiler in it
the comment ref should be 188030 rather than 188328
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andrew g <goha...@yahoo.com>: Apr 24 11:07PM -0700
on a 'longer term', if after all this *hack* (hard coding memory size)
works, I'd guess a possible way is to read custom memory size from an
'environment variable' say set by scripts in
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andrew g <goha...@yahoo.com>: Apr 24 11:19PM -0700
the statment
>> if it is run with the mainline u-boot without this hack and the
'standard' boards e.g. 2G, 4G, it boots just fine. But that with the hack
and on 1.5G Orange Pi Zero 3 board (I've
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andrew g <goha...@yahoo.com>: Apr 25 12:35AM -0700
I just did that test, I removed that 1.5GB hardcoding from mainline u-boot
build as of current
memsz = 2048UL * 1024UL * 1024UL * 3 / 4;
patched the hacked u-boot into my Armbian (Debian
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andrew g <goha...@yahoo.com>: Apr 25 01:56AM -0700
Applied 2 cortex_a53 erratum for BL31 stage in arm trusted firmware
INFO: BL31: cortex_a53: CPU workaround for erratum 855873 was applied
INFO: BL31: cortex_a53: CPU workaround for erratum
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andrew g <goha...@yahoo.com>: Apr 25 02:23AM -0700
just in case anyone has a board and wants to try it out, the image for
Orange Pi Zero 3 I'm messing with is this, note *unofficial*
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andrew g <goha...@yahoo.com>: Apr 25 02:26AM -0700
just in case anyone has a board and wants to try it out, the image for
Orange Pi Zero 3 I'm messing with is this, note *unofficial*, and this link
won't be there on a permanent basis
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