[PATCH] clk: sunxi-ng: h6: Fix CEC clock

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Andre Przywara

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Jan 6, 2021, 9:33:16 AM1/6/21
to Michael Turquette, Stephen Boyd, Maxime Ripard, Chen-Yu Tsai, Jernej Skrabec, Icenowy Zheng, linu...@vger.kernel.org, linux-ar...@lists.infradead.org, linux...@googlegroups.com
The CEC clock on the H6 SoC is a bit special, since it uses a fixed
pre-dividier for one source clock (the PLL), but conveys the other clock
(32K OSC) directly.
We are using a fixed predivider array for that, but fail to use the right
flag to actually activate that.

Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Reported-by: Jernej Skrabec <jernej....@siol.net>
Signed-off-by: Andre Przywara <andre.p...@arm.com>
---
drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
index f2497d0a4683..a26dbbdff80d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -682,7 +682,7 @@ static struct ccu_mux hdmi_cec_clk = {

.common = {
.reg = 0xb10,
- .features = CCU_FEATURE_VARIABLE_PREDIV,
+ .features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("hdmi-cec",
hdmi_cec_parents,
&ccu_mux_ops,
--
2.17.5

Chen-Yu Tsai

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Jan 6, 2021, 11:06:26 AM1/6/21
to André Przywara, Michael Turquette, Stephen Boyd, Maxime Ripard, Jernej Skrabec, Icenowy Zheng, linux-clk, linux-arm-kernel, linux-sunxi
On Wed, Jan 6, 2021 at 10:33 PM Andre Przywara <andre.p...@arm.com> wrote:
>
> The CEC clock on the H6 SoC is a bit special, since it uses a fixed
> pre-dividier for one source clock (the PLL), but conveys the other clock
> (32K OSC) directly.
> We are using a fixed predivider array for that, but fail to use the right
> flag to actually activate that.
>
> Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
> Reported-by: Jernej Skrabec <jernej....@siol.net>
> Signed-off-by: Andre Przywara <andre.p...@arm.com>

Acked-by: Chen-Yu Tsai <we...@csie.org>

Maxime Ripard

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Jan 6, 2021, 11:51:44 AM1/6/21
to Andre Przywara, Michael Turquette, Stephen Boyd, Chen-Yu Tsai, Jernej Skrabec, Icenowy Zheng, linu...@vger.kernel.org, linux-ar...@lists.infradead.org, linux...@googlegroups.com
On Wed, Jan 06, 2021 at 02:32:46PM +0000, Andre Przywara wrote:
> The CEC clock on the H6 SoC is a bit special, since it uses a fixed
> pre-dividier for one source clock (the PLL), but conveys the other clock
> (32K OSC) directly.
> We are using a fixed predivider array for that, but fail to use the right
> flag to actually activate that.
>
> Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
> Reported-by: Jernej Skrabec <jernej....@siol.net>
> Signed-off-by: Andre Przywara <andre.p...@arm.com>

Applied, thanks!
Maxime
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