[PATCH v4 01/19] sunxi: README.sunxi64: Add hint about non-debug of ARM Trusted Firmware

[Andre Przywara]

As we are running into issues where the final U-Boot FIT image file is
exceeding our size limit, add a hint to the README.sunxi64 file
to point out the possibility of building non-debug versions of the ATF
binary. These are about 12KB smaller than the standard debug build, and
so allow successful U-Boot builds for many boards with the Allwinner H5
SoC.
Please note that under normal circumstances the debug build is still
recommended, as it gives valuable clues in case something goes wrong in
the ATF.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
Acked-by: Maxime Ripard <maxime...@bootlin.com>
---
board/sunxi/README.sunxi64 | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/board/sunxi/README.sunxi64 b/board/sunxi/README.sunxi64
index 5a363d27b8..df1dbc818f 100644
--- a/board/sunxi/README.sunxi64
+++ b/board/sunxi/README.sunxi64
@@ -38,6 +38,12 @@ the root of your U-Boot build directory (or create a symbolic link).
$ export BL31=/src/arm-trusted-firmware/build/sun50iw1p1/debug/bl31.bin
(adjust the actual path accordingly)

+If you run into size issues with the resulting U-Boot image file, it might
+help to use a release build, by using "DEBUG=0" when building bl31.bin.
+As sometimes the ATF build process is a bit picky about the toolchain used,
+or if you can't be bothered with building ATF, there are known working
+binaries in the firmware repository[3], purely for convenience reasons.
+
SPL/U-Boot
------------
Both U-Boot proper and the SPL are using the 64-bit mode. As the boot ROM
--
2.14.1

[Andre Przywara]

A minor update to the v3 version sent earlier this month.
I reworked patch 09 to drop the direct MMC environment for 32-bit Allwinner
boards as well and keep the current MMC offset.
For now I also dropped the two patches changing (back) the MMC regulator.
I still believe they are good to have and keep them as U-Boot specific
.dtsi files in my tree, possibly posting them later again.

As the previous version, this combines the EMAC DT support update with
an update of the full Linux kernel DTs for all H3, H5 and A64 boards.

Patch 01 leaves some hint in the README how to avoid the situation
when overrunning U-Boot's image size on 64-bit boards.
The old v2 EMAC DT update series is in patches 02-08, it prepares U-Boot's
EMAC driver for using the new DT binding used in Linux, also updates
the DTs to the new EMAC DT node already.

Changes to sync the whole of U-Boot's DT files for the H3, H5 and A64 SoCs
to those from Linux are in the following patches. However this first requires
lifting the space limit we currently have due to the raw MMC environment.
Patch 09 disables that for all sunxi boards, to give us finally some
space. Patches 10 and 11 consequently revert the disabling of features we
saw a few weeks ago to migitate the size problem.

Patches 12-19 then bring in the Linux DTs, split by SoCs, with the .dtsi
files first, then the board files.

Merging the H3 and H5 device tree files brings in significant changes,
also to the structure of the .dtsi files. However U-Boot's own DT usage
is pretty limited, so it doesn't matter.

The huge benefit of syncing the DTs is that we can use U-Boot's DT copy
to directly pass it to the kernel, avoiding to actually load a .dtb file
from somewhere. To allows seamless and automatic UEFI booting, so
distribution installer images should just work (TM).

As a goodie the final patch brings in the actual SoPine + baseboard DT
files, which we were completely missing so far.

This is based on sunxi/master (2d53018a0ef2).

Cheers,
Andre.

Changelog v3 .. v4:
- remove MMC environment for all Allwinner boards (including 32 bit ones)
- keep MMC environment offset to the old values
- drop DT adjustments to use fixed MMC regulator

Changelog v2 .. v3:
01: added, was on the list before
02: drop redundant H5 line
03-08: unchanged
09-20: added

Changelog v1 .. v2:
01, 02, 03: unchanged
04, 05, 06, 07: added

Andre Przywara (19):
sunxi: README.sunxi64: Add hint about non-debug of ARM Trusted
Firmware
sunxi: gpio: add missing compatible strings
net: sun8i-emac: support new pinctrl DT bindings
net: sun8i-emac: add support for new EMAC DT binding
arm: dts: sunxi: update A64 to new EMAC binding
arm: dts: sunxi: update H3 to new EMAC binding
arm: dts: sunxi: update H5 to new EMAC binding
net: sun8i-emac: remove support for old binding
sunxi: disable direct MMC environment
sunxi: revert disabling of features
Revert "sunxi: Pine64: temporarily remove extra Pine64 non-plus DT"
sunxi: DT: A64: update device tree file for Allwinner A64 SoC
sunxi: DT: A64: update board .dts files from Linux
sunxi: DT: update device tree files for Allwinner H3 and H5 SoCs
sunxi: DT: H5: update board .dts files from Linux
sunxi: DT: H3: update board .dts files from Linux
sunxi: DT: H3: update libre-cc board .dts file
sunxi: DT: H2+: update Opi-zero .dts
sunxi: DT: A64: add proper SoPine baseboard device tree

arch/arm/dts/Makefile | 3 +-
arch/arm/dts/axp803.dtsi | 150 +++++
arch/arm/dts/sun50i-a64-bananapi-m64.dts | 161 +++++-
arch/arm/dts/sun50i-a64-nanopi-a64.dts | 108 +++-
arch/arm/dts/sun50i-a64-olinuxino.dts | 131 ++++-
arch/arm/dts/sun50i-a64-orangepi-win.dts | 7 +-
arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi | 50 --
arch/arm/dts/sun50i-a64-pine64-plus.dts | 17 +-
arch/arm/dts/sun50i-a64-pine64.dts | 178 +++++-
arch/arm/dts/sun50i-a64-sopine-baseboard.dts | 150 +++++
arch/arm/dts/sun50i-a64-sopine.dtsi | 142 +++++
arch/arm/dts/sun50i-a64.dtsi | 204 ++++++-
arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts | 105 +++-
arch/arm/dts/sun50i-h5-nanopi-neo2.dts | 89 ++-
arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 170 ++++--
arch/arm/dts/sun50i-h5-orangepi-prime.dts | 164 +++++-
arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts | 7 +-
arch/arm/dts/sun50i-h5.dtsi | 36 +-
arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts | 58 +-
arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts | 78 ++-
arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts | 15 +-
arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts | 71 +++
arch/arm/dts/sun8i-h3-nanopi-m1.dts | 6 +
arch/arm/dts/sun8i-h3-nanopi-neo-air.dts | 1 -
arch/arm/dts/sun8i-h3-nanopi-neo.dts | 6 +-
arch/arm/dts/sun8i-h3-orangepi-2.dts | 67 ++-
arch/arm/dts/sun8i-h3-orangepi-lite.dts | 25 +-
arch/arm/dts/sun8i-h3-orangepi-one.dts | 72 ++-
arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts | 9 +-
arch/arm/dts/sun8i-h3-orangepi-pc.dts | 88 ++-
arch/arm/dts/sun8i-h3-orangepi-plus.dts | 37 +-
arch/arm/dts/sun8i-h3-orangepi-plus2e.dts | 18 +-
arch/arm/dts/sun8i-h3.dtsi | 488 ++---------------
arch/arm/dts/sunxi-h3-h5.dtsi | 698 ++++++++++++++++++++++++
board/sunxi/README.sunxi64 | 6 +
cmd/Kconfig | 5 -
configs/pine64_plus_defconfig | 1 +
configs/sopine_baseboard_defconfig | 2 +-
drivers/gpio/sunxi_gpio.c | 3 +
drivers/net/sun8i_emac.c | 89 ++-
drivers/video/Kconfig | 2 -
env/Kconfig | 1 -
include/dt-bindings/clock/sun8i-r-ccu.h | 59 ++
include/dt-bindings/reset/sun8i-r-ccu.h | 53 ++
lib/Kconfig | 1 -
45 files changed, 2979 insertions(+), 852 deletions(-)
create mode 100644 arch/arm/dts/axp803.dtsi
delete mode 100644 arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
create mode 100644 arch/arm/dts/sun50i-a64-sopine-baseboard.dts
create mode 100644 arch/arm/dts/sun50i-a64-sopine.dtsi
create mode 100644 arch/arm/dts/sunxi-h3-h5.dtsi
create mode 100644 include/dt-bindings/clock/sun8i-r-ccu.h
create mode 100644 include/dt-bindings/reset/sun8i-r-ccu.h

--
2.14.1

[Andre Przywara]

The sunxi GPIO driver is missing some compatible strings for recent
SoCs. While most of the sunxi GPIO code seems to not rely on this (and
so works anyway), the sunxi_name_to_gpio() function does and fails at
the moment (for instance when resolving the MMC CD pin name).
Add the compatible strings for the A64 and V3s, which were missing
from the list. This now covers all pinctrl nodes in our own DTs.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
Acked-by: Maxime Ripard <maxime...@bootlin.com>
---

drivers/gpio/sunxi_gpio.c | 3 +++
1 file changed, 3 insertions(+)

diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 3cf01b6e36..ea6f3593b9 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -354,12 +354,15 @@ static const struct udevice_id sunxi_gpio_ids[] = {
ID("allwinner,sun8i-a83t-pinctrl", a_all),
ID("allwinner,sun8i-h3-pinctrl", a_all),
ID("allwinner,sun8i-r40-pinctrl", a_all),
+ ID("allwinner,sun8i-v3s-pinctrl", a_all),
ID("allwinner,sun9i-a80-pinctrl", a_all),
+ ID("allwinner,sun50i-a64-pinctrl", a_all),
ID("allwinner,sun6i-a31-r-pinctrl", l_2),
ID("allwinner,sun8i-a23-r-pinctrl", l_1),
ID("allwinner,sun8i-a83t-r-pinctrl", l_1),
ID("allwinner,sun8i-h3-r-pinctrl", l_1),
ID("allwinner,sun9i-a80-r-pinctrl", l_3),
+ ID("allwinner,sun50i-a64-r-pinctrl", l_1),
{ }
};

--
2.14.1

[Andre Przywara]

The Linux kernel driver for the Allwinner pin controller gained support
for generic properties, which are now also used in the DTs.
The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from
the DT, but so far only supported the old binding.
Update the parsing routine to cope with both the old and new bindings,
so that the newer DTs can be used with U-Boot and its Ethernet driver.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
Acked-by: Maxime Ripard <maxime...@bootlin.com>
---

drivers/net/sun8i_emac.c | 52 ++++++++++++++++++++++++++++++++++++------------
1 file changed, 39 insertions(+), 13 deletions(-)

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index be43472b1a..c8c8ef73e9 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -21,6 +21,7 @@
#include <malloc.h>
#include <miiphy.h>
#include <net.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
#ifdef CONFIG_DM_GPIO
#include <asm-generic/gpio.h>
#endif
@@ -465,30 +466,55 @@ static int parse_phy_pins(struct udevice *dev)
}

drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
- "allwinner,drive", 4);
- pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
- "allwinner,pull", 0);
+ "drive-strength", ~0);
+ if (drive != ~0) {
+ if (drive <= 10)
+ drive = SUN4I_PINCTRL_10_MA;
+ else if (drive <= 20)
+ drive = SUN4I_PINCTRL_20_MA;
+ else if (drive <= 30)
+ drive = SUN4I_PINCTRL_30_MA;
+ else
+ drive = SUN4I_PINCTRL_40_MA;
+ } else {
+ drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
+ "allwinner,drive", 4);
+ }
+
+ if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
+ pull = SUN4I_PINCTRL_PULL_UP;
+ else if (fdt_get_property(gd->fdt_blob, offset, "bias-disable", NULL))
+ pull = SUN4I_PINCTRL_NO_PULL;
+ else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
+ pull = SUN4I_PINCTRL_PULL_DOWN;
+ else
+ pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
+ "allwinner,pull", 0);
for (i = 0; ; i++) {
int pin;

pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
"allwinner,pins", i, NULL);
- if (!pin_name)
- break;
- if (pin_name[0] != 'P')
- continue;
- pin = (pin_name[1] - 'A') << 5;
- if (pin >= 26 << 5)
+ if (!pin_name) {
+ pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
+ "pins", i, NULL);
+ if (!pin_name)
+ break;
+ }
+
+ pin = sunxi_name_to_gpio(pin_name);
+ if (pin < 0)
continue;
- pin += simple_strtol(&pin_name[2], NULL, 10);

sunxi_gpio_set_cfgpin(pin, SUN8I_GPD8_GMAC);
- sunxi_gpio_set_drv(pin, drive);
- sunxi_gpio_set_pull(pin, pull);
+ if (drive != ~0)
+ sunxi_gpio_set_drv(pin, drive);
+ if (pull != ~0)
+ sunxi_gpio_set_pull(pin, pull);
}

if (!i) {
- printf("WARNING: emac: cannot find allwinner,pins property\n");
+ printf("WARNING: emac: cannot find pins property\n");
return -2;
}

--
2.14.1

[Andre Przywara]

The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an
upstream Linux driver in v4.15.
This one uses a slightly different binding from the original one used
by the U-Boot driver.
The differences to the old binding are:
- The "syscon" address is held in a separate node, referenced via a
phandle in the "syscon" property.
- The reference to the PHY is held in a property called "phy-handle",
not "phy".
- The PHY register is at offset 0x30 in the syscon device, not at 0.
- The internal PHY is activated when the node, which phy-handle points
to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node.

Teach the U-Boot driver how to find its resources in a "new-style" DT,
so that we can use a Linux kernel compatible DT for U-Boot as well.
This keeps support for the old binding for now, to allow a smooth
transition.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
Acked-by: Maxime Ripard <maxime...@bootlin.com>
---

drivers/net/sun8i_emac.c | 55 ++++++++++++++++++++++++++++++++++++++++++------
1 file changed, 48 insertions(+), 7 deletions(-)

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index c8c8ef73e9..221e95edc0 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -279,7 +279,7 @@ static int sun8i_emac_set_syscon(struct emac_eth_dev *priv)
int ret;
u32 reg;

- reg = readl(priv->sysctl_reg);
+ reg = readl(priv->sysctl_reg + 0x30);

if (priv->variant == H3_EMAC) {
ret = sun8i_emac_set_syscon_ephy(priv, &reg);
@@ -310,7 +310,7 @@ static int sun8i_emac_set_syscon(struct emac_eth_dev *priv)
return -EINVAL;
}

- writel(reg, priv->sysctl_reg);
+ writel(reg, priv->sysctl_reg + 0x30);

return 0;
}
@@ -806,17 +806,50 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
#endif

pdata->iobase = devfdt_get_addr_name(dev, "emac");
+ if (pdata->iobase == FDT_ADDR_T_NONE)
+ pdata->iobase = devfdt_get_addr(dev);
+ if (pdata->iobase == FDT_ADDR_T_NONE) {
+ debug("%s: Cannot find MAC base address\n", __func__);
+ return -EINVAL;
+ }
+
priv->sysctl_reg = devfdt_get_addr_name(dev, "syscon");
+ if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
+ const fdt32_t *reg;
+
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
+ if (offset < 0) {
+ debug("%s: cannot find syscon node\n", __func__);
+ return -EINVAL;
+ }
+ reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
+ if (!reg) {
+ debug("%s: cannot find reg property in syscon node\n",
+ __func__);
+ return -EINVAL;
+ }
+ priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
+ offset, reg);
+ } else
+ priv->sysctl_reg -= 0x30;
+ if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
+ debug("%s: Cannot find syscon base address\n", __func__);
+ return -EINVAL;
+ }

pdata->phy_interface = -1;
priv->phyaddr = -1;
priv->use_internal_phy = false;

- offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
- "phy");
- if (offset > 0)
- priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg",
- -1);
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy");
+ if (offset < 0)
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
+ "phy-handle");
+ if (offset < 0) {
+ debug("%s: Cannot find PHY address\n", __func__);
+ return -EINVAL;
+ }
+ priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);

phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);

@@ -841,6 +874,14 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
if (fdt_getprop(gd->fdt_blob, node,
"allwinner,use-internal-phy", NULL))
priv->use_internal_phy = true;
+ else {
+ int parent = fdt_parent_offset(gd->fdt_blob, offset);
+
+ if (parent >= 0 &&
+ !fdt_node_check_compatible(gd->fdt_blob, parent,
+ "allwinner,sun8i-h3-mdio-internal"))
+ priv->use_internal_phy = true;
+ }
}

priv->interface = pdata->phy_interface;
--
2.14.1

[Andre Przywara]

The U-Boot driver for the sun8i-emac was using some preliminary DT
binding. Now since Linux got its own driver in v4.15 and our driver
can now cope with both bindings, let's convert the DT nodes used for the
Pine64+ board over to the new bindings used by the kernel.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
Acked-by: Maxime Ripard <maxime...@bootlin.com>
---

arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi | 51 +++++++++++++++----------
1 file changed, 30 insertions(+), 21 deletions(-)

diff --git a/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi b/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
index 9c61beac01..32a263ce3d 100644
--- a/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
+++ b/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
@@ -4,25 +4,38 @@
};

soc {
- emac: ethernet@01c30000 {
+ syscon: syscon@1c00000 {
+ compatible = "allwinner,sun50i-a64-system-controller",
+ "syscon";
+ reg = <0x01c00000 0x1000>;
+ };
+
+ emac: ethernet@1c30000 {
compatible = "allwinner,sun50i-a64-emac";
- reg = <0x01c30000 0x2000>, <0x01c00030 0x4>;
- reg-names = "emac", "syscon";
+ syscon = <&syscon>;
+ reg = <0x01c30000 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
resets = <&ccu RST_BUS_EMAC>;
- reset-names = "ahb";
+ reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
- clock-names = "ahb";
+ clock-names = "stmmaceth";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii";
- phy = <&phy1>;
+ phy-handle = <&ext_rgmii_phy>;
status = "okay";

- phy1: ethernet-phy@1 {
- reg = <1>;
+ mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
};
};
};
@@ -30,21 +43,17 @@

&pio {
rmii_pins: rmii_pins {
- allwinner,pins = "PD10", "PD11", "PD13", "PD14",
- "PD17", "PD18", "PD19", "PD20",
- "PD22", "PD23";
- allwinner,function = "emac";
- allwinner,drive = <3>;
- allwinner,pull = <0>;
+ pins = "PD10", "PD11", "PD13", "PD14", "PD17",
+ "PD18", "PD19", "PD20", "PD22", "PD23";
+ function = "emac";
+ drive-strength = <40>;
};

rgmii_pins: rgmii_pins {
- allwinner,pins = "PD8", "PD9", "PD10", "PD11",
- "PD12", "PD13", "PD15",
- "PD16", "PD17", "PD18", "PD19",
- "PD20", "PD21", "PD22", "PD23";
- allwinner,function = "emac";
- allwinner,drive = <3>;
- allwinner,pull = <0>;
+ pins = "PD8", "PD9", "PD10", "PD11", "PD12",
+ "PD13", "PD15", "PD16", "PD17", "PD18",
+ "PD19", "PD20", "PD21", "PD22", "PD23";
+ function = "emac";
+ drive-strength = <40>;
};
};
--
2.14.1

[Andre Przywara]

The U-Boot driver for the sun8i-emac was using some preliminary DT
binding. Now since Linux got its own driver in v4.15 and our driver

can now cope with both bindings, let's convert the DT nodes used by the
various H3 boards over to the new bindings used by the kernel.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
Acked-by: Maxime Ripard <maxime...@bootlin.com>
---

arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts | 6 +--
arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts | 7 +--
arch/arm/dts/sun8i-h3-nanopi-neo.dts | 6 +--
arch/arm/dts/sun8i-h3-orangepi-2.dts | 7 +--
arch/arm/dts/sun8i-h3-orangepi-one.dts | 7 +--
arch/arm/dts/sun8i-h3-orangepi-pc.dts | 7 +--
arch/arm/dts/sun8i-h3-orangepi-plus.dts | 8 +++-
arch/arm/dts/sun8i-h3-orangepi-plus2e.dts | 9 +++-
arch/arm/dts/sun8i-h3.dtsi | 69 ++++++++++++++++++++-------
9 files changed, 75 insertions(+), 51 deletions(-)

diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
index 20d489cb2a..e0efcb3ba3 100644
--- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -100,14 +100,10 @@
};

&emac {
- phy = <&phy1>;
+ phy-handle = <&int_mii_phy>;
phy-mode = "mii";
- allwinner,use-internal-phy;
allwinner,leds-active-low;

status = "okay";
- phy1: ethernet-phy@1 {
- reg = <1>;

- };
};

&mmc0 {
diff --git a/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts b/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts
index 97b993f636..c8fd69f0a4 100644
--- a/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts
+++ b/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts
@@ -125,15 +125,10 @@
};

&emac {
- phy = <&phy1>;
+ phy-handle = <&int_mii_phy>;
phy-mode = "mii";
- allwinner,use-internal-phy;
allwinner,leds-active-low;
status = "okay";
-

- phy1: ethernet-phy@1 {
- reg = <1>;

- };
};

&ir {
diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/dts/sun8i-h3-nanopi-neo.dts
index 5113059098..78f6c24952 100644
--- a/arch/arm/dts/sun8i-h3-nanopi-neo.dts
+++ b/arch/arm/dts/sun8i-h3-nanopi-neo.dts
@@ -48,12 +48,8 @@
};

&emac {
- phy = <&phy1>;
+ phy-handle = <&int_mii_phy>;
phy-mode = "mii";
- allwinner,use-internal-phy;
allwinner,leds-active-low;

status = "okay";
- phy1: ethernet-phy@1 {
- reg = <1>;

- };
};
diff --git a/arch/arm/dts/sun8i-h3-orangepi-2.dts b/arch/arm/dts/sun8i-h3-orangepi-2.dts
index caa1a6959c..d97fdacb35 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-2.dts
@@ -55,6 +55,7 @@
aliases {
serial0 = &uart0;
/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+ ethernet0 = &emac;
ethernet1 = &rtl8189;
};

@@ -110,14 +111,10 @@
};

&emac {
- phy = <&phy1>;
+ phy-handle = <&int_mii_phy>;
phy-mode = "mii";
- allwinner,use-internal-phy;
allwinner,leds-active-low;

status = "okay";
- phy1: ethernet-phy@1 {
- reg = <1>;

- };
};

&ir {
diff --git a/arch/arm/dts/sun8i-h3-orangepi-one.dts b/arch/arm/dts/sun8i-h3-orangepi-one.dts
index 8df5c74f04..adab1cbfc9 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-one.dts
@@ -53,6 +53,7 @@
compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";

aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};

@@ -95,14 +96,10 @@
};

&emac {
- phy = <&phy1>;
+ phy-handle = <&int_mii_phy>;
phy-mode = "mii";
- allwinner,use-internal-phy;
allwinner,leds-active-low;

status = "okay";
- phy1: ethernet-phy@1 {
- reg = <1>;

- };
};

&mmc0 {
diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/dts/sun8i-h3-orangepi-pc.dts
index b8340f74e7..afba264ea5 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-pc.dts
@@ -53,6 +53,7 @@
compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";

aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};

@@ -167,12 +168,8 @@
};

&emac {
- phy = <&phy1>;
+ phy-handle = <&int_mii_phy>;
phy-mode = "mii";
- allwinner,use-internal-phy;
allwinner,leds-active-low;

status = "okay";
- phy1: ethernet-phy@1 {
- reg = <1>;

- };
};
diff --git a/arch/arm/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/dts/sun8i-h3-orangepi-plus.dts
index e7079b26bc..136e4414a4 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-plus.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-plus.dts
@@ -82,7 +82,13 @@
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-mode = "rgmii";
- /delete-property/allwinner,use-internal-phy;
+};
+
+&external_mdio {

+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";

+ reg = <0>;
+ };
};

&mmc2 {
diff --git a/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts
index f97b040b35..51aaf49b6d 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts
@@ -69,8 +69,15 @@
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
- /delete-property/allwinner,use-internal-phy;
+};
+
+&external_mdio {

+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
};

&pio {
diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi
index afa60793a2..39a6438ec4 100644
--- a/arch/arm/dts/sun8i-h3.dtsi
+++ b/arch/arm/dts/sun8i-h3.dtsi
@@ -144,9 +144,10 @@
#size-cells = <1>;
ranges;

- syscon: syscon@01c00000 {
- compatible = "allwinner,sun8i-h3-syscon","syscon";
- reg = <0x01c00000 0x34>;
+ syscon: syscon@1c00000 {
+ compatible = "allwinner,sun8i-h3-system-controller",

+ "syscon";
+ reg = <0x01c00000 0x1000>;

};

dma: dma-controller@01c02000 {
@@ -339,15 +340,12 @@
interrupt-controller;
#interrupt-cells = <3>;

- emac_rgmii_pins: emac0@0 {
- allwinner,pins = "PD0", "PD1", "PD2", "PD3",
- "PD4", "PD5", "PD7",
- "PD8", "PD9", "PD10",

- "PD12", "PD13", "PD15",

- "PD16", "PD17";
- allwinner,function = "emac";
- allwinner,drive = <SUN4I_PINCTRL_40_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ emac_rgmii_pins: emac0 {
+ pins = "PD0", "PD1", "PD2", "PD3", "PD4",
+ "PD5", "PD7", "PD8", "PD9", "PD10",
+ "PD12", "PD13", "PD15", "PD16", "PD17";

+ function = "emac";
+ drive-strength = <40>;
};

mmc0_pins_a: mmc0@0 {
@@ -466,16 +464,51 @@

emac: ethernet@1c30000 {
compatible = "allwinner,sun8i-h3-emac";
- reg = <0x01c30000 0x104>, <0x01c00030 0x4>;

- reg-names = "emac", "syscon";
+ syscon = <&syscon>;
+ reg = <0x01c30000 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;

- resets = <&ccu RST_BUS_EMAC>, <&ccu RST_BUS_EPHY>;
- reset-names = "ahb", "ephy";
- clocks = <&ccu CLK_BUS_EMAC>, <&ccu CLK_BUS_EPHY>;
- clock-names = "ahb", "ephy";
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC>;

+ clock-names = "stmmaceth";
#address-cells = <1>;
#size-cells = <0>;

status = "disabled";
+
+ mdio: mdio {

+ #address-cells = <1>;
+ #size-cells = <0>;

+ compatible = "snps,dwmac-mdio";
+ };
+
+ mdio-mux {
+ compatible = "allwinner,sun8i-h3-mdio-mux";

+ #address-cells = <1>;
+ #size-cells = <0>;
+

+ mdio-parent-bus = <&mdio>;
+ /* Only one MDIO is usable at the time */
+ internal_mdio: mdio@1 {
+ compatible = "allwinner,sun8i-h3-mdio-internal";
+ reg = <1>;

+ #address-cells = <1>;
+ #size-cells = <0>;
+

+ int_mii_phy: ethernet-phy@1 {

+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;

+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ };
+ };
+
+ external_mdio: mdio@2 {
+ reg = <2>;

+ #address-cells = <1>;
+ #size-cells = <0>;

+ };
+ };
};

gic: interrupt-controller@01c81000 {
--
2.14.1

[Andre Przywara]

The original DT binding used by U-Boot's sun8i-emac driver was not really
agreed upon, and deviated from the "official" binding now used by the
kernel. Since now all U-Boot users have been converted to the new
binding, we can remove support for the old DT nodes from the driver.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
Acked-by: Maxime Ripard <maxime...@bootlin.com>
---

drivers/net/sun8i_emac.c | 78 ++++++++++++++++--------------------------------
1 file changed, 26 insertions(+), 52 deletions(-)

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 221e95edc0..b6e5dafe83 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -456,7 +456,7 @@ static int parse_phy_pins(struct udevice *dev)
{
int offset;
const char *pin_name;
- int drive, pull, i;
+ int drive, pull = SUN4I_PINCTRL_NO_PULL, i;

offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
"pinctrl-0");
@@ -476,31 +476,20 @@ static int parse_phy_pins(struct udevice *dev)
drive = SUN4I_PINCTRL_30_MA;
else
drive = SUN4I_PINCTRL_40_MA;
- } else {
- drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
- "allwinner,drive", 4);
}

if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))

pull = SUN4I_PINCTRL_PULL_UP;
- else if (fdt_get_property(gd->fdt_blob, offset, "bias-disable", NULL))
- pull = SUN4I_PINCTRL_NO_PULL;

else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))

pull = SUN4I_PINCTRL_PULL_DOWN;
- else

- pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
- "allwinner,pull", 0);
+

for (i = 0; ; i++) {
int pin;

pin_name = fdt_stringlist_get(gd->fdt_blob, offset,

- "allwinner,pins", i, NULL);
- if (!pin_name) {
- pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
- "pins", i, NULL);

- if (!pin_name)
- break;
- }

+ "pins", i, NULL);
+ if (!pin_name)
+ break;

pin = sunxi_name_to_gpio(pin_name);
if (pin < 0)
@@ -798,6 +787,7 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
struct emac_eth_dev *priv = dev_get_priv(dev);
const char *phy_mode;
+ const fdt32_t *reg;
int node = dev_of_offset(dev);
int offset = 0;
#ifdef CONFIG_DM_GPIO
@@ -805,33 +795,25 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
int ret = 0;
#endif

- pdata->iobase = devfdt_get_addr_name(dev, "emac");
- if (pdata->iobase == FDT_ADDR_T_NONE)
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = devfdt_get_addr(dev);
if (pdata->iobase == FDT_ADDR_T_NONE) {

debug("%s: Cannot find MAC base address\n", __func__);

return -EINVAL;
}

- priv->sysctl_reg = devfdt_get_addr_name(dev, "syscon");
- if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
- const fdt32_t *reg;
-
- offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
- if (offset < 0) {
- debug("%s: cannot find syscon node\n", __func__);
- return -EINVAL;
- }
- reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
- if (!reg) {
- debug("%s: cannot find reg property in syscon node\n",
- __func__);
- return -EINVAL;
- }
- priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
- offset, reg);
- } else
- priv->sysctl_reg -= 0x30;

+ offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
+ if (offset < 0) {
+ debug("%s: cannot find syscon node\n", __func__);
+ return -EINVAL;
+ }
+ reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
+ if (!reg) {
+ debug("%s: cannot find reg property in syscon node\n",
+ __func__);
+ return -EINVAL;
+ }
+ priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
+ offset, reg);

if (priv->sysctl_reg == FDT_ADDR_T_NONE) {

debug("%s: Cannot find syscon base address\n", __func__);

return -EINVAL;
@@ -841,10 +823,7 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)

priv->phyaddr = -1;
priv->use_internal_phy = false;

- offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy");

- if (offset < 0)
- offset = fdtdec_lookup_phandle(gd->fdt_blob, node,

- "phy-handle");
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
if (offset < 0) {

debug("%s: Cannot find PHY address\n", __func__);

return -EINVAL;
@@ -871,17 +850,12 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
}

if (priv->variant == H3_EMAC) {
- if (fdt_getprop(gd->fdt_blob, node,
- "allwinner,use-internal-phy", NULL))
- priv->use_internal_phy = true;
- else {
- int parent = fdt_parent_offset(gd->fdt_blob, offset);

+ int parent = fdt_parent_offset(gd->fdt_blob, offset);

- if (parent >= 0 &&
- !fdt_node_check_compatible(gd->fdt_blob, parent,
- "allwinner,sun8i-h3-mdio-internal"))
- priv->use_internal_phy = true;
- }

+ if (parent >= 0 &&
+ !fdt_node_check_compatible(gd->fdt_blob, parent,
+ "allwinner,sun8i-h3-mdio-internal"))
+ priv->use_internal_phy = true;
}

[Andre Przywara]

The U-Boot driver for the sun8i-emac was using some preliminary DT
binding. Now since Linux got its own driver in v4.15 and our driver
can now cope with both bindings, let's convert the DT nodes used by the

OrangePi PC2 over to the new bindings used by the kernel.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
Acked-by: Maxime Ripard <maxime...@bootlin.com>
---

arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
index 780d59a096..d1c347d2b8 100644
--- a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
+++ b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
@@ -108,10 +108,13 @@

pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;

phy-mode = "rgmii";
- phy = <&phy1>;
+ phy-handle = <&ext_rgmii_phy>;
status = "okay";
+};

- phy1: ethernet-phy@1 {

+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";

reg = <1>;
};
};
--
2.14.1

[Andre Przywara]

Since the dawn of time for the Allwinner support in mainline U-Boot
we store the environment to the SD card and write directly at
544KB from the beginning of the device. This leads to problems when
the U-Boot proper image grows beyond 504KB and eventually overlaps.
With one release of having the environment preferably in a FAT
partition, let's now turn off the MMC variant fallback, so we get back
all the space we need to implement features.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
---
env/Kconfig | 1 -
1 file changed, 1 deletion(-)

diff --git a/env/Kconfig b/env/Kconfig
index a3c6298273..0c1e928f13 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -152,7 +152,6 @@ config ENV_IS_IN_MMC
bool "Environment in an MMC device"
depends on !CHAIN_OF_TRUST
depends on MMC
- default y if ARCH_SUNXI
default y if ARCH_EXYNOS4
default y if MX6SX || MX7D
default y if TEGRA30 || TEGRA124
--
2.14.1

[Andre Przywara]

In January some commits were introduced to mitigate the U-Boot image
size issues we encountered on sunxi builds.
Now with the MMC environment removed we can bring them back, as we
practically don't have a size limit anymore.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
Acked-by: Maxime Ripard <maxime...@bootlin.com>
---

cmd/Kconfig | 5 -----
drivers/video/Kconfig | 2 --
lib/Kconfig | 1 -
3 files changed, 8 deletions(-)

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 136836d146..27086df09b 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -426,7 +426,6 @@ menu "Memory commands"
config CMD_CRC32
bool "crc32"
select HASH
- default n if ARCH_SUNXI
default y
help
Compute CRC32.
@@ -568,7 +567,6 @@ config CMD_LZMADEC

config CMD_UNZIP
bool "unzip"
- default n if ARCH_SUNXI
default y if CMD_BOOTI
help
Uncompress a zip-compressed memory region.
@@ -780,14 +778,12 @@ config CMD_I2C

config CMD_LOADB
bool "loadb"
- default n if ARCH_SUNXI
default y
help
Load a binary file over serial line.

config CMD_LOADS
bool "loads"
- default n if ARCH_SUNXI
default y
help
Load an S-Record file over serial line
@@ -1187,7 +1183,6 @@ config CMD_GETTIME
# TODO: rename to CMD_SLEEP
config CMD_MISC
bool "sleep"
- default n if ARCH_SUNXI
default y
help
Delay execution for some time
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 2fc0defcd0..45a105db06 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -38,7 +38,6 @@ config BACKLIGHT_GPIO
config VIDEO_BPP8
bool "Support 8-bit-per-pixel displays"
depends on DM_VIDEO
- default n if ARCH_SUNXI
default y if DM_VIDEO
help
Support drawing text and bitmaps onto a 8-bit-per-pixel display.
@@ -49,7 +48,6 @@ config VIDEO_BPP8
config VIDEO_BPP16
bool "Support 16-bit-per-pixel displays"
depends on DM_VIDEO
- default n if ARCH_SUNXI
default y if DM_VIDEO
help
Support drawing text and bitmaps onto a 16-bit-per-pixel display.
diff --git a/lib/Kconfig b/lib/Kconfig
index 4fd41c4282..ab581f172f 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -66,7 +66,6 @@ config PANIC_HANG

config REGEX
bool "Enable regular expression support"
- default n if ARCH_SUNXI
default y if NET
help
If this variable is defined, U-Boot is linked against the
--
2.14.1

[Andre Przywara]

Now with the MMC environment gone, we have enough space to accomodate
the Pine64 "non-plus" .dtb again.

This reverts commit 47952b8e42c2790150e16d3d4235b3a1ee0ba9bb.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
---

configs/pine64_plus_defconfig | 1 +
1 file changed, 1 insertion(+)

diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index aef8c7d7a9..41ccff139d 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -10,6 +10,7 @@ CONFIG_SPL=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus"
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
--
2.14.1

[Andre Przywara]

Updates the device tree file from the the Linux tree as of v4.15-rc9,
exactly Linux commit:
commit 16416084e06e1ebff51a9e7721a8cc4ccc186f28
Author: Corentin Labbe <clabbe....@gmail.com>
Date: Tue Oct 31 09:19:15 2017 +0100
arm64: dts: allwinner: add snps,dwmac-mdio compatible to emac/mdio

This also pulls in the newly required include files for the clock and
reset bindings.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
Acked-by: Maxime Ripard <maxime...@bootlin.com>
---

arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi | 61 ++-----
arch/arm/dts/sun50i-a64.dtsi | 204 ++++++++++++++++++++----
include/dt-bindings/clock/sun8i-r-ccu.h | 59 +++++++
include/dt-bindings/reset/sun8i-r-ccu.h | 53 ++++++
4 files changed, 299 insertions(+), 78 deletions(-)

create mode 100644 include/dt-bindings/clock/sun8i-r-ccu.h
create mode 100644 include/dt-bindings/reset/sun8i-r-ccu.h

diff --git a/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi b/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
index 32a263ce3d..1b8aa3d8dc 100644
--- a/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
+++ b/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
@@ -2,58 +2,19 @@
aliases {
ethernet0 = &emac;
};
-
- soc {
- syscon: syscon@1c00000 {
- compatible = "allwinner,sun50i-a64-system-controller",
- "syscon";
- reg = <0x01c00000 0x1000>;
- };
-
- emac: ethernet@1c30000 {
- compatible = "allwinner,sun50i-a64-emac";
- syscon = <&syscon>;
- reg = <0x01c30000 0x10000>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- resets = <&ccu RST_BUS_EMAC>;
- reset-names = "stmmaceth";
- clocks = <&ccu CLK_BUS_EMAC>;
- clock-names = "stmmaceth";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- phy-mode = "rgmii";
- phy-handle = <&ext_rgmii_phy>;
- status = "okay";
-
- mdio: mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- ext_rgmii_phy: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";

- reg = <1>;
- };

- };
- };
- };
};

-&pio {
- rmii_pins: rmii_pins {
- pins = "PD10", "PD11", "PD13", "PD14", "PD17",
- "PD18", "PD19", "PD20", "PD22", "PD23";
- function = "emac";
- drive-strength = <40>;
- };
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ status = "okay";
+};

- rgmii_pins: rgmii_pins {
- pins = "PD8", "PD9", "PD10", "PD11", "PD12",
- "PD13", "PD15", "PD16", "PD17", "PD18",
- "PD19", "PD20", "PD21", "PD22", "PD23";
- function = "emac";
- drive-strength = <40>;
+&mdio {

+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";

+ reg = <1>;
};
};
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
index 65a344d9ce..d783d164b9 100644
--- a/arch/arm/dts/sun50i-a64.dtsi
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -43,6 +43,7 @@
*/

#include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/clock/sun8i-r-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/sun50i-a64-ccu.h>

@@ -129,6 +130,23 @@
#size-cells = <1>;
ranges;

+ syscon: syscon@1c00000 {
+ compatible = "allwinner,sun50i-a64-system-controller",

+ "syscon";
+ reg = <0x01c00000 0x1000>;

+ };
+
+ dma: dma-controller@1c02000 {
+ compatible = "allwinner,sun50i-a64-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DMA>;
+ dma-channels = <8>;
+ dma-requests = <27>;
+ resets = <&ccu RST_BUS_DMA>;
+ #dma-cells = <1>;
+ };
+
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun50i-a64-mmc";
reg = <0x01c0f000 0x1000>;
@@ -171,7 +189,7 @@
#size-cells = <0>;
};

- usb_otg: usb@01c19000 {
+ usb_otg: usb@1c19000 {
compatible = "allwinner,sun8i-a33-musb";
reg = <0x01c19000 0x0400>;
clocks = <&ccu CLK_BUS_OTG>;
@@ -184,7 +202,7 @@
status = "disabled";
};

- usbphy: phy@01c19400 {
+ usbphy: phy@1c19400 {
compatible = "allwinner,sun50i-a64-usb-phy";
reg = <0x01c19400 0x14>,
<0x01c1a800 0x4>,
@@ -204,7 +222,7 @@
#phy-cells = <1>;
};

- ehci0: usb@01c1a000 {
+ ehci0: usb@1c1a000 {
compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
reg = <0x01c1a000 0x100>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
@@ -216,7 +234,7 @@
status = "disabled";
};

- ohci0: usb@01c1a400 {
+ ohci0: usb@1c1a400 {
compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
reg = <0x01c1a400 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
@@ -226,7 +244,7 @@
status = "disabled";
};

- ehci1: usb@01c1b000 {
+ ehci1: usb@1c1b000 {
compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
reg = <0x01c1b000 0x100>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
@@ -240,7 +258,7 @@
status = "disabled";
};

- ohci1: usb@01c1b400 {
+ ohci1: usb@1c1b400 {
compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
reg = <0x01c1b400 0x100>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
@@ -252,7 +270,7 @@
status = "disabled";
};

- ccu: clock@01c20000 {
+ ccu: clock@1c20000 {
compatible = "allwinner,sun50i-a64-ccu";
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&osc32k>;
@@ -303,7 +321,32 @@
bias-pull-up;
};

- uart0_pins_a: uart0@0 {
+ rmii_pins: rmii_pins {

+ pins = "PD10", "PD11", "PD13", "PD14", "PD17",
+ "PD18", "PD19", "PD20", "PD22", "PD23";

+ function = "emac";
+ drive-strength = <40>;

+ };
+
+ rgmii_pins: rgmii_pins {

+ pins = "PD8", "PD9", "PD10", "PD11", "PD12",
+ "PD13", "PD15", "PD16", "PD17", "PD18",
+ "PD19", "PD20", "PD21", "PD22", "PD23";

+ function = "emac";
+ drive-strength = <40>;

+ };
+
+ spi0_pins: spi0 {
+ pins = "PC0", "PC1", "PC2", "PC3";
+ function = "spi0";
+ };
+
+ spi1_pins: spi1 {
+ pins = "PD0", "PD1", "PD2", "PD3";
+ function = "spi1";
+ };
+
+ uart0_pins_a: uart0 {
pins = "PB8", "PB9";
function = "uart0";
};
@@ -317,6 +360,26 @@
pins = "PG8", "PG9";
function = "uart1";
};
+
+ uart2_pins: uart2-pins {
+ pins = "PB0", "PB1";
+ function = "uart2";
+ };
+
+ uart3_pins: uart3-pins {
+ pins = "PD0", "PD1";
+ function = "uart3";
+ };
+
+ uart4_pins: uart4-pins {
+ pins = "PD2", "PD3";
+ function = "uart4";
+ };
+
+ uart4_rts_cts_pins: uart4-rts-cts-pins {
+ pins = "PD4", "PD5";
+ function = "uart4";
+ };
};

uart0: serial@1c28000 {
@@ -325,8 +388,8 @@
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 67>;
- resets = <&ccu 46>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};

@@ -336,8 +399,8 @@
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 68>;
- resets = <&ccu 47>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};

@@ -347,8 +410,8 @@
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 69>;
- resets = <&ccu 48>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
status = "disabled";
};

@@ -358,8 +421,8 @@
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 70>;
- resets = <&ccu 49>;
+ clocks = <&ccu CLK_BUS_UART3>;
+ resets = <&ccu RST_BUS_UART3>;
status = "disabled";
};

@@ -369,8 +432,8 @@
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 71>;
- resets = <&ccu 50>;
+ clocks = <&ccu CLK_BUS_UART4>;
+ resets = <&ccu RST_BUS_UART4>;
status = "disabled";
};

@@ -378,8 +441,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu 63>;
- resets = <&ccu 42>;
+ clocks = <&ccu CLK_BUS_I2C0>;
+ resets = <&ccu RST_BUS_I2C0>;
status = "disabled";

#address-cells = <1>;
#size-cells = <0>;

@@ -389,8 +452,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu 64>;
- resets = <&ccu 43>;
+ clocks = <&ccu CLK_BUS_I2C1>;
+ resets = <&ccu RST_BUS_I2C1>;
status = "disabled";

#address-cells = <1>;
#size-cells = <0>;

@@ -400,11 +463,67 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b400 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu 65>;
- resets = <&ccu 44>;
+ clocks = <&ccu CLK_BUS_I2C2>;
+ resets = <&ccu RST_BUS_I2C2>;
+ status = "disabled";

+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+

+
+ spi0: spi@1c68000 {
+ compatible = "allwinner,sun8i-h3-spi";
+ reg = <0x01c68000 0x1000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 23>, <&dma 23>;
+ dma-names = "rx", "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";
+ num-cs = <1>;

+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+

+ spi1: spi@1c69000 {
+ compatible = "allwinner,sun8i-h3-spi";
+ reg = <0x01c69000 0x1000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 24>, <&dma 24>;
+ dma-names = "rx", "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+ resets = <&ccu RST_BUS_SPI1>;
+ status = "disabled";
+ num-cs = <1>;

+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+

+ emac: ethernet@1c30000 {
+ compatible = "allwinner,sun50i-a64-emac";

+ syscon = <&syscon>;
+ reg = <0x01c30000 0x10000>;

+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;

+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";

status = "disabled";

#address-cells = <1>;
#size-cells = <0>;

+
+ mdio: mdio {
+ compatible = "snps,dwmac-mdio";

+ #address-cells = <1>;
+ #size-cells = <0>;

+ };
};

gic: interrupt-controller@1c81000 {
@@ -425,25 +544,54 @@
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};

+ r_intc: interrupt-controller@1f00c00 {
+ compatible = "allwinner,sun50i-a64-r-intc",
+ "allwinner,sun6i-a31-r-intc";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x01f00c00 0x400>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
r_ccu: clock@1f01400 {
compatible = "allwinner,sun50i-a64-r-ccu";
reg = <0x01f01400 0x100>;
- clocks = <&osc24M>, <&osc32k>, <&iosc>;
- clock-names = "hosc", "losc", "iosc";
+ clocks = <&osc24M>, <&osc32k>, <&iosc>,
+ <&ccu 11>;
+ clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
#reset-cells = <1>;
};

- r_pio: pinctrl@01f02c00 {
+ r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun50i-a64-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
+ clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
+
+ r_rsb_pins: rsb {
+ pins = "PL0", "PL1";
+ function = "s_rsb";
+ };
+ };
+
+ r_rsb: rsb@1f03400 {
+ compatible = "allwinner,sun8i-a23-rsb";
+ reg = <0x01f03400 0x400>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu 6>;
+ clock-frequency = <3000000>;
+ resets = <&r_ccu 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_rsb_pins>;
+ status = "disabled";

+ #address-cells = <1>;
+ #size-cells = <0>;

};
};
};
diff --git a/include/dt-bindings/clock/sun8i-r-ccu.h b/include/dt-bindings/clock/sun8i-r-ccu.h
new file mode 100644
index 0000000000..779d20aa0d
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-r-ccu.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2016 Icenowy Zheng <ice...@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_R_CCU_H_
+#define _DT_BINDINGS_CLK_SUN8I_R_CCU_H_
+
+#define CLK_AR100 0
+
+#define CLK_APB0_PIO 3
+#define CLK_APB0_IR 4
+#define CLK_APB0_TIMER 5
+#define CLK_APB0_RSB 6
+#define CLK_APB0_UART 7
+/* 8 is reserved for CLK_APB0_W1 on A31 */
+#define CLK_APB0_I2C 9
+#define CLK_APB0_TWD 10
+
+#define CLK_IR 11
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun8i-r-ccu.h b/include/dt-bindings/reset/sun8i-r-ccu.h
new file mode 100644
index 0000000000..4ba64f3d6f
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-r-ccu.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <ice...@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN8I_R_CCU_H_
+#define _DT_BINDINGS_RST_SUN8I_R_CCU_H_
+
+#define RST_APB0_IR 0
+#define RST_APB0_TIMER 1
+#define RST_APB0_RSB 2
+#define RST_APB0_UART 3
+/* 4 is reserved for RST_APB0_W1 on A31 */
+#define RST_APB0_I2C 5
+
+#endif /* _DT_BINDINGS_RST_SUN8I_R_CCU_H_ */
--
2.14.1

[Andre Przywara]

Update the device tree files from the Linux tree as of:
commit 776245ae02f63ba2b94596b892c597676e190e78
Author: Corentin Labbe <clabbe....@gmail.com>
Date: Tue Oct 31 09:19:11 2017 +0100
ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac

Since the H3 and H5 are very similar (aside from the actual ARM cores),
they share most the SoC .dtsi and thus have to be updated together.
One tiny change is the removal of the "arm/" prefix from the include
path in the sun50i-h5.dtsi, which is needed because we don't share the
same sophisticated DT directory layout of Linux.
Also we need to (temporarily) fix up the BananaPi-M2 board .dts, to
maintain bisectability.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
Acked-by: Maxime Ripard <maxime...@bootlin.com>
---

arch/arm/dts/sun50i-h5.dtsi | 36 +-
arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts | 2 +-
arch/arm/dts/sun8i-h3.dtsi | 521 ++-------------------
arch/arm/dts/sunxi-h3-h5.dtsi | 698 +++++++++++++++++++++++++++++
4 files changed, 766 insertions(+), 491 deletions(-)
create mode 100644 arch/arm/dts/sunxi-h3-h5.dtsi

diff --git a/arch/arm/dts/sun50i-h5.dtsi b/arch/arm/dts/sun50i-h5.dtsi
index c052f31131..18d45a96db 100644
--- a/arch/arm/dts/sun50i-h5.dtsi
+++ b/arch/arm/dts/sun50i-h5.dtsi
@@ -1,17 +1,17 @@
/*
- * Copyright (c) 2016 ARM Ltd.
+ * Copyright (C) 2016 ARM Ltd.
*

* This file is dual-licensed: you can use it either under the terms

* of the GPL or the X11 license, at your option. Note that this dual

* licensing only applies to this file, and not this project as a

* whole.
*
- * a) This library is free software; you can redistribute it and/or

+ * a) This file is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public License as

* published by the Free Software Foundation; either version 2 of the

* License, or (at your option) any later version.

*
- * This library is distributed in the hope that it will be useful,

+ * This file is distributed in the hope that it will be useful,

* but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

* GNU General Public License for more details.

@@ -40,24 +40,38 @@

* OTHER DEALINGS IN THE SOFTWARE.

*/

-#include "sun8i-h3.dtsi"
+#include <sunxi-h3-h5.dtsi>

/ {
cpus {

+ #address-cells = <1>;
+ #size-cells = <0>;
+

cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0>;
enable-method = "psci";
};
+
cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <1>;
enable-method = "psci";
};
+
cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <2>;
enable-method = "psci";
};
+
cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <3>;
enable-method = "psci";
};
};
@@ -69,6 +83,14 @@

timer {
compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};

@@ -76,10 +98,6 @@
compatible = "allwinner,sun50i-h5-ccu";
};

-&gic {
- compatible = "arm,gic-400";
-};
-
&mmc0 {
compatible = "allwinner,sun50i-h5-mmc",
"allwinner,sun50i-a64-mmc";
@@ -104,6 +122,6 @@
&pio {
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
compatible = "allwinner,sun50i-h5-pinctrl";
};
diff --git a/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts
index f3b1d5f6db..06fddaae8e 100644
--- a/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -185,7 +185,7 @@

&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_a>;
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
status = "okay";
};

diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi
index 39a6438ec4..b36f9f423c 100644
--- a/arch/arm/dts/sun8i-h3.dtsi
+++ b/arch/arm/dts/sun8i-h3.dtsi
@@ -40,20 +40,9 @@

* OTHER DEALINGS IN THE SOFTWARE.

*/

-#include "skeleton.dtsi"
-
-#include <dt-bindings/clock/sun8i-h3-ccu.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-#include <dt-bindings/reset/sun8i-h3-ccu.h>
+#include "sunxi-h3-h5.dtsi"

/ {
- interrupt-parent = <&gic>;
-
- aliases {
- ethernet0 = &emac;
- };
-
cpus {

#address-cells = <1>;
#size-cells = <0>;

@@ -90,478 +79,48 @@
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
+};

- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- osc24M: osc24M_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "osc24M";
- };
-
- osc32k: osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "osc32k";
- };
-
- apb0: apb0_clk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&osc24M>;
- clock-output-names = "apb0";
- };
-
- apb0_gates: clk@01f01428 {
- compatible = "allwinner,sun8i-h3-apb0-gates-clk",
- "allwinner,sun4i-a10-gates-clk";
- reg = <0x01f01428 0x4>;
- #clock-cells = <1>;
- clocks = <&apb0>;
- clock-indices = <0>, <1>;
- clock-output-names = "apb0_pio", "apb0_ir";
- };
-
- ir_clk: ir_clk@01f01454 {
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01f01454 0x4>;
- #clock-cells = <0>;
- clocks = <&osc32k>, <&osc24M>;
- clock-output-names = "ir";
- };
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- syscon: syscon@1c00000 {
- compatible = "allwinner,sun8i-h3-system-controller",

- "syscon";
- reg = <0x01c00000 0x1000>;
- };
-

- dma: dma-controller@01c02000 {
- compatible = "allwinner,sun8i-h3-dma";
- reg = <0x01c02000 0x1000>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_DMA>;
- resets = <&ccu RST_BUS_DMA>;
- #dma-cells = <1>;
- };
-
- mmc0: mmc@01c0f000 {
- compatible = "allwinner,sun7i-a20-mmc",
- "allwinner,sun5i-a13-mmc";
- reg = <0x01c0f000 0x1000>;
- clocks = <&ccu CLK_BUS_MMC0>,
- <&ccu CLK_MMC0>,
- <&ccu CLK_MMC0_OUTPUT>,
- <&ccu CLK_MMC0_SAMPLE>;

- clock-names = "ahb",

- "mmc",
- "output",
- "sample";
- resets = <&ccu RST_BUS_MMC0>;
- reset-names = "ahb";
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";

- #address-cells = <1>;
- #size-cells = <0>;

- };
-
- mmc1: mmc@01c10000 {
- compatible = "allwinner,sun7i-a20-mmc",
- "allwinner,sun5i-a13-mmc";
- reg = <0x01c10000 0x1000>;
- clocks = <&ccu CLK_BUS_MMC1>,
- <&ccu CLK_MMC1>,
- <&ccu CLK_MMC1_OUTPUT>,
- <&ccu CLK_MMC1_SAMPLE>;

- clock-names = "ahb",

- "mmc",
- "output",
- "sample";
- resets = <&ccu RST_BUS_MMC1>;
- reset-names = "ahb";
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";

- #address-cells = <1>;
- #size-cells = <0>;

- };
-
- mmc2: mmc@01c11000 {
- compatible = "allwinner,sun7i-a20-mmc",
- "allwinner,sun5i-a13-mmc";
- reg = <0x01c11000 0x1000>;
- clocks = <&ccu CLK_BUS_MMC2>,
- <&ccu CLK_MMC2>,
- <&ccu CLK_MMC2_OUTPUT>,
- <&ccu CLK_MMC2_SAMPLE>;

- clock-names = "ahb",

- "mmc",
- "output",
- "sample";
- resets = <&ccu RST_BUS_MMC2>;
- reset-names = "ahb";
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";

- #address-cells = <1>;
- #size-cells = <0>;

- };
-
- usbphy: phy@01c19400 {
- compatible = "allwinner,sun8i-h3-usb-phy";
- reg = <0x01c19400 0x2c>,
- <0x01c1a800 0x4>,
- <0x01c1b800 0x4>,
- <0x01c1c800 0x4>,
- <0x01c1d800 0x4>;
- reg-names = "phy_ctrl",
- "pmu0",
- "pmu1",
- "pmu2",
- "pmu3";
- clocks = <&ccu CLK_USB_PHY0>,
- <&ccu CLK_USB_PHY1>,
- <&ccu CLK_USB_PHY2>,
- <&ccu CLK_USB_PHY3>;
- clock-names = "usb0_phy",
- "usb1_phy",
- "usb2_phy",
- "usb3_phy";
- resets = <&ccu RST_USB_PHY0>,
- <&ccu RST_USB_PHY1>,
- <&ccu RST_USB_PHY2>,
- <&ccu RST_USB_PHY3>;
- reset-names = "usb0_reset",
- "usb1_reset",
- "usb2_reset",
- "usb3_reset";
- status = "disabled";
- #phy-cells = <1>;
- };
-
- ehci1: usb@01c1b000 {
- compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
- reg = <0x01c1b000 0x100>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
- resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
- phys = <&usbphy 1>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ohci1: usb@01c1b400 {
- compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
- reg = <0x01c1b400 0x100>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
- <&ccu CLK_USB_OHCI1>;
- resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
- phys = <&usbphy 1>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ehci2: usb@01c1c000 {
- compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
- reg = <0x01c1c000 0x100>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
- resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
- phys = <&usbphy 2>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ohci2: usb@01c1c400 {
- compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
- reg = <0x01c1c400 0x100>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
- <&ccu CLK_USB_OHCI2>;
- resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
- phys = <&usbphy 2>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ehci3: usb@01c1d000 {
- compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
- reg = <0x01c1d000 0x100>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
- resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
- phys = <&usbphy 3>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ohci3: usb@01c1d400 {
- compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
- reg = <0x01c1d400 0x100>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
- <&ccu CLK_USB_OHCI3>;
- resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
- phys = <&usbphy 3>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ccu: clock@01c20000 {
- compatible = "allwinner,sun8i-h3-ccu";
- reg = <0x01c20000 0x400>;
- clocks = <&osc24M>, <&osc32k>;
- clock-names = "hosc", "losc";
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- pio: pinctrl@01c20800 {
- compatible = "allwinner,sun8i-h3-pinctrl";
- reg = <0x01c20800 0x400>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_PIO>;
- gpio-controller;
- #gpio-cells = <3>;
- interrupt-controller;
- #interrupt-cells = <3>;
-
- emac_rgmii_pins: emac0 {
- pins = "PD0", "PD1", "PD2", "PD3", "PD4",
- "PD5", "PD7", "PD8", "PD9", "PD10",
- "PD12", "PD13", "PD15", "PD16", "PD17";

- function = "emac";
- drive-strength = <40>;
- };

-
- mmc0_pins_a: mmc0@0 {
- allwinner,pins = "PF0", "PF1", "PF2", "PF3",
- "PF4", "PF5";
- allwinner,function = "mmc0";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- mmc0_cd_pin: mmc0_cd_pin@0 {
- allwinner,pins = "PF6";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
- };
-
- mmc1_pins_a: mmc1@0 {
- allwinner,pins = "PG0", "PG1", "PG2", "PG3",
- "PG4", "PG5";
- allwinner,function = "mmc1";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- mmc2_8bit_pins: mmc2_8bit {
- allwinner,pins = "PC5", "PC6", "PC8",
- "PC9", "PC10", "PC11",
- "PC12", "PC13", "PC14",
- "PC15", "PC16";
- allwinner,function = "mmc2";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart0_pins_a: uart0@0 {
- allwinner,pins = "PA4", "PA5";
- allwinner,function = "uart0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart1_pins_a: uart1@0 {
- allwinner,pins = "PG6", "PG7", "PG8", "PG9";
- allwinner,function = "uart1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
- };
-
- timer@01c20c00 {
- compatible = "allwinner,sun4i-a10-timer";
- reg = <0x01c20c00 0xa0>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc24M>;
- };
-
- wdt0: watchdog@01c20ca0 {
- compatible = "allwinner,sun6i-a31-wdt";
- reg = <0x01c20ca0 0x20>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- uart0: serial@01c28000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28000 0x400>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_BUS_UART0>;
- resets = <&ccu RST_BUS_UART0>;
- dmas = <&dma 6>, <&dma 6>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart1: serial@01c28400 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28400 0x400>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_BUS_UART1>;
- resets = <&ccu RST_BUS_UART1>;
- dmas = <&dma 7>, <&dma 7>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart2: serial@01c28800 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28800 0x400>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_BUS_UART2>;
- resets = <&ccu RST_BUS_UART2>;
- dmas = <&dma 8>, <&dma 8>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart3: serial@01c28c00 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28c00 0x400>;
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_BUS_UART3>;
- resets = <&ccu RST_BUS_UART3>;
- dmas = <&dma 9>, <&dma 9>;
- dma-names = "rx", "tx";
- status = "disabled";

- };
-
- emac: ethernet@1c30000 {

- compatible = "allwinner,sun8i-h3-emac";

- syscon = <&syscon>;
- reg = <0x01c30000 0x10000>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- resets = <&ccu RST_BUS_EMAC>;
- reset-names = "stmmaceth";
- clocks = <&ccu CLK_BUS_EMAC>;
- clock-names = "stmmaceth";
- #address-cells = <1>;
- #size-cells = <0>;

- status = "disabled";
-
- mdio: mdio {

- #address-cells = <1>;
- #size-cells = <0>;

- compatible = "snps,dwmac-mdio";
- };
-
- mdio-mux {
- compatible = "allwinner,sun8i-h3-mdio-mux";

- #address-cells = <1>;
- #size-cells = <0>;
-

- mdio-parent-bus = <&mdio>;
- /* Only one MDIO is usable at the time */
- internal_mdio: mdio@1 {
- compatible = "allwinner,sun8i-h3-mdio-internal";
- reg = <1>;

- #address-cells = <1>;
- #size-cells = <0>;
-

- int_mii_phy: ethernet-phy@1 {

- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <1>;

- clocks = <&ccu CLK_BUS_EPHY>;
- resets = <&ccu RST_BUS_EPHY>;
- };
- };
-
- external_mdio: mdio@2 {
- reg = <2>;

- #address-cells = <1>;
- #size-cells = <0>;

- };
- };
- };
-
- gic: interrupt-controller@01c81000 {
- compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
- reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
- <0x01c84000 0x2000>,
- <0x01c86000 0x2000>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- rtc: rtc@01f00000 {
- compatible = "allwinner,sun6i-a31-rtc";
- reg = <0x01f00000 0x54>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- };
+&ccu {
+ compatible = "allwinner,sun8i-h3-ccu";
+};

- apb0_reset: reset@01f014b0 {
- reg = <0x01f014b0 0x4>;
- compatible = "allwinner,sun6i-a31-clock-reset";
- #reset-cells = <1>;
- };
+&mmc0 {
+ compatible = "allwinner,sun7i-a20-mmc";
+ clocks = <&ccu CLK_BUS_MMC0>,
+ <&ccu CLK_MMC0>,
+ <&ccu CLK_MMC0_OUTPUT>,
+ <&ccu CLK_MMC0_SAMPLE>;

+ clock-names = "ahb",

+ "mmc",
+ "output",
+ "sample";
+};

- ir: ir@01f02000 {
- compatible = "allwinner,sun5i-a13-ir";
- clocks = <&apb0_gates 1>, <&ir_clk>;
- clock-names = "apb", "ir";
- resets = <&apb0_reset 1>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x01f02000 0x40>;
- status = "disabled";
- };
+&mmc1 {
+ compatible = "allwinner,sun7i-a20-mmc";
+ clocks = <&ccu CLK_BUS_MMC1>,
+ <&ccu CLK_MMC1>,
+ <&ccu CLK_MMC1_OUTPUT>,
+ <&ccu CLK_MMC1_SAMPLE>;

+ clock-names = "ahb",

+ "mmc",
+ "output",
+ "sample";
+};

- r_pio: pinctrl@01f02c00 {
- compatible = "allwinner,sun8i-h3-r-pinctrl";
- reg = <0x01f02c00 0x400>;
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 0>;
- resets = <&apb0_reset 0>;
- gpio-controller;
- #gpio-cells = <3>;
- interrupt-controller;
- #interrupt-cells = <3>;
+&mmc2 {
+ compatible = "allwinner,sun7i-a20-mmc";
+ clocks = <&ccu CLK_BUS_MMC2>,
+ <&ccu CLK_MMC2>,
+ <&ccu CLK_MMC2_OUTPUT>,
+ <&ccu CLK_MMC2_SAMPLE>;

+ clock-names = "ahb",

+ "mmc",
+ "output",
+ "sample";
+};

- ir_pins_a: ir@0 {
- allwinner,pins = "PL11";
- allwinner,function = "s_cir_rx";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
- };
- };
+&pio {
+ compatible = "allwinner,sun8i-h3-pinctrl";
};
diff --git a/arch/arm/dts/sunxi-h3-h5.dtsi b/arch/arm/dts/sunxi-h3-h5.dtsi
new file mode 100644
index 0000000000..8d40c00d64
--- /dev/null
+++ b/arch/arm/dts/sunxi-h3-h5.dtsi
@@ -0,0 +1,698 @@
+/*
+ * Copyright (C) 2015 Jens Kuske <jens...@gmail.com>

+#include <dt-bindings/clock/sun8i-h3-ccu.h>
+#include <dt-bindings/clock/sun8i-r-ccu.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/sun8i-h3-ccu.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ iosc: internal-osc-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16000000>;
+ clock-accuracy = <300000000>;
+ clock-output-names = "iosc";
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ syscon: syscon@1c00000 {
+ compatible = "allwinner,sun8i-h3-system-controller",

+ "syscon";
+ reg = <0x01c00000 0x1000>;
+ };
+
+ dma: dma-controller@1c02000 {

+ compatible = "allwinner,sun8i-h3-dma";

+ reg = <0x01c02000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DMA>;

+ resets = <&ccu RST_BUS_DMA>;
+ #dma-cells = <1>;
+ };
+

+ mmc0: mmc@1c0f000 {
+ /* compatible and clocks are in per SoC .dtsi file */
+ reg = <0x01c0f000 0x1000>;
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;

+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+

+ mmc1: mmc@1c10000 {
+ /* compatible and clocks are in per SoC .dtsi file */
+ reg = <0x01c10000 0x1000>;
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;

+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+

+ mmc2: mmc@1c11000 {
+ /* compatible and clocks are in per SoC .dtsi file */
+ reg = <0x01c11000 0x1000>;
+ resets = <&ccu RST_BUS_MMC2>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;

+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+

+ usb_otg: usb@1c19000 {
+ compatible = "allwinner,sun8i-h3-musb";
+ reg = <0x01c19000 0x400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ status = "disabled";
+ };
+
+ usbphy: phy@1c19400 {
+ compatible = "allwinner,sun8i-h3-usb-phy";
+ reg = <0x01c19400 0x2c>,
+ <0x01c1a800 0x4>,
+ <0x01c1b800 0x4>,
+ <0x01c1c800 0x4>,
+ <0x01c1d800 0x4>;
+ reg-names = "phy_ctrl",
+ "pmu0",
+ "pmu1",
+ "pmu2",
+ "pmu3";
+ clocks = <&ccu CLK_USB_PHY0>,
+ <&ccu CLK_USB_PHY1>,
+ <&ccu CLK_USB_PHY2>,
+ <&ccu CLK_USB_PHY3>;
+ clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy",
+ "usb3_phy";
+ resets = <&ccu RST_USB_PHY0>,
+ <&ccu RST_USB_PHY1>,
+ <&ccu RST_USB_PHY2>,
+ <&ccu RST_USB_PHY3>;
+ reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset",
+ "usb3_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci0: usb@1c1a000 {
+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
+ resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
+ ohci0: usb@1c1a400 {
+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
+ ehci1: usb@1c1b000 {
+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+ reg = <0x01c1b000 0x100>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
+ resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@1c1b400 {
+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+ reg = <0x01c1b400 0x100>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci2: usb@1c1c000 {
+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+ reg = <0x01c1c000 0x100>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
+ resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci2: usb@1c1c400 {
+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+ reg = <0x01c1c400 0x100>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
+ <&ccu CLK_USB_OHCI2>;
+ resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci3: usb@1c1d000 {
+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+ reg = <0x01c1d000 0x100>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
+ resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
+ phys = <&usbphy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci3: usb@1c1d400 {
+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+ reg = <0x01c1d400 0x100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
+ <&ccu CLK_USB_OHCI3>;
+ resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
+ phys = <&usbphy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ccu: clock@1c20000 {
+ /* compatible is in per SoC .dtsi file */
+ reg = <0x01c20000 0x400>;
+ clocks = <&osc24M>, <&osc32k>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pio: pinctrl@1c20800 {
+ /* compatible is in per SoC .dtsi file */
+ reg = <0x01c20800 0x400>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+

+ emac_rgmii_pins: emac0 {
+ pins = "PD0", "PD1", "PD2", "PD3", "PD4",

+ "PD5", "PD7", "PD8", "PD9", "PD10",
+ "PD12", "PD13", "PD15", "PD16", "PD17";

+ function = "emac";
+ drive-strength = <40>;
+ };
+

+ i2c0_pins: i2c0 {
+ pins = "PA11", "PA12";
+ function = "i2c0";
+ };
+
+ i2c1_pins: i2c1 {
+ pins = "PA18", "PA19";
+ function = "i2c1";
+ };
+
+ i2c2_pins: i2c2 {
+ pins = "PE12", "PE13";
+ function = "i2c2";
+ };
+
+ mmc0_pins_a: mmc0 {
+ pins = "PF0", "PF1", "PF2", "PF3",
+ "PF4", "PF5";
+ function = "mmc0";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ mmc0_cd_pin: mmc0_cd_pin {
+ pins = "PF6";
+ function = "gpio_in";
+ bias-pull-up;
+ };
+
+ mmc1_pins_a: mmc1 {
+ pins = "PG0", "PG1", "PG2", "PG3",
+ "PG4", "PG5";
+ function = "mmc1";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ mmc2_8bit_pins: mmc2_8bit {
+ pins = "PC5", "PC6", "PC8",
+ "PC9", "PC10", "PC11",
+ "PC12", "PC13", "PC14",
+ "PC15", "PC16";
+ function = "mmc2";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ spdif_tx_pins_a: spdif {
+ pins = "PA17";
+ function = "spdif";

+ };
+
+ spi0_pins: spi0 {
+ pins = "PC0", "PC1", "PC2", "PC3";
+ function = "spi0";
+ };
+
+ spi1_pins: spi1 {

+ pins = "PA15", "PA16", "PA14", "PA13";

+ function = "spi1";
+ };
+
+ uart0_pins_a: uart0 {

+ pins = "PA4", "PA5";
+ function = "uart0";
+ };
+
+ uart1_pins: uart1 {
+ pins = "PG6", "PG7";
+ function = "uart1";
+ };
+
+ uart1_rts_cts_pins: uart1_rts_cts {
+ pins = "PG8", "PG9";
+ function = "uart1";
+ };
+
+ uart2_pins: uart2 {
+ pins = "PA0", "PA1";

+ function = "uart2";
+ };
+

+ uart3_pins: uart3 {
+ pins = "PA13", "PA14";

+ function = "uart3";
+ };
+

+ uart3_rts_cts_pins: uart3_rts_cts {
+ pins = "PA15", "PA16";

+ function = "uart3";
+ };
+ };
+

+ timer@1c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0xa0>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;

+ };
+
+ emac: ethernet@1c30000 {

+ compatible = "allwinner,sun8i-h3-emac";

+ syscon = <&syscon>;
+ reg = <0x01c30000 0x10000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";

+ #address-cells = <1>;
+ #size-cells = <0>;

+ status = "disabled";
+
+ mdio: mdio {

+ #address-cells = <1>;
+ #size-cells = <0>;

+ compatible = "snps,dwmac-mdio";
+ };
+
+ mdio-mux {
+ compatible = "allwinner,sun8i-h3-mdio-mux";

+ #address-cells = <1>;
+ #size-cells = <0>;
+

+ mdio-parent-bus = <&mdio>;
+ /* Only one MDIO is usable at the time */
+ internal_mdio: mdio@1 {
+ compatible = "allwinner,sun8i-h3-mdio-internal";

+ reg = <1>;

+ #address-cells = <1>;
+ #size-cells = <0>;
+

+ int_mii_phy: ethernet-phy@1 {

+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;

+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ };
+ };
+
+ external_mdio: mdio@2 {
+ reg = <2>;

+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+
+ spi0: spi@1c68000 {
+ compatible = "allwinner,sun8i-h3-spi";
+ reg = <0x01c68000 0x1000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 23>, <&dma 23>;
+ dma-names = "rx", "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";

+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@1c69000 {
+ compatible = "allwinner,sun8i-h3-spi";
+ reg = <0x01c69000 0x1000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 24>, <&dma 24>;
+ dma-names = "rx", "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+ resets = <&ccu RST_BUS_SPI1>;
+ status = "disabled";

+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+

+ wdt0: watchdog@1c20ca0 {
+ compatible = "allwinner,sun6i-a31-wdt";
+ reg = <0x01c20ca0 0x20>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ spdif: spdif@1c21000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-h3-spdif";
+ reg = <0x01c21000 0x400>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
+ resets = <&ccu RST_BUS_SPDIF>;
+ clock-names = "apb", "spdif";
+ dmas = <&dma 2>;
+ dma-names = "tx";
+ status = "disabled";
+ };
+
+ pwm: pwm@1c21400 {
+ compatible = "allwinner,sun8i-h3-pwm";
+ reg = <0x01c21400 0x8>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ i2s0: i2s@1c22000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-h3-i2s";
+ reg = <0x01c22000 0x400>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 3>, <&dma 3>;
+ resets = <&ccu RST_BUS_I2S0>;

+ dma-names = "rx", "tx";

+ status = "disabled";
+ };
+
+ i2s1: i2s@1c22400 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-h3-i2s";
+ reg = <0x01c22400 0x400>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 4>, <&dma 4>;
+ resets = <&ccu RST_BUS_I2S1>;

+ dma-names = "rx", "tx";

+ status = "disabled";
+ };
+
+ codec: codec@1c22c00 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-h3-codec";
+ reg = <0x01c22c00 0x400>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
+ clock-names = "apb", "codec";
+ resets = <&ccu RST_BUS_CODEC>;
+ dmas = <&dma 15>, <&dma 15>;

+ dma-names = "rx", "tx";

+ allwinner,codec-analog-controls = <&codec_analog>;
+ status = "disabled";
+ };
+
+ uart0: serial@1c28000 {
+ compatible = "snps,dw-apb-uart";

+ reg = <0x01c28000 0x400>;

+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;

+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;

+ dmas = <&dma 6>, <&dma 6>;

+ dma-names = "rx", "tx";

+ status = "disabled";
+ };
+
+ uart1: serial@1c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;

+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;

+ dmas = <&dma 7>, <&dma 7>;

+ dma-names = "rx", "tx";

+ status = "disabled";
+ };
+
+ uart2: serial@1c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;

+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;

+ dmas = <&dma 8>, <&dma 8>;

+ dma-names = "rx", "tx";

+ status = "disabled";
+ };
+
+ uart3: serial@1c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;

+ clocks = <&ccu CLK_BUS_UART3>;
+ resets = <&ccu RST_BUS_UART3>;

+ dmas = <&dma 9>, <&dma 9>;

+ dma-names = "rx", "tx";

+ status = "disabled";
+ };
+
+ i2c0: i2c@1c2ac00 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2ac00 0x400>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;

+ clocks = <&ccu CLK_BUS_I2C0>;
+ resets = <&ccu RST_BUS_I2C0>;

+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;

+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+

+ i2c1: i2c@1c2b000 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;

+ clocks = <&ccu CLK_BUS_I2C1>;
+ resets = <&ccu RST_BUS_I2C1>;

+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;

+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+

+ i2c2: i2c@1c2b400 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b400 0x400>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;

+ clocks = <&ccu CLK_BUS_I2C2>;
+ resets = <&ccu RST_BUS_I2C2>;

+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;

+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+

+ gic: interrupt-controller@1c81000 {
+ compatible = "arm,gic-400";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x2000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ rtc: rtc@1f00000 {
+ compatible = "allwinner,sun6i-a31-rtc";
+ reg = <0x01f00000 0x54>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ r_ccu: clock@1f01400 {
+ compatible = "allwinner,sun8i-h3-r-ccu";
+ reg = <0x01f01400 0x100>;

+ clocks = <&osc24M>, <&osc32k>, <&iosc>,

+ <&ccu 9>;

+ clock-names = "hosc", "losc", "iosc", "pll-periph";

+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ codec_analog: codec-analog@1f015c0 {
+ compatible = "allwinner,sun8i-h3-codec-analog";
+ reg = <0x01f015c0 0x4>;
+ };
+
+ ir: ir@1f02000 {
+ compatible = "allwinner,sun5i-a13-ir";
+ clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ resets = <&r_ccu RST_APB0_IR>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x01f02000 0x40>;
+ status = "disabled";
+ };
+
+ r_pio: pinctrl@1f02c00 {
+ compatible = "allwinner,sun8i-h3-r-pinctrl";
+ reg = <0x01f02c00 0x400>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;

+ clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;

+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ ir_pins_a: ir {
+ pins = "PL11";
+ function = "s_cir_rx";
+ };
+ };
+ };
+};
--
2.14.1

[Andre Przywara]

Update the .dts files for the various boards with an Allwinner A64 SoC.
This is as of v4.15-rc9, exactly Linux commit:
commit bdfe4cebea11476d278b1b98dd0f7cdac8269d62
Author: Icenowy Zheng <ice...@aosc.io>
Date: Fri Nov 10 17:26:54 2017 +0800
arm64: allwinner: a64: add Ethernet PHY regulator for several boards

It updates the existing DT files, adds the newly added axp803.dtsi and
removes our temporary kludge file to get Ethernet support in U-Boot.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
Acked-by: Maxime Ripard <maxime...@bootlin.com>
---

arch/arm/dts/axp803.dtsi | 150 ++++++++++++++++++++
arch/arm/dts/sun50i-a64-bananapi-m64.dts | 161 +++++++++++++++++++--
arch/arm/dts/sun50i-a64-nanopi-a64.dts | 108 ++++++++++++--
arch/arm/dts/sun50i-a64-olinuxino.dts | 131 +++++++++++++++--
arch/arm/dts/sun50i-a64-orangepi-win.dts | 7 +-
arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi | 20 ---
arch/arm/dts/sun50i-a64-pine64-plus.dts | 17 ++-
arch/arm/dts/sun50i-a64-pine64.dts | 178 +++++++++++++++++++++++-
8 files changed, 716 insertions(+), 56 deletions(-)

create mode 100644 arch/arm/dts/axp803.dtsi
delete mode 100644 arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi

diff --git a/arch/arm/dts/axp803.dtsi b/arch/arm/dts/axp803.dtsi
new file mode 100644
index 0000000000..ff8af52743
--- /dev/null
+++ b/arch/arm/dts/axp803.dtsi
@@ -0,0 +1,150 @@
+/*
+ * Copyright 2017 Icenowy Zheng <ice...@aosc.xyz>

+/*
+ * AXP803 Integrated Power Management Chip
+ * http://files.pine64.org/doc/datasheet/pine64/AXP803_Datasheet_V1.0.pdf
+ */
+
+&axp803 {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ regulators {
+ /* Default work frequency for buck regulators */
+ x-powers,dcdc-freq = <3000>;
+
+ reg_aldo1: aldo1 {
+ regulator-name = "aldo1";
+ };
+
+ reg_aldo2: aldo2 {
+ regulator-name = "aldo2";
+ };
+
+ reg_aldo3: aldo3 {
+ regulator-name = "aldo3";
+ };
+
+ reg_dc1sw: dc1sw {
+ regulator-name = "dc1sw";
+ };
+
+ reg_dcdc1: dcdc1 {
+ regulator-name = "dcdc1";
+ };
+
+ reg_dcdc2: dcdc2 {
+ regulator-name = "dcdc2";
+ };
+
+ reg_dcdc3: dcdc3 {
+ regulator-name = "dcdc3";
+ };
+
+ reg_dcdc4: dcdc4 {
+ regulator-name = "dcdc4";
+ };
+
+ reg_dcdc5: dcdc5 {
+ regulator-name = "dcdc5";
+ };
+
+ reg_dcdc6: dcdc6 {
+ regulator-name = "dcdc6";
+ };
+
+ reg_dldo1: dldo1 {
+ regulator-name = "dldo1";
+ };
+
+ reg_dldo2: dldo2 {
+ regulator-name = "dldo2";
+ };
+
+ reg_dldo3: dldo3 {
+ regulator-name = "dldo3";
+ };
+
+ reg_dldo4: dldo4 {
+ regulator-name = "dldo4";
+ };
+
+ reg_eldo1: eldo1 {
+ regulator-name = "eldo1";
+ };
+
+ reg_eldo2: eldo2 {
+ regulator-name = "eldo2";
+ };
+
+ reg_eldo3: eldo3 {
+ regulator-name = "eldo3";
+ };
+
+ reg_fldo1: fldo1 {
+ regulator-name = "fldo1";
+ };
+
+ reg_fldo2: fldo2 {
+ regulator-name = "fldo2";
+ };
+
+ reg_ldo_io0: ldo-io0 {
+ regulator-name = "ldo-io0";

+ status = "disabled";
+ };
+

+ reg_ldo_io1: ldo-io1 {
+ regulator-name = "ldo-io1";

+ status = "disabled";
+ };
+

+ reg_rtc_ldo: rtc-ldo {
+ /* RTC_LDO is a fixed, always-on regulator */
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "rtc-ldo";
+ };
+ };
+};
diff --git a/arch/arm/dts/sun50i-a64-bananapi-m64.dts b/arch/arm/dts/sun50i-a64-bananapi-m64.dts
index 02db114113..4a8d3f83a3 100644
--- a/arch/arm/dts/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm/dts/sun50i-a64-bananapi-m64.dts
@@ -1,6 +1,5 @@
/*

* Copyright (c) 2016 ARM Ltd.

- * Copyright (C) 2017 Jagan Teki <jt...@openedev.com>

*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual

@@ -52,6 +51,7 @@
compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64";

aliases {
+ ethernet0 = &emac;
serial0 = &uart0;

serial1 = &uart1;
};
@@ -60,14 +60,25 @@
stdout-path = "serial0:115200n8";
};

- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
};
};

+&ehci1 {

+ status = "okay";
+};

+
+&emac {
+ pinctrl-names = "default";

+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;

+ phy-supply = <&reg_dc1sw>;

+ status = "okay";
+};

+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@@ -78,10 +89,17 @@
bias-pull-up;
};

+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {

+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;

+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
- vmmc-supply = <&reg_vcc3v3>;
+ vmmc-supply = <&reg_dcdc1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
disable-wp;
@@ -92,22 +110,143 @@
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
- vmmc-supply = <&reg_vcc3v3>;
+ vmmc-supply = <&reg_dldo2>;
+ vqmmc-supply = <&reg_dldo4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
+ interrupt-names = "host-wake";
+ };
};

&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
- vmmc-supply = <&reg_vcc3v3>;
+ vmmc-supply = <&reg_dcdc1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
status = "okay";
};

+&ohci1 {

+ status = "okay";
+};

+
+&r_rsb {

+ status = "okay";
+

+ axp803: pmic@3a3 {
+ compatible = "x-powers,axp803";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp803.dtsi"
+
+&reg_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl";
+};
+
+&reg_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+&reg_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+&reg_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1040000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+&reg_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+&reg_dcdc6 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys";
+};
+
+&reg_dldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-hdmi-dsi";
+};
+
+&reg_dldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+&reg_dldo4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-io";
+};
+
+&reg_eldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "cpvdd";
+};
+
+&reg_fldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-1v2-hsic";
+};
+
+/*
+ * The A64 chip cannot work without this regulator off, although
+ * it seems to be only driving the AR100 core.
+ * Maybe we don't still know well about CPUs domain.
+ */
+&reg_fldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpus";
+};
+
+&reg_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
@@ -119,3 +258,7 @@

pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
status = "okay";
};

+
+&usbphy {

+ status = "okay";
+};

diff --git a/arch/arm/dts/sun50i-a64-nanopi-a64.dts b/arch/arm/dts/sun50i-a64-nanopi-a64.dts
index 778636c73a..2beef9e6cb 100644
--- a/arch/arm/dts/sun50i-a64-nanopi-a64.dts
+++ b/arch/arm/dts/sun50i-a64-nanopi-a64.dts
@@ -57,13 +57,6 @@
chosen {
stdout-path = "serial0:115200n8";
};
-
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
};

&ehci0 {
@@ -88,7 +81,7 @@
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
- vmmc-supply = <&reg_vcc3v3>;
+ vmmc-supply = <&reg_dcdc1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
disable-wp;
@@ -104,6 +97,105 @@
status = "okay";
};

+&r_rsb {

+ status = "okay";
+

+ axp803: pmic@3a3 {
+ compatible = "x-powers,axp803";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp803.dtsi"
+
+&reg_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl";
+};
+
+&reg_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-3v";
+};
+
+&reg_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1040000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+&reg_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+&reg_dcdc6 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys";
+};
+
+&reg_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-hdmi-dsi";
+};
+
+&reg_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-pg-wifi-io";
+};
+
+&reg_eldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "cpvdd";
+};
+
+&reg_fldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-1v2-hsic";
+};
+
+/*
+ * The A64 chip cannot work without this regulator off, although
+ * it seems to be only driving the AR100 core.
+ * Maybe we don't still know well about CPUs domain.
+ */
+&reg_fldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpus";
+};
+
+&reg_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm/dts/sun50i-a64-olinuxino.dts b/arch/arm/dts/sun50i-a64-olinuxino.dts
index 7bd4730c93..338e786155 100644
--- a/arch/arm/dts/sun50i-a64-olinuxino.dts
+++ b/arch/arm/dts/sun50i-a64-olinuxino.dts
@@ -57,19 +57,12 @@
chosen {
stdout-path = "serial0:115200n8";
};
-
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
};

&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
- vmmc-supply = <&reg_vcc3v3>;
+ vmmc-supply = <&reg_dcdc1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
disable-wp;
@@ -77,6 +70,128 @@
status = "okay";
};

+&r_rsb {

+ status = "okay";
+

+ axp803: pmic@3a3 {
+ compatible = "x-powers,axp803";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp803.dtsi"
+
+&reg_aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vcc-pe";
+};
+
+&reg_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl";
+};
+
+&reg_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+&reg_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1040000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+&reg_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-ddr3";
+};
+
+&reg_dcdc6 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys";
+};
+
+&reg_dldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-hdmi";
+};
+
+&reg_dldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-mipi";
+};
+
+&reg_dldo3 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vcc-avdd-csi";
+};
+
+&reg_dldo4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-io";
+};
+
+&reg_eldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "cpvdd";
+};
+
+&reg_eldo2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-dvdd-csi";
+};
+
+&reg_fldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-1v2-hsic";
+};
+
+/*
+ * The A64 chip cannot work without this regulator off, although
+ * it seems to be only driving the AR100 core.
+ * Maybe we don't still know well about CPUs domain.
+ */
+&reg_fldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpus";
+};
+
+&reg_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm/dts/sun50i-a64-orangepi-win.dts b/arch/arm/dts/sun50i-a64-orangepi-win.dts
index cf76c35237..5f8ff4017d 100644
--- a/arch/arm/dts/sun50i-a64-orangepi-win.dts
+++ b/arch/arm/dts/sun50i-a64-orangepi-win.dts
@@ -67,7 +67,7 @@
};

&ehci1 {
- status = "okay";
+ status = "okay";
};

&mmc0 {
@@ -80,7 +80,7 @@
};

&ohci1 {
- status = "okay";
+ status = "okay";
};

&uart0 {
@@ -90,5 +90,6 @@
};

&usbphy {
- status = "okay";

+ status = "okay";
};
+

diff --git a/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi b/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
deleted file mode 100644
index 1b8aa3d8dc..0000000000
--- a/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
+++ /dev/null
@@ -1,20 +0,0 @@
-/ {

- aliases {
- ethernet0 = &emac;
- };

-};
-
-&emac {

- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- phy-mode = "rgmii";
- phy-handle = <&ext_rgmii_phy>;
- status = "okay";
-};
-

-&mdio {
- ext_rgmii_phy: ethernet-phy@1 {

- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <1>;

- };
-};
diff --git a/arch/arm/dts/sun50i-a64-pine64-plus.dts b/arch/arm/dts/sun50i-a64-pine64-plus.dts
index 790d14daaa..24f1aac366 100644
--- a/arch/arm/dts/sun50i-a64-pine64-plus.dts
+++ b/arch/arm/dts/sun50i-a64-pine64-plus.dts
@@ -46,5 +46,20 @@
model = "Pine64+";
compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";

- /* TODO: Camera, Ethernet PHY, touchscreen, etc. */
+ /* TODO: Camera, touchscreen, etc. */
+};
+
+&emac {
+ pinctrl-names = "default";

+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ status = "okay";
+};

+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {

+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;

+ };
};
diff --git a/arch/arm/dts/sun50i-a64-pine64.dts b/arch/arm/dts/sun50i-a64-pine64.dts
index c680ed385d..604cdaedac 100644
--- a/arch/arm/dts/sun50i-a64-pine64.dts
+++ b/arch/arm/dts/sun50i-a64-pine64.dts
@@ -51,25 +51,37 @@
compatible = "pine64,pine64", "allwinner,sun50i-a64";

aliases {
+ ethernet0 = &emac;
serial0 = &uart0;

+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
};

chosen {
stdout-path = "serial0:115200n8";
};
+};

- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
+&ehci0 {
+ status = "okay";
};

&ehci1 {
status = "okay";
};

+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rmii_pins>;
+ phy-mode = "rmii";
+ phy-handle = <&ext_rmii_phy1>;
+ phy-supply = <&reg_dc1sw>;

+ status = "okay";
+

+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@@ -80,10 +92,17 @@
bias-pull-up;
};

+&mdio {
+ ext_rmii_phy1: ethernet-phy@1 {

+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;

+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
- vmmc-supply = <&reg_vcc3v3>;
+ vmmc-supply = <&reg_dcdc1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
disable-wp;
@@ -91,16 +110,161 @@
status = "okay";
};

+&ohci0 {

+ status = "okay";
+};

+
&ohci1 {
status = "okay";
};

+&r_rsb {

+ status = "okay";
+

+ axp803: pmic@3a3 {
+ compatible = "x-powers,axp803";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp803.dtsi"
+
+&reg_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl";
+};
+
+&reg_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+&reg_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+&reg_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1040000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+/*
+ * The DRAM chips used by Pine64 boards are DDR3L-compatible, so they can
+ * work at 1.35V with less power consumption.
+ * As AXP803 DCDC5 cannot reach 1.35V accurately, use 1.36V instead.
+ */
+&reg_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1360000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vcc-dram";
+};
+
+&reg_dcdc6 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys";
+};
+
+&reg_dldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-hdmi";
+};
+
+&reg_dldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-mipi";
+};
+
+&reg_dldo4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+&reg_eldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "cpvdd";
+};
+
+&reg_fldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-1v2-hsic";
+};
+
+/*
+ * The A64 chip cannot work without this regulator off, although
+ * it seems to be only driving the AR100 core.
+ * Maybe we don't still know well about CPUs domain.
+ */
+&reg_fldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpus";
+};
+
+&reg_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+/* On Exp and Euler connectors */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};

+/* On Wifi/BT connector, with RTS/CTS */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;

+ status = "disabled";
+};
+

+/* On Pi-2 connector */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;

+ status = "disabled";
+};
+

+/* On Euler connector */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;

+ status = "disabled";
+};
+

+/* On Euler connector, RTS/CTS optional */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins>;

+ status = "disabled";
+};
+

&usb_otg {
dr_mode = "host";
status = "okay";
--
2.14.1

[Andre Przywara]

Update the .dts file for the various boards with an Allwinner H5 SoC.

This is as of v4.15-rc9, exactly Linux commit:

commit f88e9301948173dd35afad4a6939092c7f269aed
Author: Sergey Matyukevich <geom...@gmail.com>
Date: Fri Nov 3 22:58:54 2017 +0300
arm64: dts: orange-pi-zero-plus2: fix sdcard detect

Signed-off-by: Andre Przywara <andre.p...@arm.com>
Acked-by: Maxime Ripard <maxime...@bootlin.com>
---

arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts | 105 ++++++++++++++--
arch/arm/dts/sun50i-h5-nanopi-neo2.dts | 89 +++++++++++--
arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 165 +++++++++++++++++++------
arch/arm/dts/sun50i-h5-orangepi-prime.dts | 164 +++++++++++++++++++++---
arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts | 7 +-
5 files changed, 455 insertions(+), 75 deletions(-)

diff --git a/arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts b/arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts
index f1406c224b..7c028af58f 100644
--- a/arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts
+++ b/arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts
@@ -1,18 +1,18 @@
/*
* Copyright (C) 2017 Antony Antony <ant...@phenome.org>

- * Copyright (c) 2016 ARM Ltd.
+ * Copyright (C) 2016 ARM Ltd.

*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual

* licensing only applies to this file, and not this project as a

* whole.
*
- * a) This library is free software; you can redistribute it and/or

+ * a) This file is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public License as

* published by the Free Software Foundation; either version 2 of the

* License, or (at your option) any later version.

*
- * This library is distributed in the hope that it will be useful,

+ * This file is distributed in the hope that it will be useful,

* but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

* GNU General Public License for more details.

@@ -42,13 +42,14 @@
*/

/dts-v1/;
-
#include "sun50i-h5.dtsi"

#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>

/ {
- model = "FriendlyARM NanoPi NEO Plus 2";
+ model = "FriendlyARM NanoPi NEO Plus2";
compatible = "friendlyarm,nanopi-neo-plus2", "allwinner,sun50i-h5";

aliases {
@@ -59,15 +60,76 @@
stdout-path = "serial0:115200n8";
};

+ leds {
+ compatible = "gpio-leds";
+
+ pwr {
+ label = "nanopi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ status {
+ label = "nanopi:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ regulator-name = "gmac-3v3";

+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;

+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ vdd_cpux: gpio-regulator {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ regulator-name = "vdd-cpux";
+ regulator-type = "voltage";
+ regulator-boot-on;

+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;

+ regulator-max-microvolt = <1300000>;
+ regulator-ramp-delay = <50>; /* 4ms */
+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0x1>;
+ states = <1100000 0x0
+ 1300000 0x1>;
+ };
+

+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";

+ pinctrl-names = "default";
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+ post-power-on-delay-ms = <200>;
+ };
};

-&ehci1 {
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";

+ status = "okay";
+};
+

+&ehci0 {
+ status = "okay";

+};
+
+&ehci3 {
status = "okay";
};

@@ -76,11 +138,26 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
- cd-inverted;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
status = "okay";
};

+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_a>;
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;

+ status = "okay";
+

+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";

+ };
+};

+
&mmc2 {
pinctrl-names = "default";

pinctrl-0 = <&mmc2_8bit_pins>;
@@ -91,7 +168,11 @@
status = "okay";
};

-&ohci1 {

+&ohci0 {
+ status = "okay";
+};
+

+&ohci3 {
status = "okay";
};

@@ -101,6 +182,12 @@
status = "okay";
};

+&usb_otg {
+ dr_mode = "host";

+ status = "okay";
+};
+

&usbphy {
+ /* USB Type-A ports' VBUS is always on */
status = "okay";
};
diff --git a/arch/arm/dts/sun50i-h5-nanopi-neo2.dts b/arch/arm/dts/sun50i-h5-nanopi-neo2.dts
index c08af7881b..6eb8092d8e 100644
--- a/arch/arm/dts/sun50i-h5-nanopi-neo2.dts
+++ b/arch/arm/dts/sun50i-h5-nanopi-neo2.dts
@@ -1,18 +1,17 @@
/*
* Copyright (C) 2017 Icenowy Zheng <ice...@aosc.io>

- * Copyright (C) 2017 Jagan Teki <jt...@openedev.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual

* licensing only applies to this file, and not this project as a

* whole.
*
- * a) This library is free software; you can redistribute it and/or

+ * a) This file is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public License as

* published by the Free Software Foundation; either version 2 of the

* License, or (at your option) any later version.

*
- * This library is distributed in the hope that it will be useful,

+ * This file is distributed in the hope that it will be useful,

* but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

* GNU General Public License for more details.

@@ -42,7 +41,6 @@
*/

/dts-v1/;
-
#include "sun50i-h5.dtsi"

#include <dt-bindings/gpio/gpio.h>
@@ -52,6 +50,7 @@
compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5";

aliases {
+ ethernet0 = &emac;
serial0 = &uart0;

};

@@ -59,18 +58,74 @@
stdout-path = "serial0:115200n8";
};

+ leds {
+ compatible = "gpio-leds";
+
+ pwr {
+ label = "nanopi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ status {
+ label = "nanopi:blue:status";
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";

+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;

+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ reg_usb0_vbus: usb0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */

+ status = "okay";
+ };
+};
+

+&ehci0 {
+ status = "okay";

+};
+
+&ehci3 {

+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";

+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";

+ status = "okay";
+};
+

+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
};

&mmc0 {
- compatible = "allwinner,sun50i-h5-mmc",
- "allwinner,sun50i-a64-mmc",
- "allwinner,sun5i-a13-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
@@ -79,8 +134,28 @@

status = "okay";
};

+&ohci0 {
+ status = "okay";
+};
+

+&ohci3 {

+ status = "okay";
+};
+

&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
+

+&usb_otg {
+ dr_mode = "otg";

+ status = "okay";
+};
+

+&usbphy {
+ /* USB Type-A port's VBUS is always on */
+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ usb0_vbus-supply = <&reg_usb0_vbus>;

+ status = "okay";
+};

diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
index d1c347d2b8..a0ca925175 100644
--- a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
+++ b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts

@@ -1,17 +1,17 @@
/*
- * Copyright (c) 2016 ARM Ltd.
+ * Copyright (C) 2016 ARM Ltd.

*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual

* licensing only applies to this file, and not this project as a

* whole.
*
- * a) This library is free software; you can redistribute it and/or

+ * a) This file is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public License as

* published by the Free Software Foundation; either version 2 of the

* License, or (at your option) any later version.

*
- * This library is distributed in the hope that it will be useful,

+ * This file is distributed in the hope that it will be useful,

* but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

* GNU General Public License for more details.

@@ -41,74 +41,108 @@
*/

/dts-v1/;
-
#include "sun50i-h5.dtsi"

#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>

/ {
- model = "OrangePi PC 2";
- compatible = "xunlong,orangepi-pc-2", "allwinner,sun50i-h5";
+ model = "Xunlong Orange Pi PC 2";
+ compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";

+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;

+ };
+
+ aliases {
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ };

chosen {
stdout-path = "serial0:115200n8";
};

- memory {
- reg = <0x40000000 0x40000000>;
- };
+ leds {
+ compatible = "gpio-leds";

- aliases {
- serial0 = &uart0;
- ethernet0 = &emac;
+ pwr {
+ label = "orangepi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ status {
+ label = "orangepi:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ };
};

- soc {

- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;

+ r-gpio-keys {
+ compatible = "gpio-keys";
+
+ sw4 {
+ label = "sw4";
+ linux,code = <BTN_0>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
};
};
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";

+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;

+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_usb0_vbus: usb0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */

+ status = "okay";
+ };

};

-&mmc0 {
- compatible = "allwinner,sun50i-h5-mmc",
- "allwinner,sun50i-a64-mmc",
- "allwinner,sun5i-a13-mmc";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
- vmmc-supply = <&reg_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
- cd-inverted;
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
status = "okay";
};

-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+&ehci0 {
status = "okay";
};

-&usbphy {
+&ehci1 {
status = "okay";
};

-&ohci1 {
+&ehci2 {
status = "okay";
};

-&ehci1 {
+&ehci3 {
status = "okay";
};

&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
- phy-mode = "rgmii";
+ phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
status = "okay";
};

@@ -118,3 +152,64 @@
reg = <1>;
};
};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;

+ status = "okay";
+};
+

+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

+ status = "okay";
+};
+

+&ohci0 {
+ status = "okay";
+};
+

+&ohci1 {
+ status = "okay";
+};
+

+&ohci2 {

+ status = "okay";
+};
+

+&ohci3 {

+ status = "okay";
+};
+

+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;

+ status = "okay";
+};
+

+&uart1 {
+ pinctrl-names = "default";

+ pinctrl-0 = <&uart1_pins>;

+ status = "disabled";
+};
+

+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "disabled";
+};
+

+&usb_otg {
+ dr_mode = "otg";

+ status = "okay";
+};
+

+&usbphy {
+ /* USB Type-A ports' VBUS is always on */
+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ usb0_vbus-supply = <&reg_usb0_vbus>;

+ status = "okay";
+};

diff --git a/arch/arm/dts/sun50i-h5-orangepi-prime.dts b/arch/arm/dts/sun50i-h5-orangepi-prime.dts
index d4577dfae1..b477906501 100644
--- a/arch/arm/dts/sun50i-h5-orangepi-prime.dts
+++ b/arch/arm/dts/sun50i-h5-orangepi-prime.dts
@@ -1,17 +1,20 @@
/*

- * Copyright (C) 2017 Jagan Teki <jt...@openedev.com>

+ * Copyright (C) 2017 Icenowy Zheng <ice...@aosc.xyz>
+ *
+ * Based on sun50i-h5-orangepi-pc2.dts, which is:

+ * Copyright (C) 2016 ARM Ltd.

*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual

* licensing only applies to this file, and not this project as a

* whole.
*
- * a) This library is free software; you can redistribute it and/or

+ * a) This file is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public License as

* published by the Free Software Foundation; either version 2 of the

* License, or (at your option) any later version.

*
- * This library is distributed in the hope that it will be useful,

+ * This file is distributed in the hope that it will be useful,

* but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

* GNU General Public License for more details.

@@ -41,16 +44,17 @@
*/

/dts-v1/;
-
#include "sun50i-h5.dtsi"

#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>

/ {
- model = "OrangePi Prime";
+ model = "Xunlong Orange Pi Prime";
compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5";

aliases {
+ ethernet0 = &emac;
serial0 = &uart0;

};

@@ -58,34 +62,130 @@
stdout-path = "serial0:115200n8";
};

- memory {
- reg = <0x40000000 0x80000000>;
+ leds {
+ compatible = "gpio-leds";
+
+ pwr {
+ label = "orangepi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ status {
+ label = "orangepi:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ };
};

- soc {

- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;

+ r-gpio-keys {
+ compatible = "gpio-keys";
+
+ sw4 {
+ label = "sw4";
+ linux,code = <BTN_0>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
};
};
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";

+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;

+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";

+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;

+ };
+
+ reg_usb0_vbus: usb0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */

+ status = "okay";
+ };
+

+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";

+ reset-gpios = <&pio 2 14 GPIO_ACTIVE_LOW>; /* PC14 */
+ };
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";

+ status = "okay";
+};
+

+&ehci0 {
+ status = "okay";
};

&ehci1 {
status = "okay";
};

+&ehci2 {

+ status = "okay";
+};
+

+&ehci3 {

+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";

+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";

+ status = "okay";
+};
+

+&external_mdio {

+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+

+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;

+ status = "okay";
+};
+

&mmc0 {
- compatible = "allwinner,sun50i-h5-mmc",
- "allwinner,sun50i-a64-mmc",
- "allwinner,sun5i-a13-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
- cd-inverted;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

+ status = "okay";
+};
+

+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_a>;
+ vmmc-supply = <&reg_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;

+ status = "okay";
+};
+

+&ohci0 {
status = "okay";
};

@@ -93,12 +193,40 @@
status = "okay";
};

+&ohci2 {

+ status = "okay";
+};
+

+&ohci3 {

+ status = "okay";
+};
+

&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};

+&uart1 {
+ pinctrl-names = "default";

+ pinctrl-0 = <&uart1_pins>;

+ status = "disabled";
+};
+

+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "disabled";
+};
+

+&usb_otg {
+ dr_mode = "otg";

+ status = "okay";
+};
+

&usbphy {
+ /* USB Type-A ports' VBUS is always on */
+ usb0_id_det-gpios = <&pio 0 21 GPIO_ACTIVE_HIGH>; /* PA21 */
+ usb0_vbus-supply = <&reg_usb0_vbus>;
status = "okay";
};
diff --git a/arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts b/arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts
index 3f4baba310..a42fd79a62 100644
--- a/arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts
+++ b/arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts
@@ -46,7 +46,6 @@

#include <dt-bindings/gpio/gpio.h>

-
/ {
model = "OrangePi Zero Plus2";
compatible = "xunlong,orangepi-zero-plus2", "allwinner,sun50i-h5";
@@ -68,15 +67,11 @@
};

&mmc0 {
- compatible = "allwinner,sun50i-h5-mmc",
- "allwinner,sun50i-a64-mmc",
- "allwinner,sun5i-a13-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
- cd-inverted;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;

[Andre Przywara]

Update the .dts file for the various boards with an Allwinner H3 SoC.

This is as of v4.15-rc9, exactly Linux commit:

commit 4904337fe34fa7fc529d6f4d9ee8b96fe7db310a
Author: Corentin Labbe <clabbe....@gmail.com>
Date: Tue Oct 31 09:19:12 2017 +0100
ARM: dts: sunxi: Restore EMAC changes (boards)

Signed-off-by: Andre Przywara <andre.p...@arm.com>
Acked-by: Maxime Ripard <maxime...@bootlin.com>
---

arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts | 76 +++++++++++++++++----------
arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts | 71 +++++++++++++++++++++++++
arch/arm/dts/sun8i-h3-nanopi-m1.dts | 6 +++
arch/arm/dts/sun8i-h3-nanopi-neo-air.dts | 1 -
arch/arm/dts/sun8i-h3-orangepi-2.dts | 60 ++++++++++++---------
arch/arm/dts/sun8i-h3-orangepi-lite.dts | 25 ++++-----
arch/arm/dts/sun8i-h3-orangepi-one.dts | 65 +++++++++++++++++------
arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts | 9 +++-
arch/arm/dts/sun8i-h3-orangepi-pc.dts | 83 ++++++++++++++++++++++--------
arch/arm/dts/sun8i-h3-orangepi-plus.dts | 29 +++++------
arch/arm/dts/sun8i-h3-orangepi-plus2e.dts | 15 +-----
11 files changed, 302 insertions(+), 138 deletions(-)

diff --git a/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts
index 06fddaae8e..f2292deaa5 100644
--- a/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -46,13 +46,13 @@

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>

/ {
model = "Banana Pi BPI-M2-Plus";
compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";

aliases {
+ ethernet0 = &emac;
serial0 = &uart0;

serial1 = &uart1;
};
@@ -64,7 +64,6 @@
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
- pinctrl-0 = <&pwr_led_bpi_m2p>;

pwr_led {
label = "bananapi-m2-plus:red:pwr";
@@ -76,7 +75,6 @@
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
- pinctrl-0 = <&sw_r_bpi_m2p>;

sw4 {
label = "power";
@@ -85,14 +83,27 @@
};
};

+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+

wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
- pinctrl-0 = <&wifi_en_bpi_m2p>;

reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */

};
};

+&ehci0 {
+ status = "okay";
+};
+

&ehci1 {
status = "okay";
};
@@ -101,6 +112,24 @@
status = "okay";
};

+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+

+ allwinner,leds-active-low;

+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";

+ reg = <0>;
+ };
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
@@ -127,7 +156,7 @@
non-removable;
status = "okay";

- brcmf: bcrmf@1 {
+ brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&pio>;
@@ -146,6 +175,10 @@

status = "okay";
};

+&ohci0 {
+ status = "okay";
+};
+

&ohci1 {
status = "okay";
};
@@ -154,27 +187,9 @@
status = "okay";
};

-&r_pio {
- pwr_led_bpi_m2p: led_pins@0 {
- allwinner,pins = "PL10";
- allwinner,function = "gpio_out";

- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-

- sw_r_bpi_m2p: key_pins@0 {
- allwinner,pins = "PL3";

- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;

- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- wifi_en_bpi_m2p: wifi_en_pin {
- allwinner,pins = "PL7";
- allwinner,function = "gpio_out";

- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };

+&reg_usb0_vbus {
+ gpio = <&pio 3 11 GPIO_ACTIVE_HIGH>; /* PD11 */
+ status = "okay";
};

&uart0 {
@@ -189,7 +204,14 @@
status = "okay";
};

+&usb_otg {

+ dr_mode = "otg";
+ status = "okay";
+};
+
&usbphy {

- /* USB VBUS is on as long as VCC-IO is on */
+ usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+ usb0_vbus-supply = <&reg_usb0_vbus>;
+ /* USB host VBUS is on as long as VCC-IO is on */
status = "okay";
};
diff --git a/arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts
index 8ddd1b2cc0..0a8b79cf59 100644
--- a/arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts
+++ b/arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts
@@ -45,6 +45,27 @@
/ {
model = "FriendlyArm NanoPi M1 Plus";
compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3";
+
+ aliases {
+ serial1 = &uart3;
+ ethernet1 = &sdio_wifi;

+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+

+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */

+ };
};

&ehci1 {
@@ -55,6 +76,50 @@
status = "okay";
};

+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+

+ allwinner,leds-active-low;
+

+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";

+ reg = <7>;

+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+};
+

+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_a>;
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+

+ sdio_wifi: sdio_wifi@1 {

+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";

+ interrupt-parent = <&pio>;
+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */

+ interrupt-names = "host-wake";
+ };

+};
+
&ohci1 {
status = "okay";
};

@@ -62,3 +127,9 @@
&ohci2 {
status = "okay";
};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>;

+ status = "okay";
+};

diff --git a/arch/arm/dts/sun8i-h3-nanopi-m1.dts b/arch/arm/dts/sun8i-h3-nanopi-m1.dts
index ec63d104b4..3a2ccdb28a 100644
--- a/arch/arm/dts/sun8i-h3-nanopi-m1.dts
+++ b/arch/arm/dts/sun8i-h3-nanopi-m1.dts
@@ -55,6 +55,12 @@
status = "okay";
};

+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+};
+

&ohci1 {
status = "okay";
};
diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts
index 3ba081c1f5..03ff6f8b93 100644
--- a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts
+++ b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts
@@ -45,7 +45,6 @@
#include "sunxi-common-regulators.dtsi"

#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>

/ {
model = "FriendlyARM NanoPi NEO Air";
diff --git a/arch/arm/dts/sun8i-h3-orangepi-2.dts b/arch/arm/dts/sun8i-h3-orangepi-2.dts
index d97fdacb35..b20be95b49 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-2.dts

@@ -46,7 +46,6 @@

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>

/ {
model = "Xunlong Orange Pi 2";
@@ -106,6 +105,15 @@
};
};

+&codec {
+ allwinner,pa-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */
+ allwinner,audio-routing =
+ "Speaker", "LINEOUT",

+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+

&ehci1 {
status = "okay";
};
@@ -152,34 +160,26 @@
};

&pio {
- leds_opc: led_pins@0 {
- allwinner,pins = "PA15";
- allwinner,function = "gpio_out";

- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

+ leds_opc: led_pins {
+ pins = "PA15";
+ function = "gpio_out";
};
};

&r_pio {
- leds_r_opc: led_pins@0 {
- allwinner,pins = "PL10";
- allwinner,function = "gpio_out";

- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

+ leds_r_opc: led_pins {
+ pins = "PL10";
+ function = "gpio_out";
};

- sw_r_opc: key_pins@0 {
- allwinner,pins = "PL3", "PL4";

- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;

- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ sw_r_opc: key_pins {
+ pins = "PL3", "PL4";
+ function = "gpio_in";
};

- wifi_pwrseq_pin_orangepi: wifi_pwrseq_pin@0 {
- allwinner,pins = "PL7";
- allwinner,function = "gpio_out";

- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

+ wifi_pwrseq_pin_orangepi: wifi_pwrseq_pin {
+ pins = "PL7";
+ function = "gpio_out";
};
};

@@ -194,8 +194,22 @@
status = "okay";
};

-&usb1_vbus_pin_a {
- allwinner,pins = "PG13";

+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "disabled";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "disabled";
+};
+

+&uart3 {
+ pinctrl-names = "default";

+ pinctrl-0 = <&uart3_pins>;
+ status = "disabled";

};

&usbphy {
diff --git a/arch/arm/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/dts/sun8i-h3-orangepi-lite.dts
index 1550fee1ec..a70a1daf4e 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-lite.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-lite.dts

@@ -46,7 +46,6 @@

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>

/ {
model = "Xunlong Orange Pi Lite";
@@ -142,27 +141,21 @@
};

&pio {
- leds_opc: led_pins@0 {
- allwinner,pins = "PA15";
- allwinner,function = "gpio_out";

- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

+ leds_opc: led_pins {
+ pins = "PA15";
+ function = "gpio_out";
};
};

&r_pio {
- leds_r_opc: led_pins@0 {
- allwinner,pins = "PL10";
- allwinner,function = "gpio_out";

- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

+ leds_r_opc: led_pins {
+ pins = "PL10";
+ function = "gpio_out";
};

- sw_r_opc: key_pins@0 {
- allwinner,pins = "PL3";

- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;

- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ sw_r_opc: key_pins {
+ pins = "PL3";
+ function = "gpio_in";
};
};

diff --git a/arch/arm/dts/sun8i-h3-orangepi-one.dts b/arch/arm/dts/sun8i-h3-orangepi-one.dts
index adab1cbfc9..82e5d28cd6 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-one.dts

@@ -46,7 +46,6 @@

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>

/ {
model = "Xunlong Orange Pi One";
@@ -91,6 +90,10 @@
};
};

+&ehci0 {
+ status = "okay";
+};
+

&ehci1 {
status = "okay";
};
@@ -112,42 +115,70 @@

status = "okay";
};

+&ohci0 {
+ status = "okay";
+};
+

&ohci1 {
status = "okay";
};

&pio {
- leds_opc: led_pins@0 {
- allwinner,pins = "PA15";
- allwinner,function = "gpio_out";

- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

+ leds_opc: led_pins {
+ pins = "PA15";
+ function = "gpio_out";
};
};

&r_pio {
- leds_r_opc: led_pins@0 {
- allwinner,pins = "PL10";
- allwinner,function = "gpio_out";

- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

+ leds_r_opc: led_pins {
+ pins = "PL10";
+ function = "gpio_out";
};

- sw_r_opc: key_pins@0 {
- allwinner,pins = "PL3";

- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;

- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ sw_r_opc: key_pins {
+ pins = "PL3";
+ function = "gpio_in";
};
};

+&reg_usb0_vbus {

+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
+ status = "okay";
+};
+

&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};

+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "disabled";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "disabled";
+};
+

+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;

+ status = "disabled";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
&usbphy {

- /* USB VBUS is always on */

+ /* USB Type-A port's VBUS is always on */
+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ usb0_vbus-supply = <&reg_usb0_vbus>;

status = "okay";
};
diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts
index 851fd2c2cc..a10281b455 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts
@@ -53,6 +53,11 @@
};
};

+&emac {
+ /* LEDs changed to active high on the plus */
+ /delete-property/ allwinner,leds-active-low;
+};
+
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>;
@@ -82,7 +87,7 @@

&mmc2_8bit_pins {
/* Increase drive strength for DDR modes */
- allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+ drive-strength = <40>;
/* eMMC is missing pull-ups */
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ bias-pull-up;
};
diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/dts/sun8i-h3-orangepi-pc.dts
index afba264ea5..d22546df1b 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-pc.dts

@@ -46,7 +46,6 @@

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>

/ {
model = "Xunlong Orange Pi PC";
@@ -91,6 +90,18 @@
};
};

+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+

&ehci1 {
status = "okay";
};
@@ -103,6 +114,13 @@
status = "okay";
};

+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;

+ status = "okay";
+};
+

&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
@@ -119,6 +137,10 @@

status = "okay";
};

+&ohci0 {
+ status = "okay";
+};
+

&ohci1 {
status = "okay";
};
@@ -132,44 +154,61 @@
};

&pio {
- leds_opc: led_pins@0 {
- allwinner,pins = "PA15";
- allwinner,function = "gpio_out";

- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

+ leds_opc: led_pins {
+ pins = "PA15";
+ function = "gpio_out";
};
};

&r_pio {
- leds_r_opc: led_pins@0 {
- allwinner,pins = "PL10";
- allwinner,function = "gpio_out";

- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

+ leds_r_opc: led_pins {
+ pins = "PL10";
+ function = "gpio_out";
};

- sw_r_opc: key_pins@0 {
- allwinner,pins = "PL3";

- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;

- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ sw_r_opc: key_pins {
+ pins = "PL3";
+ function = "gpio_in";
};
};

+&reg_usb0_vbus {

+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
+ status = "okay";
+};
+

&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};

-&usbphy {
- /* USB VBUS is always on */

+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "disabled";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "disabled";
+};
+

+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;

+ status = "disabled";
+};
+
+&usb_otg {
+ dr_mode = "otg";

status = "okay";
};

-&emac {
- phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
- allwinner,leds-active-low;
+&usbphy {

+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ usb0_vbus-supply = <&reg_usb0_vbus>;

+ /* VBUS on USB host ports are always on */
status = "okay";
};
diff --git a/arch/arm/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/dts/sun8i-h3-orangepi-plus.dts
index 136e4414a4..b403e5d787 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-plus.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-plus.dts
@@ -47,10 +47,12 @@
model = "Xunlong Orange Pi Plus / Plus 2";
compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";

+ aliases {
+ ethernet0 = &emac;

+ };
+
reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac_power_pin_orangepi>;
regulator-name = "gmac-3v3";

regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;

@@ -77,11 +79,13 @@
};

&emac {
- /* The Orange Pi Plus uses an external phy */

pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;

phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;

phy-mode = "rgmii";
+
+ status = "okay";
};

&external_mdio {
@@ -103,24 +107,15 @@

&mmc2_8bit_pins {
/* Increase drive strength for DDR modes */
- allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+ drive-strength = <40>;
/* eMMC is missing pull-ups */
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ bias-pull-up;
};

&pio {
- gmac_power_pin_orangepi: gmac_power_pin@0 {
- allwinner,pins = "PD6";
- allwinner,function = "gpio_out";

- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-

- usb3_vbus_pin_a: usb3_vbus_pin@0 {
- allwinner,pins = "PG11";
- allwinner,function = "gpio_out";

- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

+ usb3_vbus_pin_a: usb3_vbus_pin {
+ pins = "PG11";
+ function = "gpio_out";
};
};

diff --git a/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts
index 51aaf49b6d..6dbf7b2e0c 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts
@@ -53,24 +53,22 @@

reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac_power_pin_orangepi>;
regulator-name = "gmac-3v3";

regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;

startup-delay-us = <100000>;
enable-active-high;
- gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
};
};

&emac {
- /* The Orange Pi Plus 2E uses an external gbit phy */

pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;

phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;

phy-mode = "rgmii";
+ status = "okay";

};

&external_mdio {
@@ -79,12 +77,3 @@
reg = <1>;
};
};
-
-&pio {
- gmac_power_pin_orangepi: gmac_power_pin@0 {
- allwinner,pins = "PD6";
- allwinner,function = "gpio_out";

- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };

-};
--
2.14.1

[Andre Przywara]

Update the board DT file to match the updated h3.dtsi base.
This file is not (yet?) in Linux, so we can't update from there
directly.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
Acked-by: Maxime Ripard <maxime...@bootlin.com>
---

arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts | 8 ++++++++
1 file changed, 8 insertions(+)

diff --git a/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts b/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts
index c8fd69f0a4..cb3ecddb33 100644
--- a/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts
+++ b/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts
@@ -112,6 +112,10 @@

};
};

+&ehci0 {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};

@@ -147,6 +151,10 @@

status = "okay";
};

+&ohci0 {
+ status = "okay";
+};
+
&ohci1 {
status = "okay";
};

--
2.14.1

[Andre Przywara]

Update the .dts file for the OrangePi Zero board, using the H2+ SoC.

This is as of v4.15-rc9, exactly Linux commit:
commit 4904337fe34fa7fc529d6f4d9ee8b96fe7db310a
Author: Corentin Labbe <clabbe....@gmail.com>
Date: Tue Oct 31 09:19:12 2017 +0100
ARM: dts: sunxi: Restore EMAC changes (boards)

Signed-off-by: Andre Przywara <andre.p...@arm.com>
Acked-by: Maxime Ripard <maxime...@bootlin.com>
---

arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts | 52 ++++++++++++++++++++++++++--
1 file changed, 50 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
index e0efcb3ba3..6713d0f2b3 100644
--- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -49,7 +49,6 @@

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>

/ {

model = "Xunlong Orange Pi Zero";
@@ -58,6 +57,7 @@
aliases {

serial0 = &uart0;
/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+ ethernet0 = &emac;

ethernet1 = &xr819;
};

@@ -92,9 +92,14 @@

wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";

reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>;

+ post-power-on-delay-ms = <200>;

};
};

+&ehci0 {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};

@@ -134,17 +139,60 @@
};
};

+&mmc1_pins_a {
+ bias-pull-up;
+};
+

+&ohci0 {
+ status = "okay";
+};
+
&ohci1 {
status = "okay";
};

+&spi0 {
+ /* Disable SPI NOR by default: it optional on Orange Pi Zero boards */

+ status = "disabled";
+

+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mxicy,mx25l1606e", "winbond,w25q128";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };

+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};

+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "disabled";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "disabled";
+};
+

+&usb_otg {
+ dr_mode = "peripheral";

+ status = "okay";
+};
+

&usbphy {
- /* USB VBUS is always on */
+ /*

+ * USB Type-A port VBUS is always on. However, MicroUSB VBUS can only
+ * power up the board; when it's used as OTG port, this VBUS is
+ * always off even if the board is powered via GPIO pins.
+ */
status = "okay";

+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */

};
--
2.14.1

[Andre Przywara]

When the defconfig for the SoPine baseboard was added, there wasn't any
proper DT for the board yet, so we used the Pine64 DT as a placeholder.
Copy the DT file(s) meanwhile added in Linux over to U-Boot, and use
them in our defconfig.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
Acked-by: Maxime Ripard <maxime...@bootlin.com>
---

arch/arm/dts/Makefile | 3 +-
arch/arm/dts/sun50i-a64-sopine-baseboard.dts | 150 +++++++++++++++++++++++++++
arch/arm/dts/sun50i-a64-sopine.dtsi | 142 +++++++++++++++++++++++++
configs/sopine_baseboard_defconfig | 2 +-
4 files changed, 295 insertions(+), 2 deletions(-)

create mode 100644 arch/arm/dts/sun50i-a64-sopine-baseboard.dts
create mode 100644 arch/arm/dts/sun50i-a64-sopine.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 20a4c37d48..b947cbcc59 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -368,7 +368,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-olinuxino.dtb \
sun50i-a64-orangepi-win.dtb \
sun50i-a64-pine64-plus.dtb \
- sun50i-a64-pine64.dtb
+ sun50i-a64-pine64.dtb \
+ sun50i-a64-sopine-baseboard.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb \
diff --git a/arch/arm/dts/sun50i-a64-sopine-baseboard.dts b/arch/arm/dts/sun50i-a64-sopine-baseboard.dts
new file mode 100644
index 0000000000..abe179de35
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-sopine-baseboard.dts

@@ -0,0 +1,150 @@
+/*

+ * Copyright (c) 2017 Icenowy Zheng <ice...@aosc.xyz>
+ *
+ * Based on sun50i-a64-pine64.dts, which is:
+ * Copyright (c) 2016 ARM Ltd.
+ *

+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *

+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,

+/dts-v1/;
+
+#include "sun50i-a64-sopine.dtsi"
+
+/ {
+ model = "SoPine with baseboard";
+ compatible = "pine64,sopine-baseboard", "pine64,sopine",
+ "allwinner,sun50i-a64";
+

+ aliases {
+ ethernet0 = &emac;

+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc1v8: vcc1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8";

+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;

+ };
+};
+

+&ehci0 {
+ status = "okay";
+};
+

+&ehci1 {

+ status = "okay";
+};
+

+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";

+ phy-handle = <&ext_rgmii_phy>;
+ phy-supply = <&reg_dc1sw>;

+ status = "okay";
+};
+

+&mdio {

+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";

+ reg = <1>;
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <&reg_dcdc1>;
+ vqmmc-supply = <&reg_vcc1v8>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;

+ status = "okay";
+};
+

+&ohci0 {
+ status = "okay";
+};
+

+&ohci1 {

+ status = "okay";
+};
+

+&reg_dc1sw {
+ regulator-name = "vcc-phy";
+};
+

+&reg_dldo1 {

+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;

+ regulator-name = "vcc-hdmi";
+};
+
+&reg_dldo2 {

+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;

+ regulator-name = "vcc-mipi";
+};
+
+&reg_dldo4 {

+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;

+ regulator-name = "vcc-wifi";
+};
+

+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;

+ status = "okay";
+};
+

+&usb_otg {
+ dr_mode = "host";

+ status = "okay";
+};
+

+&usbphy {

+ status = "okay";
+};

diff --git a/arch/arm/dts/sun50i-a64-sopine.dtsi b/arch/arm/dts/sun50i-a64-sopine.dtsi
new file mode 100644
index 0000000000..43418bd881
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-sopine.dtsi
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2017 Icenowy Zheng <ice...@aosc.xyz>
+ *
+ * Based on sun50i-a64-pine64.dts, which is:
+ * Copyright (c) 2016 ARM Ltd.
+ *

+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *

+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,

+#include "sun50i-a64.dtsi"
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_dcdc1>;
+ non-removable;
+ disable-wp;
+ bus-width = <4>;

+ status = "okay";
+};
+

+&r_rsb {

+ status = "okay";
+

+ axp803: pmic@3a3 {
+ compatible = "x-powers,axp803";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp803.dtsi"
+
+&reg_aldo2 {

+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;

+ regulator-name = "vcc-pl";
+};
+
+&reg_aldo3 {

+ regulator-always-on;

+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dcdc1 {
+ regulator-always-on;

+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;

+ regulator-name = "vcc-3v3";
+};
+
+&reg_dcdc2 {

+ regulator-always-on;
+ regulator-min-microvolt = <1040000>;
+ regulator-max-microvolt = <1300000>;

+ regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+&reg_dcdc5 {

+ regulator-always-on;

+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;

+ regulator-name = "vcc-dram";
+};
+
+&reg_dcdc6 {

+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;

+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys";
+};
+

+&reg_eldo1 {
+ regulator-always-on;

+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;

+ regulator-name = "vdd-1v8-lpddr";

+};
+
+&reg_fldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-1v2-hsic";
+};
+
+/*
+ * The A64 chip cannot work without this regulator off, although
+ * it seems to be only driving the AR100 core.
+ * Maybe we don't still know well about CPUs domain.
+ */
+&reg_fldo2 {

+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;

+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpus";
+};
+
+&reg_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};

diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig
index 8ca43a6eac..cba392fb6c 100644
--- a/configs/sopine_baseboard_defconfig
+++ b/configs/sopine_baseboard_defconfig
@@ -9,7 +9,7 @@ CONFIG_DRAM_ZQ=3881949
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC0_CD_PIN=""
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-sopine-baseboard"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
--
2.14.1

[Jagan Teki]

On Wed, Mar 14, 2018 at 7:26 AM, Andre Przywara <andre.p...@arm.com> wrote:
> As we are running into issues where the final U-Boot FIT image file is
> exceeding our size limit, add a hint to the README.sunxi64 file
> to point out the possibility of building non-debug versions of the ATF
> binary. These are about 12KB smaller than the standard debug build, and
> so allow successful U-Boot builds for many boards with the Allwinner H5
> SoC.
> Please note that under normal circumstances the debug build is still
> recommended, as it gives valuable clues in case something goes wrong in
> the ATF.
>
> Signed-off-by: Andre Przywara <andre.p...@arm.com>
> Acked-by: Maxime Ripard <maxime...@bootlin.com>
> ---
> board/sunxi/README.sunxi64 | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/board/sunxi/README.sunxi64 b/board/sunxi/README.sunxi64
> index 5a363d27b8..df1dbc818f 100644
> --- a/board/sunxi/README.sunxi64
> +++ b/board/sunxi/README.sunxi64
> @@ -38,6 +38,12 @@ the root of your U-Boot build directory (or create a symbolic link).
> $ export BL31=/src/arm-trusted-firmware/build/sun50iw1p1/debug/bl31.bin
> (adjust the actual path accordingly)
>
> +If you run into size issues with the resulting U-Boot image file, it might
> +help to use a release build, by using "DEBUG=0" when building bl31.bin.

I thought I've commented this in previous version patch, w/o DEBUG=0
can also build release right? like

make PLAT=sun50iw1p1 bl31

[André Przywara]

Hi,

Yes, DEBUG=0 is the (current) default in the Makefile. But what's the
question? The original recipe said DEBUG=1, so stating DEBUG=0 makes it
obvious what to change. Given that with DEBUG not defined to 1, ATF is
*completely* silent, I would very much like to encourage people to use
DEBUG builds, and just suggesting DEBUG=0 as a workaround.

Cheers,
Andre.

[Jagan Teki]

My question is without mentioning any DEBUG just build like this

make PLAT=sun50iw1p1 bl31

will be similar to

make PLAT=sun50iw1p1 DEBUG=0 bl31

right?

[André Przywara]

Yes, that's what I said above. The Makefile in the ATF root directory
sets DEBUG to 0, if not overridden on the make command line.

Cheers,
Andre.

[Jagan Teki]

These AXP regulator stuff need to wait until the relevant driver
supported through dt otherwise moving to DM_MMC might fail to get the
regulator? [1]

[1] https://patchwork.ozlabs.org/patch/887405/

Jagan.

[André Przywara]

On 23/03/18 18:14, Jagan Teki wrote:
> On Wed, Mar 14, 2018 at 7:27 AM, Andre Przywara <andre.p...@arm.com> wrote:
>> Update the .dts files for the various boards with an Allwinner A64 SoC.
>> This is as of v4.15-rc9, exactly Linux commit:

....

>>
>> &mmc2 {
>> pinctrl-names = "default";
>> pinctrl-0 = <&mmc2_pins>;
>> - vmmc-supply = <&reg_vcc3v3>;
>> + vmmc-supply = <&reg_dcdc1>;
>
> These AXP regulator stuff need to wait until the relevant driver
> supported through dt

Well, we could take the two patches I had in v3 that revert this change.
As mentioned before, DCDC1 is an always-on regulator anyways.

But actually that's not our problem, as we don't define DM_REGULATORS,
so we will never parse those properties.

Instead:

> otherwise moving to DM_MMC might fail to get the
> regulator? [1]
> [1] https://patchwork.ozlabs.org/patch/887405/

Ah, thanks for the link, I totally missed that.
So as Heinrich rightfully feared in his first patch, this change - for
all sunxi boards - breaks most of them: The DM-MMC part of the sunxi MMC
driver is not ready for any other SoC than the A20:
a) The only compatible string it knows is "allwinner,sun5i-a13-mmc".
b) It assumes the old style clocks, even without checking if the
referenced nodes are compatible.

So while a) is trivial to fix (U-Boot probably does not need to care
about the differences in the MMC controllers of the different SoCs), b)
is more of a beast.
I started looking into an easy implementation of the new clocks,
basically just enough to get MMC going, for the H3/H5 and A64. This
could be extended for other clocks once we need them.
But I am afraid this is not 2018.05 material anymore.

So what do we do here?

1) Just switch over A20? The A20 DTs in U-Boot use the old-style clocks
still, so that's fine. And we postpone the DM-MMC switch for the rest
until we have some DM new-style clock driver?
2) Push forward on some simple sunxi-ng MMC clock driver?
3) Don't use DM_MMC at all?

Would love to here other's opinions.

Cheers,
Andre.

[Andre Przywara]

Hi Maxime,

thanks for the answer.

On 27/03/18 15:30, Maxime Ripard wrote:
> Hi,

> I'm not sure I'd like to do that to be honest, this sounds like
> something that will never happen.

>
>> 2) Push forward on some simple sunxi-ng MMC clock driver?
>

> That one would work for me

>
>> 3) Don't use DM_MMC at all?
>

> Given the warning that was set for the next release, I'm not sure we
> have much choice unfortunately.

OK. So meanwhile I have something almost(TM) working:
- drivers/clk/sunxi/clk-a64.c, which is a UCLASS_CLK implementation of
the clock IDs from allwinner,sun50i-a64-ccu that we need: CLK_BUS_UARTx,
CLK_BUS_MMCx, CLK_MMCx. Their implementation is fairly simple, actually
(I did it the U-Boot way, not pulling in any super-fancy Linux code).
Porting this over to H3/H5 and other SoCs should be trivial: copy/paste
for now. We can look at how to unify this later.
- drivers/mmc/sunxi_mmc.c extended to use UCLASS_CLK clocks. This is
also not too bad, but I seem to miss a bit in here, as it times out.
Will debug this tonight.
- Cowardly dodging a proper UCLASS_RESET driver for now, instead hacking
the single bit in :-(

That looks tight to still get into this merge window, though, at least
if we follow the usual process.

Keep you posted.

Cheers,
Andre.

[Jagan Teki]

I did this missing DM work like pinctrl, reset and clk and unable to
send because of size issues. which was with v2017.03.

I'm thinking DM_MMC should wait till the driver should have support of
these feature with all family SOC's

Jagan.

--
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

[Jagan Teki]

On Sat, Mar 24, 2018 at 6:37 AM, André Przywara <andre.p...@arm.com> wrote:
> On 23/03/18 18:14, Jagan Teki wrote:
>> On Wed, Mar 14, 2018 at 7:27 AM, Andre Przywara <andre.p...@arm.com> wrote:
>>> Update the .dts files for the various boards with an Allwinner A64 SoC.
>>> This is as of v4.15-rc9, exactly Linux commit:
>
> ....
>
>>>
>>> &mmc2 {
>>> pinctrl-names = "default";
>>> pinctrl-0 = <&mmc2_pins>;
>>> - vmmc-supply = <&reg_vcc3v3>;
>>> + vmmc-supply = <&reg_dcdc1>;
>>
>> These AXP regulator stuff need to wait until the relevant driver
>> supported through dt
>
> Well, we could take the two patches I had in v3 that revert this change.
> As mentioned before, DCDC1 is an always-on regulator anyways.

May it's good option to look at v3 changes, since DM_MMC Migration
expires in coming release, dt changes which are related to MMC we can
wait for proper supported feature get IN(like pinctrl, clock, reset),
that means we should anyway need to move DM_MMC but with working dt
changes.

The big question for me here is about SPL, I'm sure we can get the
size issues. May be we try platdata but in any case we need to enable
DM ie increase the size (atleast for A64, H5)

Jagan.

[André Przywara]

So my understanding is that those DM_<SUBSYS> defines are just for
U-Boot proper, and the SPL needs extra symbols to be also "DMed".
See the definition of CONFIG_IS_ENABLED().
So by just #defining CONFIG_DM_MMC the SPL still looks the same (using
the non-DM code), and indeed I don't run into size issues with the SPL.

Given the uniformity of at least the MMC device in sunxi, I think in the
medium term we get away with some simple platdata, without pulling the
DT into SPL. The clocks might be a bit more hairy here, though. But
that's nothing for *now* to solve.

Just getting cheeky and wonder if we actually need to touch the clocks
since the boot ROM has actually done all this work already (since we
always load from the same media as the boot ROOM).

Cheers,
Andre.

[Jagan Teki]

I don't think so, Idea about migrating to BLK, DM_MMC should remove
#ifdef code with DM vs non-DM such that the driver should have DM
version with DT along with PLATDATA

> See the definition of CONFIG_IS_ENABLED().
> So by just #defining CONFIG_DM_MMC the SPL still looks the same (using
> the non-DM code), and indeed I don't run into size issues with the SPL.

Even to use DM_MMC in SPL we should enable SPL_DM so I'm unable to
build SPL even with SPL_DM=y

SPL build, with SPL_DM_, SPL_DM_MMC, SPL_OF_PLATDATA

aarch64-linux-gnu-ld.bfd: address 0x18d18 of u-boot-spl section
`.text' is not within region `.sram'
aarch64-linux-gnu-ld.bfd: u-boot-spl section `.rodata' will not fit in
region `.sram'
aarch64-linux-gnu-ld.bfd: address 0x18d18 of u-boot-spl section
`.text' is not within region `.sram'
aarch64-linux-gnu-ld.bfd: address 0x18d18 of u-boot-spl section
`.text' is not within region `.sram'
aarch64-linux-gnu-ld.bfd: region `.sram' overflowed by 11104 bytes

>
> Given the uniformity of at least the MMC device in sunxi, I think in the
> medium term we get away with some simple platdata, without pulling the
> DT into SPL. The clocks might be a bit more hairy here, though. But
> that's nothing for *now* to solve.

platdata available only for SPL, not for U-Boot proper.

I agree that clock might be more hairy for now. and we can go with DT
for U-Boot proper and just grab the minimum properties which are
required for probe and rest we can use the driver as before, so-that
regulator, clock, gpio, reset, pinctrl we use step by step.

[Andre Przywara]

Hi,

Yes, but how do you want to make this happen in the one remaining week
of the merge window? For some reason I was totally unaware of this
deadline, and we should have started working on this months ago. But my
DeLorean is in the garage, so we can only look forward from here.

Which means we start with just DM_MMC, but not DM_SPL_MMC, and hope that
this threat of "Boards not converted by this time may be removed in a
subsequent release." does not really apply to sunxi as strictly as put
in this file.

The rest comes over time, giving us opportunity to find solutions for
the space constraint problems.

>> See the definition of CONFIG_IS_ENABLED().
>> So by just #defining CONFIG_DM_MMC the SPL still looks the same (using
>> the non-DM code), and indeed I don't run into size issues with the SPL.
>
> Even to use DM_MMC in SPL we should enable SPL_DM so I'm unable to
> build SPL even with SPL_DM=y

??? I said we should *not* #define DM_SPL_MMC, because of (not only)
this reason. If we follow Heinrich's patch, it just selects DM_MMC, so
no changes for the SPL.

> SPL build, with SPL_DM_, SPL_DM_MMC, SPL_OF_PLATDATA
>
> aarch64-linux-gnu-ld.bfd: address 0x18d18 of u-boot-spl section
> `.text' is not within region `.sram'
> aarch64-linux-gnu-ld.bfd: u-boot-spl section `.rodata' will not fit in
> region `.sram'
> aarch64-linux-gnu-ld.bfd: address 0x18d18 of u-boot-spl section
> `.text' is not within region `.sram'
> aarch64-linux-gnu-ld.bfd: address 0x18d18 of u-boot-spl section
> `.text' is not within region `.sram'
> aarch64-linux-gnu-ld.bfd: region `.sram' overflowed by 11104 bytes

Sure, no surprise.

>> Given the uniformity of at least the MMC device in sunxi, I think in the
>> medium term we get away with some simple platdata, without pulling the
>> DT into SPL. The clocks might be a bit more hairy here, though. But
>> that's nothing for *now* to solve.
>
> platdata available only for SPL, not for U-Boot proper.

Yes, that's what I meant: fixed platdata for SPL, U-Boot proper gets the
full DT glory.

> I agree that clock might be more hairy for now. and we can go with DT
> for U-Boot proper and just grab the minimum properties which are
> required for probe and rest we can use the driver as before, so-that
> regulator, clock, gpio, reset, pinctrl we use step by step.

That is what I was trying to say ;-)

Cheers,
Andre.

[Jagan Teki]

On Wed, Mar 28, 2018 at 4:45 PM, Maxime Ripard
<maxime...@bootlin.com> wrote:

> On Wed, Mar 28, 2018 at 03:22:20PM +0530, Jagan Teki wrote:
>> >> May it's good option to look at v3 changes, since DM_MMC Migration
>> >> expires in coming release, dt changes which are related to MMC we can
>> >> wait for proper supported feature get IN(like pinctrl, clock, reset),
>> >> that means we should anyway need to move DM_MMC but with working dt
>> >> changes.
>> >>
>> >> The big question for me here is about SPL, I'm sure we can get the
>> >> size issues. May be we try platdata but in any case we need to enable
>> >> DM ie increase the size (atleast for A64, H5)
>> >
>> > So my understanding is that those DM_<SUBSYS> defines are just for
>> > U-Boot proper, and the SPL needs extra symbols to be also "DMed".
>>
>> I don't think so, Idea about migrating to BLK, DM_MMC should remove
>> #ifdef code with DM vs non-DM such that the driver should have DM
>> version with DT along with PLATDATA
>

> I'm not even sure what is the point of having the DM in the SPL. We
> won't be able to have any of the benefits due to our size constraint.

True, but what if MIGRATION.txt intention is to remove old or non-dm
code after v2018.05?

Jagan.

[Andre Przywara]

Hi,

On 29/03/18 09:51, Jagan Teki wrote:
> Hi Andre,
>
> On Wed, Mar 14, 2018 at 7:26 AM, Andre Przywara <andre.p...@arm.com> wrote:
>> A minor update to the v3 version sent earlier this month.
>> I reworked patch 09 to drop the direct MMC environment for 32-bit Allwinner
>> boards as well and keep the current MMC offset.
>> For now I also dropped the two patches changing (back) the MMC regulator.
>> I still believe they are good to have and keep them as U-Boot specific
>> .dtsi files in my tree, possibly posting them later again.
>>
>> As the previous version, this combines the EMAC DT support update with
>> an update of the full Linux kernel DTs for all H3, H5 and A64 boards.
>>
>> Patch 01 leaves some hint in the README how to avoid the situation
>> when overrunning U-Boot's image size on 64-bit boards.
>> The old v2 EMAC DT update series is in patches 02-08, it prepares U-Boot's
>> EMAC driver for using the new DT binding used in Linux, also updates
>> the DTs to the new EMAC DT node already.
>>
>> Changes to sync the whole of U-Boot's DT files for the H3, H5 and A64 SoCs
>> to those from Linux are in the following patches. However this first requires
>> lifting the space limit we currently have due to the raw MMC environment.
>> Patch 09 disables that for all sunxi boards, to give us finally some
>> space. Patches 10 and 11 consequently revert the disabling of features we
>> saw a few weeks ago to migitate the size problem.
>>
>> Patches 12-19 then bring in the Linux DTs, split by SoCs, with the .dtsi
>> files first, then the board files.
>>
>> Merging the H3 and H5 device tree files brings in significant changes,
>> also to the structure of the .dtsi files. However U-Boot's own DT usage
>> is pretty limited, so it doesn't matter.
>>
>> The huge benefit of syncing the DTs is that we can use U-Boot's DT copy
>> to directly pass it to the kernel, avoiding to actually load a .dtb file
>> from somewhere. To allows seamless and automatic UEFI booting, so
>> distribution installer images should just work (TM).
>>
>> As a goodie the final patch brings in the actual SoPine + baseboard DT
>> files, which we were completely missing so far.
>>
>> This is based on sunxi/master (2d53018a0ef2).
>>
>> Cheers,
>> Andre.
>>
>> Changelog v3 .. v4:
>> - remove MMC environment for all Allwinner boards (including 32 bit ones)
>> - keep MMC environment offset to the old values
>> - drop DT adjustments to use fixed MMC regulator
>>
>> Changelog v2 .. v3:
>> 01: added, was on the list before
>> 02: drop redundant H5 line
>> 03-08: unchanged
>> 09-20: added
>>
>> Changelog v1 .. v2:
>> 01, 02, 03: unchanged
>> 04, 05, 06, 07: added
>>
>> Andre Przywara (19):
>> sunxi: README.sunxi64: Add hint about non-debug of ARM Trusted
>> Firmware
>> sunxi: gpio: add missing compatible strings
>> net: sun8i-emac: support new pinctrl DT bindings
>> net: sun8i-emac: add support for new EMAC DT binding
>> arm: dts: sunxi: update A64 to new EMAC binding
>> arm: dts: sunxi: update H3 to new EMAC binding
>> arm: dts: sunxi: update H5 to new EMAC binding
>> net: sun8i-emac: remove support for old binding
>> sunxi: disable direct MMC environment
>> sunxi: revert disabling of features
>> Revert "sunxi: Pine64: temporarily remove extra Pine64 non-plus DT"
>> sunxi: DT: A64: update device tree file for Allwinner A64 SoC
>> sunxi: DT: A64: update board .dts files from Linux
>> sunxi: DT: update device tree files for Allwinner H3 and H5 SoCs
>> sunxi: DT: H5: update board .dts files from Linux
>> sunxi: DT: H3: update board .dts files from Linux
>> sunxi: DT: H3: update libre-cc board .dts file
>> sunxi: DT: H2+: update Opi-zero .dts
>> sunxi: DT: A64: add proper SoPine baseboard device tree
>
> I agree that we have space for now with U-Boot proper since we removed
> MMC raw, but why we need to Sync all the dts nodes from Linux?

The main reason for me is to allow passing U-Boot's DT to Linux - or any
other OS, for that matter. This happens already automatically with the
distro defaults UEFI boot: just put in an UEFI enabled USB pen drive
(distro installers) and U-Boot will boot from there - without any user
interaction or special boot script, without the OS providing any DTs.

Conceptually there is only one DT for each board. The fact that U-Boot
has deviated has no technical reason, it's just not being updated.

> it is costing some space right?

We don't care about this so much anymore. For practical reasons it would
be good to stay below 984KB (from after the SPL till 1MB, where the
first partition normally starts). Adding like 10 KB to the image size is
nothing in there, especially when looking at the benefits - automatic
boot of any OS.

> becuase
> - most of the nodes doesn't have proper drivers yet example: clock,
> reset, spi, axp803 and some include files and etc
> - Few nodes like mmc1 from bananpi-m64 doesn't need from U-Boot point-of-view

Yes, U-Boot itself does not use those - but it doesn't hurt either. We
don't need to invent some notion of U-Boot DT. The DT is not an OS
configuration file, it's a hardware description.

> What I'm trying to say is we should anyway sync to Linux bindings and
> dts files, but that could be like step-by-step based on the relevant
> driver support with proper testing this way we can monitor the "Size"
> instead of adding unneeded(for now) and untested once now struggling
> to think about size constraints later.

I hope we will never have to deal with hard size constraint for U-Boot
proper anymore. I would like to judge any increase in size by its
benefit. And booting random UEFI enabled OSes out of the box is a very
good rationale for adding 10KB to the image size.

Keep in mind: Eventually you have to load this DT anyway, so effectively
you will save on the image size, because you avoid duplication. Actually
the OS does not need to carry all supported DTs, because the only one
needed is provided by U-Boot.

> If are fine with this please re-work based on above points and resend
> the next version otherwise please comment.

I wonder if we could just merge the first few patches now, up until and
including 11/19. The EMAC DT binding deviation we have at the moment is
really annoying and those patches do not increase the size.

We can have a separate discussion about the rest, if you really like.

Cheers,
Andre.

[Jagan Teki]

On Thu, Mar 29, 2018 at 2:37 PM, Maxime Ripard
<maxime...@bootlin.com> wrote:

> Then that intention is unreallistic, and unless the one that wrote it
> can make it fit in the SPL of all platforms, that's just wishful
> thinking.

I do have follow similar approach to remove #ifdef for SPI(_FLASH)
areas, I already written to MMC migration thread hope they come back
with proper.

Jagan.

[Chen-Yu Tsai]

Hi,

You could post an initial version during the merge window, and refine it
in the following two weeks? AFAIK the rules allow for it to be merged for
the coming release, instead of the next.

Curiously, U-boot repositories don't have -next branches. Is that a
maintainer preference? Having one would help developers in a way as
to not have to hunt down prerequisites and try to figure out whether
they have passed review and will be merged or not, and also avoid
conflicts with other to-be-queued patches. I know this takes extra
effort from the maintainer to possibly rebase or manage conflicts
after a new merge window has opened, as I personally manage sunxi-next
for the Linux kernel to serve as sort of an integration branch for
others. I'm asking is it possible to have -next, even just for sunxi.

>
> Keep you posted.

I'm interested. IMHO we don't need full blown drivers like in Linux.
We should be able to get away with selectively supporting only the
resources needed for the peripherals supported / actively used in U-boot.
This goes for clocks, resets, pinctrl, regulators, etc..

Regards
ChenYu

[André Przywara]

On 30/03/18 05:25, Chen-Yu Tsai wrote:

....

>> OK. So meanwhile I have something almost(TM) working:
>> - drivers/clk/sunxi/clk-a64.c, which is a UCLASS_CLK implementation of
>> the clock IDs from allwinner,sun50i-a64-ccu that we need: CLK_BUS_UARTx,
>> CLK_BUS_MMCx, CLK_MMCx. Their implementation is fairly simple, actually
>> (I did it the U-Boot way, not pulling in any super-fancy Linux code).
>> Porting this over to H3/H5 and other SoCs should be trivial: copy/paste
>> for now. We can look at how to unify this later.
>> - drivers/mmc/sunxi_mmc.c extended to use UCLASS_CLK clocks. This is
>> also not too bad, but I seem to miss a bit in here, as it times out.
>> Will debug this tonight.
>> - Cowardly dodging a proper UCLASS_RESET driver for now, instead hacking
>> the single bit in :-(
>>
>> That looks tight to still get into this merge window, though, at least
>> if we follow the usual process.
>
> You could post an initial version during the merge window, and refine it
> in the following two weeks? AFAIK the rules allow for it to be merged for
> the coming release, instead of the next.

Is that so? I had the impression that this was tightened in the last few
releases, so no features would be allowed beyond the merge window
anymore. I will try to send something ASAP, but ...

> Curiously, U-boot repositories don't have -next branches. Is that a
> maintainer preference? Having one would help developers in a way as
> to not have to hunt down prerequisites and try to figure out whether
> they have passed review and will be merged or not, and also avoid
> conflicts with other to-be-queued patches. I know this takes extra
> effort from the maintainer to possibly rebase or manage conflicts
> after a new merge window has opened, as I personally manage sunxi-next
> for the Linux kernel to serve as sort of an integration branch for
> others. I'm asking is it possible to have -next, even just for sunxi.
>
>>
>> Keep you posted.
>
> I'm interested. IMHO we don't need full blown drivers like in Linux.
> We should be able to get away with selectively supporting only the
> resources needed for the peripherals supported / actively used in U-boot.
> This goes for clocks, resets, pinctrl, regulators, etc..

So I have something(TM) working now. This is a bit like a can of worms:
- As mentioned above, we need a UCLASS_CLK driver. This is pretty
straightforward, one driver per SoC, then something like:
int sunxi_clk_enable(clk)
{
switch (clk->id) {
case CLK_MMC0:
addr = priv->base + 0x88;
setbits_le32(clk_base, BIT(31));
(plus get_rate/set_rate)
As you guessed, we just list the clocks we need, in the moment this is
UART and MMC. Adding new clocks is easy, other SoCs can be copy&pasted
for now, we might find a clever way of code sharing later.
One nasty property is the marriage of RESET and CLK in the sunxi-ng
clock binding. So we also need a DM reset driver. I need to wrap my head
around how to instantiate those at the same time from only one compatible.

- Also I realised two days ago that we need a DM pinctrl driver. As this
was on my list anyway, I just bit the bullet. Eventually this isn't as
bad as it sounds, as I resorted to the "pinmux" property to give me the
mux value, so don't need the huge table Linux uses.
But: a similar problem as above, as we need to marry this to the already
existing DM_GPIO driver, because they share a DT node.

So the current status is:
- UCLASS_CLK works and looks fairly reasonable.
- UCLASS_PINCTRL works, just requires adding a pinmux property to each
pinctrl pin group node (just a few), as I proposed last year for Linux[1].
- no UCLASS_RESET for the sunxi-ng resets yet. Hacked badly atm.
- The existing UCLASS_GPIO driver clashes with UCLASS_PINCTRL, so I
disabled the former for now.
- The existing UCLASS_MMC driver got amended to use all of those.

This boots on the Pine64, at least via FEL, with USB, MMC and Ethernet
working in U-Boot proper.

Just in case someone gets impatient:
https://github.com/apritzel/u-boot/commits/sunxi-dm-WIP

I will try to get rid of the hacks and post an RFC.

But, as Jagan mentioned already: eventually the outcome is quite
questionable. For the near future we need the non-DM bits (UART + MMC)
for the SPL still, so we can't get rid of this code. So technically we
support DM_MMC/DM_BLK, but it's not clear what the actual benefit is.

Cheers,
Andre.

[1]
http://archive.armlinux.org.uk/lurker/message/20171113.012520.b50dc300.en.html

[Chen-Yu Tsai]

We could look at how the DM gpio driver currently does it: The compatible
matches the driver directly, and the DM bind function creates many child
devices using platform data and binds it to the same driver. The device
node is also assigned to the same one. AFAIK you have to figure out how
to lookup a different driver by name for the child device, e.g. a reset
driver to bind to the child device of the clk device.

In addition, Philipp from Theobroma Systems posted a series some time ago
for sunxi DM conversion, which included some patches that involved creating
multiple uclass devices for the same device node.

>
> - Also I realised two days ago that we need a DM pinctrl driver. As this
> was on my list anyway, I just bit the bullet. Eventually this isn't as
> bad as it sounds, as I resorted to the "pinmux" property to give me the
> mux value, so don't need the huge table Linux uses.
> But: a similar problem as above, as we need to marry this to the already
> existing DM_GPIO driver, because they share a DT node.

Same as the above I guess? And having the pinctrl driver as the base device
might work out better. It looks like we won't have gpio/pinctrl exclusivity
like we do in Linux, so people should try to avoid shooting themselves in
the foot. We could try denying requests based on whether the pinmux value
in the register is not the default GPIO / disconnected value.

>
> So the current status is:
> - UCLASS_CLK works and looks fairly reasonable.
> - UCLASS_PINCTRL works, just requires adding a pinmux property to each
> pinctrl pin group node (just a few), as I proposed last year for Linux[1].

IIRC this didn't go well? We could have a simplified table to cover the
use cases we need (again it's probably just UART + MMC). We don't need
to declare every single pin. Since a function tends to have the same
pinmux value for each used pin within the same pingroup, we could just
have a table that maps [SoC, pingroup, function] to pinmux value. And
you could just ignore the gpio_{in,out} pinmux nodes.

> - no UCLASS_RESET for the sunxi-ng resets yet. Hacked badly atm.
> - The existing UCLASS_GPIO driver clashes with UCLASS_PINCTRL, so I
> disabled the former for now.
> - The existing UCLASS_MMC driver got amended to use all of those.
>
> This boots on the Pine64, at least via FEL, with USB, MMC and Ethernet
> working in U-Boot proper.
>
> Just in case someone gets impatient:
> https://github.com/apritzel/u-boot/commits/sunxi-dm-WIP
>
> I will try to get rid of the hacks and post an RFC.
>
> But, as Jagan mentioned already: eventually the outcome is quite
> questionable. For the near future we need the non-DM bits (UART + MMC)
> for the SPL still, so we can't get rid of this code. So technically we
> support DM_MMC/DM_BLK, but it's not clear what the actual benefit is.

My thoughts exactly. We end up with either two drivers, one DM and one not,
or we have a whole bunch of #ifdefs in the DM driver to trim it down for
SPL.


Regards
ChenYu

[André Przywara]

On 02/04/18 08:40, Jagan Teki wrote:

Hi Jagan,

> If I understood correctly, look like all comments from your side for
> syncing full Linux dts have benefit with automatic boot of OS.
>
> This feature make U-Boot to have full Linux dts inside, Can't we
> implement automatic-boot-of-os distro to grab Linux dtb during
> commands stage like other distro does?

You mean something like:
$ fatload mmc 0 $fdt_addr_r $fdtfile

I think that works already and some distros use it.
But my point is that distros don't need to ship DTs at all. Actually
this is the EFI boot flow: The UEFI firmware provides the DT. Firmware
is device specific anyway, so just bundling up the DT is a no-brainer.
So when using the EFI boot flow there is no canonical way for the OS to
provide a .dtb (leave alone the grub DT hack, which is just that: a hack).
This might not be be a strong argument if you think of Linux, because it
carries all DTs. But for instance I can boot FreeBSD with that method
(mainline Linux DTs in U-Boot) just fine. FreeBSD doesn't have DTs for
ARM64 systems, as no other supported ARM64 platform require them.

And also this allows to boot boards which a particular (distribution
provided!) kernel just didn't support. Sometimes DTs are just not
upstreamed, or miss a certain release. But technically it's just the DT
that is different, and the kernel would run just fine on that board.
Think Pine64-LTS or the Olimex laptop, plus any other boards for which
nobody cared so far. And now run them on the new Ubuntu 18.04 LTS.

> Because this make few
> development struggles for U-Boot project like (few of the comments are

I don't get what's the "struggle" here. We have a canonical DT source:
the Linux kernel. We sync those files over from time to time. U-Boot
should not use its own (conflicting) bindings in the first place anyway.
So fixing this up in U-Boot, if needed, is good in any case, and mostly
not hard to do. For all the nodes that U-Boot doesn't care about at all
(video, audio) it's a no-brainer anyway.

> repeated from previous mail, but I'm trying to group them all)
> - Unnecessary to maintain nodes which are not required for bootloader
> and which doesn't have proper dt drivers.

What's to maintain? The patches I sent copy all the .dts and .dtsi files
verbatim from Linux. I mentioned the Linux commit in the later
revisions, I think.

> - It becomes more patches for each-and-every sync.

??? What's the problem with that? If you are concerned about churn: We
can have *one* DT update patch for every kernel release, that's about 4
patches a year.
And review-wise this is really easy, as you could rely on the Linux
review, possibly do some testing to see if it breaks something in
U-Boot. If it does, chances are that U-Boot had a bug and would need to
be updated anyway.

> - We can compare the sync with Linux dt and simply apply on U-Boot
> which look not good to project growing.

This sounds like actual work, compared to just copy the .dts files.

> - Increase size(though it 10KB increase) it becomes unnecessary size
> from U-Boot point-of-view

But that's the DT file, not the code size. Yes, it contributes to the
overall image size, but as mentioned before: You need the full blown DT
file anyway.

I see that this is a departure from the strict embedded use case, where
everything gets bundled into one gigantic image for a particular board.
But maintaining those images (per distribution!) for all the boards out
there is just a maintenance nightmare and technically not necessary.

>>> If are fine with this please re-work based on above points and resend
>>> the next version otherwise please comment.
>>
>> I wonder if we could just merge the first few patches now, up until and
>> including 11/19. The EMAC DT binding deviation we have at the moment is
>> really annoying and those patches do not increase the size.
>

> Will re-check and apply all OK.

Thanks, that would be much appreciated!

>> We can have a separate discussion about the rest, if you really like.
>

> Worth to have thread with subject like "Full DT sync from Linux is required?"

That thread can be very short: Yes, it is. :-D

Cheers,
Andre

[André Przywara]

On 02/04/18 12:20, Mark Kettenis wrote:

....

>> This feature make U-Boot to have full Linux dts inside, Can't we
>> implement automatic-boot-of-os distro to grab Linux dtb during

>> commands stage like other distro does? Because this make few

>> development struggles for U-Boot project like (few of the comments are

>> repeated from previous mail, but I'm trying to group them all)
>> - Unnecessary to maintain nodes which are not required for bootloader
>> and which doesn't have proper dt drivers.

>> - It becomes more patches for each-and-every sync.

>> - We can compare the sync with Linux dt and simply apply on U-Boot
>> which look not good to project growing.

>> - Increase size(though it 10KB increase) it becomes unnecessary size
>> from U-Boot point-of-view
>

> This is not just about booting Linux. And even if it was, it means
> that you can only boot on hardware for which a full device tree is
> included in your distro. So a new board that comes with a usable
> U-Boot in SPI flash still won't work since the right device tree isn't
> there.

Ah right, I didn't even mention SPI flash in that thread. Thanks!

Out of curiosity: what OS are you thinking about? Collecting trophies
here ;-) I tried the FreeBSD-current installer the other day, and it
worked pretty well.

> So I Agree with Andre, U-Boot should provide the full device tree if
> possible. That doesn't mean it shouldn't try to load a device tree
> from the boot media if there is one. That way users can easily
> update/tweak their device tree without re-flashing the complete
> firmware.

Yes, users should still be able to provide their own DT, if needed.
Actually that's what I often do for Linux development myself.

Thanks!
Andre.

[André Przywara]

On 02/04/18 13:47, Mark Kettenis wrote:

Hi,

> OpenBSD. ARMv8-wise, our support for Allwinner A64/H5 and Rockchip
> RK3399 is pretty decent these days and Rockchip RK3328 is coming along
> as well.

Ah, great! I didn't know that OpenBSD was that far.
Do you know of anything missing in the DT or UEFI support from mainline
U-Boot? I put firmware images on my Pine64 github repo[1] for A64 and H5
boards, which are based on 2018.03 plus this series, if you want to give
it a try.
Trying to wrap my around INSTALL.arm64, but you might be faster ;-)
Does 6.2 provide enough to work? Or shall I wait till the 15th?

> And I'm working on Marvell 8040 support. There is support
> for ARMv7 as well which includes many of the older Allwinner SoCs.
> We don't have the resources to build images for all the different
> boards that are out there though, which probably is the biggest
> stumbling block for getting OpenBSD to run. Our bootloader is UEFI,

That sounds good!

> so with a recent enough U-Boot in flash the default install.fs image

Is that the FFS filesystem in the OpenBSD partition of miniroot.fs?
Which just contains the bsd.rd kernel + RAM fs?
The 6.2 directory didn't have an explicit install.fs image.

Cheers,
Andre

[1] https://github.com/apritzel/pine64/tree/master/images

> should just work. It does on Rock64! Otherwise you have to know the
> magic to write the U-Boot image at the right location into that image
> to make it boot.
>
> Cheers,
>
> Mark
>

[Jagan Teki]

what about writing glue mmc spl code? like what we did for spi_flash
or drivers/mmc/fsl_esdhc_spl.c

[Andre Przywara]

Hi,

So what is your idea here? To make a small SPL driver which directly
calls some internal, but exported function from the DM driver, which
does the actual work? So that the DM driver has all the DM boilerplate
around that function, and the SPL driver does not? But it sounds hairy
when it comes to the details ...
We could get away with just read support, I guess?

Do you feel like giving this a try and see how it looks like?

Cheers,
Andre.

[Jagan Teki]

+ Vasily

May be an another option to try, because trying for another stage like
TPL seems doesn't suit for A64.