Hi,
Apologies for the bad etiquette - I didn't realise the copy paste from bootlin would put so much HTML. I will strip the formatting from my messages in the future.
I am away from my desk and devkit for a few days, but I think I could have narrowed it down to two issues:
1) Clock is wrong source - according to the device tree the mod clock for the DSI interface is from TCON_TOP as you mention, and from the patchset "[PATCH v2 1/4] dt-bindings: display: sun6i-dsi: Fix clock conditional"
Samuel makes the following point: "the module clock routes through the TCON TOP".
the device tree has the following:
dsi: dsi@5450000 {
compatible = "allwinner,sun20i-d1-mipi-dsi",
"allwinner,sun50i-a100-mipi-dsi";
reg = <0x5450000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MIPI_DSI>,
<&tcon_top CLK_TCON_TOP_DSI>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_MIPI_DSI>;
phys = <&dphy>;
phy-names = "dphy";
status = "disabled";
};
dphy: phy@5451000 {
compatible = "allwinner,sun20i-d1-mipi-dphy",
"allwinner,sun50i-a100-mipi-dphy";
reg = <0x5451000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MIPI_DSI>,
<&ccu CLK_MIPI_DSI>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_MIPI_DSI>;
#phy-cells = <0>;
};
In this case the DPHY is getting its clock from the CCU node "CLK_MIPI_DSI" instead of TCON TOP, so one of the following cases could be true:
> The DSI node should get its mod clock from CCU CLK_MIPI_DSI and the TCON_TOP CLK_TCON_TOP_DSI clock source is incorrect, or
> The DPHY should get its mod clock from TCON_TOP CLK_TCON_TOP_DSI and the ccu CLK_MIPI_DSI source is incorrect, or
> These clock sources are correct and there is some other issue (such as below).
2) alternatively, it could be just a quirk of the D1/T113 TCON TOP setup.
I also had found this in reviewing the devicetree for this board - the patchset "[PATCH v2 00/14] drm/sun4i: Allwinner D1 Display Engine 2.0 Support" includes the TCON Top Support the following note:
[PATCH v2 12/14] drm/sun4i: Add support for D1 TCON TOP
"D1 has a TCON TOP with TCON TV0 and DSI, but no TCON TV1. This puts theDSI clock name at index 1 in clock-output-names. Support this by only incrementing the index for clocks that are actually supported."
But reviewing the DSI node:
dsi: dsi@5450000 {
compatible = "allwinner,sun20i-d1-mipi-dsi",
"allwinner,sun50i-a100-mipi-dsi";
reg = <0x5450000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MIPI_DSI>,
<&tcon_top CLK_TCON_TOP_DSI>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_MIPI_DSI>;
phys = <&dphy>;
phy-names = "dphy";
status = "disabled";
the definition of CLK_TCON_TOP_DSI comes from sun8i-tcon-top.h:
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/* Copyright (C) 2018 Jernej Skrabec <
jernej....@siol.net> */
#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
#define CLK_TCON_TOP_TV0 0
#define CLK_TCON_TOP_TV1 1
#define CLK_TCON_TOP_DSI 2
#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */
I believe, if that the quirk of the D1s correct to the above comment, the incorrect clock index is being selected in the devicetree which would also cause the failure.
In which case:
clocks = <&ccu CLK_BUS_MIPI_DSI>, <&tcon_top 1>;
clock-names = "bus", "mod";
would be a sufficient fix without updating the header/source.
Either case as soon as I am back with my devkit, I would try this for sure and try and see if I can find an answer.
>You can check /sys/kernel/debug/clk/clk_summary (with debugfs mounted)
>to see what clocks are there and how they are used
Also great information, I will test.
Regards,