[PATCH 2/8] sunxi: SPL SPI: add support for read command with 2 byte address

[Icenowy Zheng]

This kind of read command is utilized in SPI NANDs for reading data
inside a selected page, which is obviously smaller than how much 2
byte address can address. So 2 bytes are used for the address and one
dummy byte is needed after the real address. As the address is sent out
in bit endian, this makes it not compatible with usual 3 byte address.

Signed-off-by: Icenowy Zheng <u...@icenowy.me>
---
arch/arm/mach-sunxi/spl_spi_sunxi.c | 20 +++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 7975457758..88c15a3ee9 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -305,7 +305,7 @@ static void spi0_xfer(const u8 *txbuf, u32 txlen, u8 *rxbuf, u32 rxlen)
}
}

-static void spi0_read_data(void *buf, u32 addr, u32 len)
+static void spi0_read_data(void *buf, u32 addr, u32 len, u32 addr_len)
{
u8 *buf8 = buf;
u32 chunk_len;
@@ -316,9 +316,15 @@ static void spi0_read_data(void *buf, u32 addr, u32 len)

/* Configure the Read Data Bytes (03h) command header */
txbuf[0] = 0x03;
- txbuf[1] = (u8)(addr >> 16);
- txbuf[2] = (u8)(addr >> 8);
- txbuf[3] = (u8)(addr);
+ if (addr_len == 3) {
+ txbuf[1] = (u8)(addr >> 16);
+ txbuf[2] = (u8)(addr >> 8);
+ txbuf[3] = (u8)(addr);
+ } else if (addr_len == 2) {
+ txbuf[1] = (u8)(addr >> 8);
+ txbuf[2] = (u8)(addr);
+ txbuf[3] = 0; /* dummy */
+ }

if (chunk_len > SPI_READ_MAX_SIZE)
chunk_len = SPI_READ_MAX_SIZE;
@@ -337,7 +343,7 @@ static void spi0_read_data(void *buf, u32 addr, u32 len)
static ulong spi_load_read(struct spl_load_info *load, ulong sector,
ulong count, void *buf)
{
- spi0_read_data(buf, sector, count);
+ spi0_read_data(buf, sector, count, 3);

return count;
}
@@ -356,7 +362,7 @@ static int spl_spi_load_image(struct spl_image_info *spl_image,

spi0_init();

- spi0_read_data((void *)header, load_offset, 0x40);
+ spi0_read_data((void *)header, load_offset, 0x40, 3);

if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
image_get_magic(header) == FDT_MAGIC) {
@@ -376,7 +382,7 @@ static int spl_spi_load_image(struct spl_image_info *spl_image,
return ret;

spi0_read_data((void *)spl_image->load_addr,
- load_offset, spl_image->size);
+ load_offset, spl_image->size, 3);
}

spi0_deinit();
--
2.37.1

[Icenowy Zheng]

This patchset tries to extend SPI-based boot code in sunxi SPL to
support SPI NAND, following the same principle with current SPI NOR code
(mimicking the behavior of sunxi BROM). In addition, as part of test to
this patchset, some patches for Source Parts Inc. PopStick is attached,
although marked DO NOT MERGE because the DT should come from Linux after
it's ready.

To keep thr code that accesses SPI NAND as simple as possible, it
assumes fixed page size, which is also what sunxi BROM does. The SUNIV
SPL assumes 0x400 page size, but here to utilize the space better, in
the attached example of PopStick, U-Boot main part is assumed to be
with 0x800 page size (which is the real situation of the W25N01 flash
used by PopStick).

Icenowy Zheng (8):
sunxi: SPL SPI: extract code for doing SPI transfer
sunxi: SPL SPI: add support for read command with 2 byte address
sunxi: SPL SPI: allow multiple boot attempt
sunxi: SPL SPI: add initial support for booting from SPI NAND
sunxi: enable support for SPI NAND booting on SUNIV
[DO NOT MERGE] sunxi: sync DT from my tree for PopStick
[DO NOT MERGE, DIRTY HACK] sunxi: use UBI for environement storage
[DO NOT MERGE] sunxi: add a defconfig for PopStick

arch/arm/dts/Makefile | 3 +-
arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 16 ++
arch/arm/dts/suniv-f1c100s.dtsi | 26 ++
arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts | 101 ++++++++
arch/arm/mach-sunxi/Kconfig | 16 ++
arch/arm/mach-sunxi/board.c | 4 +-
arch/arm/mach-sunxi/spl_spi_sunxi.c | 247 ++++++++++++++-----
board/sunxi/board.c | 1 +
configs/popstick_defconfig | 35 +++
9 files changed, 377 insertions(+), 72 deletions(-)
create mode 100644 arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts
create mode 100644 configs/popstick_defconfig

--
2.37.1

[Icenowy Zheng]

To support SPI NAND flashes, more commands than Read (03h) are needed.

Extract the code for doing SPI transfer from the reading code for code
reuse.

Signed-off-by: Icenowy Zheng <u...@icenowy.me>
---

arch/arm/mach-sunxi/spl_spi_sunxi.c | 105 ++++++++++++++++------------
1 file changed, 59 insertions(+), 46 deletions(-)

diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 925bf85f2d..7975457758 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -243,77 +243,90 @@ static void spi0_deinit(void)

#define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */

-static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize,
- ulong spi_ctl_reg,
- ulong spi_ctl_xch_bitmask,
- ulong spi_fifo_reg,
- ulong spi_tx_reg,
- ulong spi_rx_reg,
- ulong spi_bc_reg,
- ulong spi_tc_reg,
- ulong spi_bcc_reg)
+static void sunxi_spi0_xfer(const u8 *txbuf, u32 txlen,
+ u8 *rxbuf, u32 rxlen,
+ ulong spi_ctl_reg,
+ ulong spi_ctl_xch_bitmask,
+ ulong spi_fifo_reg,
+ ulong spi_tx_reg,
+ ulong spi_rx_reg,
+ ulong spi_bc_reg,
+ ulong spi_tc_reg,
+ ulong spi_bcc_reg)
{
- writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */
- writel(4, spi_tc_reg); /* Transfer counter (bytes to send) */
+ writel(txlen + rxlen, spi_bc_reg); /* Burst counter (total bytes) */
+ writel(txlen, spi_tc_reg); /* Transfer counter (bytes to send) */
if (spi_bcc_reg)
- writel(4, spi_bcc_reg); /* SUN6I also needs this */
+ writel(txlen, spi_bcc_reg); /* SUN6I also needs this */

- /* Send the Read Data Bytes (03h) command header */
- writeb(0x03, spi_tx_reg);
- writeb((u8)(addr >> 16), spi_tx_reg);
- writeb((u8)(addr >> 8), spi_tx_reg);
- writeb((u8)(addr), spi_tx_reg);
+ for (u32 i = 0; i < txlen; i++)
+ writeb(*(txbuf++), spi_tx_reg);

/* Start the data transfer */
setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask);

/* Wait until everything is received in the RX FIFO */
- while ((readl(spi_fifo_reg) & 0x7F) < 4 + bufsize)
+ while ((readl(spi_fifo_reg) & 0x7F) < txlen + rxlen)
;

- /* Skip 4 bytes */
- readl(spi_rx_reg);
+ /* Skip txlen bytes */
+ for (u32 i = 0; i < txlen; i++)
+ readb(spi_rx_reg);

/* Read the data */
- while (bufsize-- > 0)
- *buf++ = readb(spi_rx_reg);
+ while (rxlen-- > 0)
+ *rxbuf++ = readb(spi_rx_reg);
+}
+
+static void spi0_xfer(const u8 *txbuf, u32 txlen, u8 *rxbuf, u32 rxlen)
+{
+ uintptr_t base = spi0_base_address();

- /* tSHSL time is up to 100 ns in various SPI flash datasheets */
- udelay(1);
+ if (is_sun6i_gen_spi()) {
+ sunxi_spi0_xfer(txbuf, txlen, rxbuf, rxlen,
+ base + SUN6I_SPI0_TCR,
+ SUN6I_TCR_XCH,
+ base + SUN6I_SPI0_FIFO_STA,
+ base + SUN6I_SPI0_TXD,
+ base + SUN6I_SPI0_RXD,
+ base + SUN6I_SPI0_MBC,
+ base + SUN6I_SPI0_MTC,
+ base + SUN6I_SPI0_BCC);
+ } else {
+ sunxi_spi0_xfer(txbuf, txlen, rxbuf, rxlen,
+ base + SUN4I_SPI0_CTL,
+ SUN4I_CTL_XCH,
+ base + SUN4I_SPI0_FIFO_STA,
+ base + SUN4I_SPI0_TX,
+ base + SUN4I_SPI0_RX,
+ base + SUN4I_SPI0_BC,
+ base + SUN4I_SPI0_TC,
+ 0);
+ }

}

static void spi0_read_data(void *buf, u32 addr, u32 len)

{
u8 *buf8 = buf;
u32 chunk_len;

- uintptr_t base = spi0_base_address();
+ u8 txbuf[4];

while (len > 0) {
chunk_len = len;
+
+ /* Configure the Read Data Bytes (03h) command header */
+ txbuf[0] = 0x03;

+ txbuf[1] = (u8)(addr >> 16);
+ txbuf[2] = (u8)(addr >> 8);
+ txbuf[3] = (u8)(addr);
+

if (chunk_len > SPI_READ_MAX_SIZE)
chunk_len = SPI_READ_MAX_SIZE;

- if (is_sun6i_gen_spi()) {
- sunxi_spi0_read_data(buf8, addr, chunk_len,
- base + SUN6I_SPI0_TCR,
- SUN6I_TCR_XCH,
- base + SUN6I_SPI0_FIFO_STA,
- base + SUN6I_SPI0_TXD,
- base + SUN6I_SPI0_RXD,
- base + SUN6I_SPI0_MBC,
- base + SUN6I_SPI0_MTC,
- base + SUN6I_SPI0_BCC);
- } else {
- sunxi_spi0_read_data(buf8, addr, chunk_len,
- base + SUN4I_SPI0_CTL,
- SUN4I_CTL_XCH,
- base + SUN4I_SPI0_FIFO_STA,
- base + SUN4I_SPI0_TX,
- base + SUN4I_SPI0_RX,
- base + SUN4I_SPI0_BC,
- base + SUN4I_SPI0_TC,
- 0);
- }
+ spi0_xfer(txbuf, 4, buf8, chunk_len);
+
+ /* tSHSL time is up to 100 ns in various SPI flash datasheets */
+ udelay(1);

len -= chunk_len;
buf8 += chunk_len;
--
2.37.1

[Icenowy Zheng]

As we added support for SPI NAND to the existing SPL SPI codepath, route
the boot code to it when it detects the BROM loads SPL from SPI NAND, as
for SoCs with both SPI NAND and boot media indicator support, the boot
media indicator is the same for SPI NOR and NAND.

Signed-off-by: Icenowy Zheng <u...@icenowy.me>
---

arch/arm/mach-sunxi/board.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 220ed80ba7..3a81743e8f 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -210,12 +210,10 @@ static int suniv_get_boot_source(void)
case SUNIV_BOOTED_FROM_MMC0:
return SUNXI_BOOTED_FROM_MMC0;
case SUNIV_BOOTED_FROM_SPI:
+ case SUNIV_BOOTED_FROM_NAND:
return SUNXI_BOOTED_FROM_SPI;
case SUNIV_BOOTED_FROM_MMC1:
return SUNXI_BOOTED_FROM_MMC2;
- /* SPI NAND is not supported yet. */
- case SUNIV_BOOTED_FROM_NAND:
- return SUNXI_INVALID_BOOT_SOURCE;
}
/* If we get here something went wrong try to boot from FEL.*/
printf("Unknown boot source from BROM: 0x%x\n", brom_call);
--
2.37.1

[Icenowy Zheng]

Signed-off-by: Icenowy Zheng <u...@icenowy.me>
---

arch/arm/dts/Makefile | 3 +-
arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 16 +++
arch/arm/dts/suniv-f1c100s.dtsi | 26 +++++
arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts | 101 +++++++++++++++++++
4 files changed, 145 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9b00b64509..ef7fff3559 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -529,7 +529,8 @@ dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
stm32h750i-art-pi.dtb

dtb-$(CONFIG_MACH_SUNIV) += \
- suniv-f1c100s-licheepi-nano.dtb
+ suniv-f1c100s-licheepi-nano.dtb \
+ suniv-f1c200s-popstick-v1.1.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \
diff --git a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
index 04e59b8381..1935d8c885 100644
--- a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
+++ b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
@@ -6,6 +6,8 @@
/dts-v1/;
#include "suniv-f1c100s.dtsi"

+#include <dt-bindings/gpio/gpio.h>
+
/ {
model = "Lichee Pi Nano";
compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";
@@ -50,8 +52,22 @@
};
};

+&otg_sram {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pe_pins>;
status = "okay";
};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpio = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */
+ status = "okay";
+};
diff --git a/arch/arm/dts/suniv-f1c100s.dtsi b/arch/arm/dts/suniv-f1c100s.dtsi
index bc563c12e9..6d7b120da2 100644
--- a/arch/arm/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/dts/suniv-f1c100s.dtsi
@@ -133,6 +133,32 @@
#size-cells = <0>;
};

+ usb_otg: usb@1c13000 {
+ compatible = "allwinner,suniv-f1c100s-musb";
+ reg = <0x01c13000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <26>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ allwinner,sram = <&otg_sram 1>;
+ status = "disabled";
+ };
+
+ usbphy: phy@1c13400 {
+ compatible = "allwinner,suniv-f1c100s-usb-phy";
+ reg = <0x01c13400 0x10>;
+ reg-names = "phy_ctrl";
+ clocks = <&ccu CLK_USB_PHY0>;
+ clock-names = "usb0_phy";
+ resets = <&ccu RST_USB_PHY0>;
+ reset-names = "usb0_reset";
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
ccu: clock@1c20000 {
compatible = "allwinner,suniv-f1c100s-ccu";
reg = <0x01c20000 0x400>;
diff --git a/arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts b/arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts
new file mode 100644
index 0000000000..121dfc6f60
--- /dev/null
+++ b/arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Icenowy Zheng <u...@icenowy.me>
+ */
+
+/dts-v1/;
+#include "suniv-f1c100s.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Popcorn Computer PopStick v1.1";
+ compatible = "sourceparts,popstick-v1.1", "sourceparts,popstick",
+ "allwinner,suniv-f1c200s", "allwinner,suniv-f1c100s";
+
+ aliases {
+ mmc0 = &mmc0;
+ serial0 = &uart0;
+ spi0 = &spi0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 4 6 GPIO_ACTIVE_HIGH>; /* PE6 */
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&mmc0 {
+ cd-gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */
+ bus-width = <4>;
+ disable-wp;
+ status = "okay";
+ vmmc-supply = <&reg_vcc3v3>;
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pc_pins>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot-with-spl";
+ reg = <0x0 0x100000>;
+ };
+
+ ubi@100000 {
+ label = "ubi";
+ reg = <0x100000 0x7f00000>;
+ };
+ };
+ };
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pe_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
--
2.37.1

[Icenowy Zheng]

---
configs/popstick_defconfig | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
create mode 100644 configs/popstick_defconfig

diff --git a/configs/popstick_defconfig b/configs/popstick_defconfig
new file mode 100644
index 0000000000..6dc21695b7
--- /dev/null
+++ b/configs/popstick_defconfig
@@ -0,0 +1,35 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SYS_MALLOC_LEN=0x120000
+CONFIG_ENV_SIZE=0x1f000
+CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c200s-popstick-v1.1"
+CONFIG_SPL=y
+CONFIG_MACH_SUNIV=y
+CONFIG_DRAM_CLK=156
+CONFIG_DRAM_ZQ=0
+CONFIG_SUNXI_MINIMUM_DRAM_MB=64
+CONFIG_MMC0_CD_PIN="PE3"
+# CONFIG_VIDEO_SUNXI is not set
+CONFIG_SPL_SPI_SUNXI=y
+CONFIG_SPL_SPI_SUNXI_NAND=y
+CONFIG_SPL_SPI_SUNXI_NAND_ASSUMED_PAGESIZE=0x800
+CONFIG_SPL_STACK=0x8000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
+CONFIG_CMD_MTD=y
+# CONFIG_CMD_SF is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+# CONFIG_ENV_IS_IN_FAT is not set
+# CONFIG_ENV_IS_IN_SPI_FLASH is not set
+CONFIG_ENV_IS_IN_UBI=y
+CONFIG_ENV_UBI_PART="ubi"
+CONFIG_ENV_UBI_VOLUME="env"
+# CONFIG_NET is not set
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+# CONFIG_SPI_FLASH is not set
+CONFIG_SF_DEFAULT_SPEED=25000000
+# CONFIG_UBI_SILENCE_MSG is not set
+CONFIG_SPI=y
+# CONFIG_UBIFS_SILENCE_MSG is not set
--
2.37.1

[Icenowy Zheng]

Signed-off-by: Icenowy Zheng <u...@icenowy.me>
---

board/sunxi/board.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 21a2407e06..f4138573d4 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -133,6 +133,7 @@ void i2c_init_board(void)
*/
enum env_location env_get_location(enum env_operation op, int prio)
{
+ return prio ? ENVL_UNKNOWN : ENVL_UBI;
if (prio > 1)
return ENVL_UNKNOWN;

--
2.37.1

[Samuel Holland]

On 10/13/22 22:05, Icenowy Zheng wrote:
> To support SPI NAND flashes, more commands than Read (03h) are needed.
>
> Extract the code for doing SPI transfer from the reading code for code
> reuse.
>
> Signed-off-by: Icenowy Zheng <u...@icenowy.me>

One comment below.

Reviewed-by: Samuel Holland <sam...@sholland.org>
Tested-by: Samuel Holland <sam...@sholland.org> # Orange Pi Zero Plus

I think txbuf[i] would be a bit clearer here.

Regards,
Samuel

[Samuel Holland]

On 10/13/22 22:05, Icenowy Zheng wrote:

> This kind of read command is utilized in SPI NANDs for reading data
> inside a selected page, which is obviously smaller than how much 2
> byte address can address. So 2 bytes are used for the address and one
> dummy byte is needed after the real address. As the address is sent out
> in bit endian, this makes it not compatible with usual 3 byte address.

typo: big

> Signed-off-by: Icenowy Zheng <u...@icenowy.me>
> ---
> arch/arm/mach-sunxi/spl_spi_sunxi.c | 20 +++++++++++++-------
> 1 file changed, 13 insertions(+), 7 deletions(-)

Reviewed-by: Samuel Holland <sam...@sholland.org>
Tested-by: Samuel Holland <sam...@sholland.org> # Orange Pi Zero Plus

[Samuel Holland]

On 10/13/22 22:05, Icenowy Zheng wrote:

> As we added support for SPI NAND to the existing SPL SPI codepath, route
> the boot code to it when it detects the BROM loads SPL from SPI NAND, as
> for SoCs with both SPI NAND and boot media indicator support, the boot
> media indicator is the same for SPI NOR and NAND.
>
> Signed-off-by: Icenowy Zheng <u...@icenowy.me>
> ---
> arch/arm/mach-sunxi/board.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)

Reviewed-by: Samuel Holland <sam...@sholland.org>

[Icenowy Zheng]

在 2022-10-14星期五的 11:05 +0800，Icenowy Zheng写道：
> Signed-off-by: Icenowy Zheng <u...@icenowy.me>

By the way should we have some better way to handle the placement of
environments?