u-boot: rk3328: fails to read my SD cards
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黄鲜升
May 10, 2020, 9:51:30 PM5/10/20
to linux-rockchip
Hi all,
I ported the rk3328 to u-boot master branch, it works with u-boot-nodtb.bin, but fails when using u-boot.itb (dd offset 16384) and idbloader (dd offset 64), below is the dts of u-boot:
/*
* (C) Copyright 2020 Radxa
*/
/dts-v1/;
#include "rk3328.dtsi"
/ {
model = "Radxa Rockpi E";
compatible = "radxa,rockpie", "rockchip,rk3328";
chosen {
stdout-path = &uart2;
};
gmac_clkin: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac_clkin";
#clock-cells = <0>;
};
vcc3v3_sdmmc: sdmmc-pwren {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sdmmc";
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0m1_gpio>;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_io>;
};
vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
compatible = "regulator-fixed";
enable-active-high;
regulator-name = "vcc5v0_host_xhci";
gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&cpu1 {
cpu-supply = <&vdd_arm>;
};
&cpu2 {
cpu-supply = <&vdd_arm>;
};
&cpu3 {
cpu-supply = <&vdd_arm>;
};
&saradc {
status = "okay";
};
&uart2 {
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp;
max-frequency = <150000000>;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
supports-sd;
vmmc-supply = <&vcc3v3_sdmmc>;
status = "okay";
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
supports-emmc;
disable-wp;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
vmmc-supply = <&vcc_io>;
vqmmc-supply = <&vcc_18emmc>;
status = "okay";
};
&gmac2io {
phy-supply = <&vcc_io>;
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
pinctrl-names = "default";
pinctrl-0 = <&rgmiim1_pins>;
tx_delay = <0x26>;
rx_delay = <0x11>;
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb20_otg {
status = "okay";
};
&i2c1 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <168>;
i2c-scl-falling-time-ns = <4>;
status = "okay";
rk805: pmic@18 {
compatible = "rockchip,rk805";
status = "okay";
reg = <0x18>;
interrupt-parent = <&gpio2>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
gpio-controller;
#gpio-cells = <2>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-ramp-delay = <6001>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vdd_arm: DCDC_REG2 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-ramp-delay = <6001>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_io: DCDC_REG4 {
regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vdd_18: LDO_REG1 {
regulator-name = "vdd_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_18emmc: LDO_REG2 {
regulator-name = "vcc_18emmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_10: LDO_REG3 {
regulator-name = "vdd_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
};
};
};
&io_domains {
status = "okay";
vccio1-supply = <&vcc_io>;
vccio2-supply = <&vcc_18emmc>;
vccio3-supply = <&vcc_io>;
vccio4-supply = <&vcc_io>;
vccio5-supply = <&vcc_io>;
vccio6-supply = <&vcc_io>;
pmuio-supply = <&vcc_io>;
};
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins =
<2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; /* gpio2_a6 */
};
};
};
And there is the log when booting at the stage of u-boot:
```
U-Boot TPL 2020.04 (May 10 2020 - 06:47:07)
spl_early_init
rk3328_dmc_init phy ff400000 pctrl ff780000 grf ff100000 cru ff440000 msch ff720000 ddr_grf ff798000
Starting SDRAM initialization...
DDR3, 333MHz
BW=32 Col=10 Bk=8 CS0 Row=14 CS=1 Die BW=16 Size=512MB
SPL malloc() before relocation used 0x5e8 bytes (1 KB)
>>TPL: board_init_r()
spl_init
Trying to boot from BOOTROM
Returning to boot ROM...
<debug_uart>
spl:debug uart enabled in board_init_f
spl_early_init
clk_set_defaults()
clk_set_default_parents: could not read assigned-clock-parents for 3fc030
ofnode_read_prop: assigned-clock-rates: <not found>
fdtdec_get_addr_size_auto_parent: na=2, ns=2, fdtdec_get_addr_size_fixed: reg: addr=00000000x
ofnode_read_u32: reg-offset: (not found)
ofnode_read_u32: reg-shift: x (2)
ofnode_read_u32: reg-io-width: x (4)
fdtdec_get_int: #clock-cells: x (1)
fdtdec_get_addr_size_auto_parent: na=2, ns=2, fdtdec_get_addr_size_fixed: reg: addr=00000000x
clk_set_defaults(clock-controller@ff440000)
clk_set_default_parents: could not read assigned-clock-parents for 3fc2c0
ofnode_read_prop: assigned-clock-rates: <not found>
PLL at ff440000: fbdiv=75, refdiv=1, postdiv1=3, postdiv2=1, vco=1800000 khz, output=600000 khz
PLL at ff440060: fbdiv=96, refdiv=1, postdiv1=4, postdiv2=1, vco=2304000 khz, output=576000 khz
PLL at ff440040: fbdiv=99, refdiv=2, postdiv1=2, postdiv2=1, vco=1188000 khz, output=594000 khz
clk_set_defaults(clock-controller@ff440000)
clk_set_default_parents: could not read assigned-clock-parents for 3fc2c0
ofnode_read_prop: assigned-clock-rates: <not found>
clk_of_xlate_default(clk=3fbd78)
clk_request(dev=3fc2c0, clk=3fbd78)
clk_get_rate(clk=3fbd78)
ofnode_read_u32: clock-frequency: x (24000000)
clk_set_defaults(serial@ff130000)
clk_set_default_parents: could not read assigned-clock-parents for 3fc1d0
ofnode_read_prop: assigned-clock-rates: <not found>
U-Boot SPL 2020.04 (May 10 2020 - 06:47:07 +0000)
SPL malloc() before relocation used 0xbd0 bytes (2 KB)
>>SPL: board_init_r()
spl_init
board_spl_was_booted_from: brom_bootdevice_id 5 maps to '/rksdmmc@ff500000'
fdtdec_get_addr_size_auto_parent: na=2, ns=2, fdtdec_get_addr_size_fixed: reg: addr=00000000x
ofnode_read_u32: bus-width: x (4)
ofnode_read_bool: non-removable: false
ofnode_read_u32: fifo-depth: x (256)
ofnode_read_bool: fifo-mode: false
ofnode_read_bool: u-boot,spl-fifo-mode: true
ofnode_read_u32_array: clock-freq-min-max: fdtdec_get_int_array: clock-freq-min-max
get_prop_check_min_len: clock-freq-min-max
ofnode_read_u32: max-frequency: x (150000000)
clk_set_defaults(rksdmmc@ff500000)
clk_set_default_parents: could not read assigned-clock-parents for 3fc468
ofnode_read_prop: assigned-clock-rates: <not found>
fdtdec_get_int: #clock-cells: x (1)
clk_of_xlate_default(clk=3ff0000)
clk_request(dev=3fc2c0, clk=3ff0000)
clk_set_rate(clk=3ff0000, rate=400000)
fdtdec_get_addr_size_auto_parent: na=2, ns=2, fdtdec_get_addr_size_fixed: reg: addr=00000000x
ofnode_read_u32: bus-width: x (8)
ofnode_read_bool: non-removable: true
ofnode_read_u32: fifo-depth: x (256)
ofnode_read_bool: fifo-mode: false
ofnode_read_bool: u-boot,spl-fifo-mode: true
ofnode_read_u32_array: clock-freq-min-max: fdtdec_get_int_array: clock-freq-min-max
get_prop_check_min_len: clock-freq-min-max
ofnode_read_u32: max-frequency: x (150000000)
clk_set_defaults(rksdmmc@ff520000)
clk_set_default_parents: could not read assigned-clock-parents for 3fc790
ofnode_read_prop: assigned-clock-rates: <not found>
fdtdec_get_int: #clock-cells: x (1)
clk_of_xlate_default(clk=3ff00a8)
clk_request(dev=3fc2c0, clk=3ff00a8)
clk_set_rate(clk=3ff00a8, rate=400000)
Trying to boot from MMC1
blk_find_device: if_type=6, devnum=0: rks...@ff500000.blk, 6, 0
clock is disabled (0Hz)
Buswidth = 0, clock: 0
Buswidth = 1, clock: 0
clock is enabled (400000Hz)
Buswidth = 1, clock: 400000
Sending CMD0
Sending CMD8
dwmci_send_cmd: Response Timeout.
Sending CMD55
Sending CMD41
Sending CMD55
dwmci_send_cmd: Response Timeout.
Sending CMD0
Sending CMD1
dwmci_send_cmd: Response Timeout.
Card did not respond to voltage select!
spl: mmc init failed with error: -95
Trying to boot from MMC1
blk_find_device: if_type=6, devnum=0: rks...@ff500000.blk, 6, 0
clock is disabled (0Hz)
Buswidth = 1, clock: 0
Buswidth = 1, clock: 0
clock is enabled (400000Hz)
Buswidth = 1, clock: 400000
Sending CMD0
Sending CMD8
Sending CMD55
Sending CMD41
Sending CMD55
dwmci_send_cmd: Response Timeout.
Sending CMD0
Sending CMD1
dwmci_send_cmd: Response Timeout.
Card did not respond to voltage select!
spl: mmc init failed with error: -95
Trying to boot from MMC2
blk_find_device: if_type=6, devnum=1: rks...@ff500000.blk, 6, 0
blk_find_device: if_type=6, devnum=1: rks...@ff520000.blk, 6, 1
clock is disabled (0Hz)
Buswidth = 0, clock: 0
Buswidth = 1, clock: 0
clock is enabled (400000Hz)
Buswidth = 1, clock: 400000
Sending CMD0
Sending CMD8
dwmci_send_cmd: Response Timeout.
Sending CMD55
dwmci_send_cmd: Response Timeout.
Sending CMD0
Sending CMD1
dwmci_send_cmd: Response Timeout.
Card did not respond to voltage select!
spl: mmc init failed with error: -95
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
<debug_uart>
U-Boot TPL 2020.04 (May 10 2020 - 06:47:07)
spl_early_init
rk3328_dmc_init phy ff400000 pctrl ff780000 grf ff100000 cru ff440000 msch ff720000 ddr_grf ff798000
Starting SDRAM initialization...
DDR3, 333MHz
BW=32 Col=10 Bk=8 CS0 Row=14 CS=1 Die BW=16 Size=512MB
SPL malloc() before relocation used 0x5e8 bytes (1 KB)
>>TPL: board_init_r()
spl_init
Trying to boot from BOOTROM
Returning to boot ROM...
<debug_uart>
spl:debug uart enabled in board_init_f
spl_early_init
clk_set_defaults()
clk_set_default_parents: could not read assigned-clock-parents for 3fc030
ofnode_read_prop: assigned-clock-rates: <not found>
fdtdec_get_addr_size_auto_parent: na=2, ns=2, fdtdec_get_addr_size_fixed: reg: addr=00000000x
ofnode_read_u32: reg-offset: (not found)
ofnode_read_u32: reg-shift: x (2)
ofnode_read_u32: reg-io-width: x (4)
fdtdec_get_int: #clock-cells: x (1)
fdtdec_get_addr_size_auto_parent: na=2, ns=2, fdtdec_get_addr_size_fixed: reg: addr=00000000x
clk_set_defaults(clock-controller@ff440000)
clk_set_default_parents: could not read assigned-clock-parents for 3fc2c0
ofnode_read_prop: assigned-clock-rates: <not found>
PLL at ff440000: fbdiv=75, refdiv=1, postdiv1=3, postdiv2=1, vco=1800000 khz, output=600000 khz
PLL at ff440060: fbdiv=96, refdiv=1, postdiv1=4, postdiv2=1, vco=2304000 khz, output=576000 khz
PLL at ff440040: fbdiv=99, refdiv=2, postdiv1=2, postdiv2=1, vco=1188000 khz, output=594000 khz
clk_set_defaults(clock-controller@ff440000)
clk_set_default_parents: could not read assigned-clock-parents for 3fc2c0
ofnode_read_prop: assigned-clock-rates: <not found>
clk_of_xlate_default(clk=3fbd78)
clk_request(dev=3fc2c0, clk=3fbd78)
clk_get_rate(clk=3fbd78)
ofnode_read_u32: clock-frequency: x (24000000)
clk_set_defaults(serial@ff130000)
clk_set_default_parents: could not read assigned-clock-parents for 3fc1d0
ofnode_read_prop: assigned-clock-rates: <not found>
U-Boot SPL 2020.04 (May 10 2020 - 06:47:07 +0000)
SPL malloc() before relocation used 0xbd0 bytes (2 KB)
>>SPL: board_init_r()
spl_init
board_spl_was_booted_from: brom_bootdevice_id 5 maps to '/rksdmmc@ff500000'
fdtdec_get_addr_size_auto_parent: na=2, ns=2, fdtdec_get_addr_size_fixed: reg: addr=00000000x
ofnode_read_u32: bus-width: x (4)
ofnode_read_bool: non-removable: false
ofnode_read_u32: fifo-depth: x (256)
ofnode_read_bool: fifo-mode: false
ofnode_read_bool: u-boot,spl-fifo-mode: true
ofnode_read_u32_array: clock-freq-min-max: fdtdec_get_int_array: clock-freq-min-max
get_prop_check_min_len: clock-freq-min-max
ofnode_read_u32: max-frequency: x (150000000)
clk_set_defaults(rksdmmc@ff500000)
clk_set_default_parents: could not read assigned-clock-parents for 3fc468
ofnode_read_prop: assigned-clock-rates: <not found>
fdtdec_get_int: #clock-cells: x (1)
clk_of_xlate_default(clk=3ff0000)
clk_request(dev=3fc2c0, clk=3ff0000)
clk_set_rate(clk=3ff0000, rate=400000)
fdtdec_get_addr_size_auto_parent: na=2, ns=2, fdtdec_get_addr_size_fixed: reg: addr=00000000x
ofnode_read_u32: bus-width: x (8)
ofnode_read_bool: non-removable: true
ofnode_read_u32: fifo-depth: x (256)
ofnode_read_bool: fifo-mode: false
ofnode_read_bool: u-boot,spl-fifo-mode: true
ofnode_read_u32_array: clock-freq-min-max: fdtdec_get_int_array: clock-freq-min-max
get_prop_check_min_len: clock-freq-min-max
ofnode_read_u32: max-frequency: x (150000000)
clk_set_defaults(rksdmmc@ff520000)
clk_set_default_parents: could not read assigned-clock-parents for 3fc790
ofnode_read_prop: assigned-clock-rates: <not found>
fdtdec_get_int: #clock-cells: x (1)
clk_of_xlate_default(clk=3ff00a8)
clk_request(dev=3fc2c0, clk=3ff00a8)
clk_set_rate(clk=3ff00a8, rate=400000)
Trying to boot from MMC1
blk_find_device: if_type=6, devnum=0: rks...@ff500000.blk, 6, 0
clock is disabled (0Hz)
Buswidth = 0, clock: 0
Buswidth = 1, clock: 0
clock is enabled (400000Hz)
Buswidth = 1, clock: 400000
Sending CMD0
Sending CMD8
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD2
Sending CMD3
Sending CMD9
Sending CMD7
Sending CMD55
Sending CMD51
Sending CMD55
Sending CMD6
Buswidth = 4, clock: 400000
clock is enabled (25000000Hz)
Buswidth = 4, clock: 25000000
clk_set_rate(clk=3ff0000, rate=25000000)
spl: mmc boot mode: raw
blk_find_device: if_type=6, devnum=0: rks...@ff500000.blk, 6, 0
Sending CMD16
Sending CMD17
dwmci_data_transfer: DATA ERROR!
hdr read sector 4000, count=0
mmc_load_image_raw_sector: mmc block read error
spl: mmc boot mode: fs
Trying to boot from MMC1
spl: mmc boot mode: raw
blk_find_device: if_type=6, devnum=0: rks...@ff500000.blk, 6, 0
Sending CMD16
dwmci_send_cmd: Response Timeout.
Sending CMD16
dwmci_send_cmd: Response Timeout.
Sending CMD16
dwmci_send_cmd: Response Timeout.
Sending CMD16
dwmci_send_cmd: Response Timeout.
Sending CMD16
dwmci_send_cmd: Response Timeout.
Sending CMD16
dwmci_send_cmd: Response Timeout.
hdr read sector 4000, count=0
mmc_load_image_raw_sector: mmc block read error
spl: mmc boot mode: fs
Trying to boot from MMC2
spl: mmc boot mode: raw
blk_find_device: if_type=6, devnum=0: rks...@ff500000.blk, 6, 0
Sending CMD16
dwmci_send_cmd: Response Timeout.
Sending CMD16
dwmci_send_cmd: Response Timeout.
Sending CMD16
dwmci_send_cmd: Response Timeout.
Sending CMD16
dwmci_send_cmd: Response Timeout.
Sending CMD16
dwmci_send_cmd: Response Timeout.
Sending CMD16
dwmci_send_cmd: Response Timeout.
hdr read sector 4000, count=0
mmc_load_image_raw_sector: mmc block read error
spl: mmc boot mode: fs
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
```
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