Re: riscv: add support for SBI Supervisor Software Events

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May 16, 2025, 3:54:16 PMMay 16

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Dear submitter,

Thank you for submitting the patches to the Linux RISC-V mailing list.
This is a CI test results with your patch series:
PW Link:https://patchwork.kernel.org/project/linux-riscv/list/?series=963680

---Test result---
Test Summary:
Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions" build-rv32-defconfig PASS 106.53 seconds
Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions" build-rv64-clang-allmodconfig PASS 987.60 seconds
Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions" build-rv64-gcc-allmodconfig PASS 1280.96 seconds
Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions" build-rv64-nommu-k210-defconfig PASS 20.62 seconds
Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions" build-rv64-nommu-k210-virt PASS 21.65 seconds
Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions" checkpatch WARNING 1.54 seconds
Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions" dtb-warn-rv64 PASS 67.03 seconds
Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions" header-inline PASS 0.24 seconds
Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions" kdoc PASS 0.91 seconds
Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions" module-param PASS 0.25 seconds
Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions" verify-fixes PASS 0.22 seconds
Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions" verify-signedoff PASS 0.30 seconds
Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension" build-rv32-defconfig PASS 106.26 seconds
Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension" build-rv64-clang-allmodconfig PASS 1920.89 seconds
Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension" build-rv64-gcc-allmodconfig PASS 2436.59 seconds
Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension" build-rv64-nommu-k210-defconfig PASS 20.52 seconds
Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension" build-rv64-nommu-k210-virt PASS 21.33 seconds
Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension" checkpatch WARNING 4.02 seconds
Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension" dtb-warn-rv64 PASS 67.79 seconds
Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension" header-inline PASS 0.25 seconds
Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension" kdoc PASS 0.87 seconds
Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension" module-param PASS 0.27 seconds
Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension" verify-fixes PASS 0.22 seconds
Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension" verify-signedoff PASS 0.31 seconds
Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support" build-rv32-defconfig PASS 105.88 seconds
Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support" build-rv64-clang-allmodconfig ERROR 997.27 seconds
Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support" build-rv64-gcc-allmodconfig ERROR 1289.50 seconds
Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support" build-rv64-nommu-k210-defconfig PASS 21.03 seconds
Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support" build-rv64-nommu-k210-virt PASS 21.55 seconds
Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support" checkpatch WARNING 3.87 seconds
Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support" dtb-warn-rv64 PASS 67.45 seconds
Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support" header-inline PASS 1.99 seconds
Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support" kdoc PASS 1.41 seconds
Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support" module-param PASS 0.33 seconds
Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support" verify-fixes PASS 0.89 seconds
Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support" verify-signedoff PASS 0.30 seconds
Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event" build-rv32-defconfig PASS 106.34 seconds
Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event" build-rv64-clang-allmodconfig PASS 1006.10 seconds
Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event" build-rv64-gcc-allmodconfig PASS 1290.97 seconds
Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event" build-rv64-nommu-k210-defconfig PASS 20.89 seconds
Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event" build-rv64-nommu-k210-virt PASS 21.44 seconds
Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event" checkpatch WARNING 2.14 seconds
Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event" dtb-warn-rv64 PASS 67.34 seconds
Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event" header-inline PASS 0.24 seconds
Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event" kdoc PASS 0.85 seconds
Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event" module-param PASS 0.27 seconds
Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event" verify-fixes PASS 0.22 seconds
Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event" verify-signedoff PASS 0.29 seconds

Details
##############################
Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions"
Test: checkpatch - WARNING
Desc: Runs checkpatch.pl on the patch
Output:
CHECK: Prefer using the BIT macro
#78: FILE: arch/riscv/include/asm/sbi.h:447:
+#define SBI_SSE_ATTR_CONFIG_ONESHOT (1 << 0)

CHECK: Prefer using the BIT macro
#80: FILE: arch/riscv/include/asm/sbi.h:449:
+#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SPP (1 << 0)

CHECK: Prefer using the BIT macro
#81: FILE: arch/riscv/include/asm/sbi.h:450:
+#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SPIE (1 << 1)

CHECK: Prefer using the BIT macro
#82: FILE: arch/riscv/include/asm/sbi.h:451:
+#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_HSTATUS_SPV (1 << 2)

CHECK: Prefer using the BIT macro
#83: FILE: arch/riscv/include/asm/sbi.h:452:
+#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_HSTATUS_SPVP (1 << 3)

CHECK: Prefer using the BIT macro
#94: FILE: arch/riscv/include/asm/sbi.h:463:
+#define SBI_SSE_EVENT_PLATFORM (1 << 14)

CHECK: Prefer using the BIT macro
#95: FILE: arch/riscv/include/asm/sbi.h:464:
+#define SBI_SSE_EVENT_GLOBAL (1 << 15)

total: 0 errors, 0 warnings, 7 checks, 89 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
mechanically convert to the typical style using --fix or --fix-inplace.

Commit b6a193d93e26 ("riscv: add SBI SSE extension definitions") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 0 warnings, 7 checks, 89 lines checked
CHECK: Prefer using the BIT macro

##############################
Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension"
Test: checkpatch - WARNING
Desc: Runs checkpatch.pl on the patch
Output:
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#119:
new file mode 100644

CHECK: Alignment should match open parenthesis
#164: FILE: arch/riscv/include/asm/sse.h:41:
+asmlinkage void do_sse(struct sse_event_arch_data *arch_evt,
+ struct pt_regs *reg);

WARNING: usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc
#250: FILE: arch/riscv/kernel/asm-offsets.c:523:
+ DEFINE(NR_CPUS, NR_CPUS);

CHECK: No space is necessary after a cast
#386: FILE: arch/riscv/kernel/sse.c:128:
+ (unsigned long) handle_sse, (unsigned long) arch_evt,

total: 0 errors, 2 warnings, 2 checks, 454 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
mechanically convert to the typical style using --fix or --fix-inplace.

Commit 0a09f5d86123 ("riscv: add support for SBI Supervisor Software Events extension") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 2 warnings, 2 checks, 454 lines checked
CHECK: Alignment should match open parenthesis
CHECK: No space is necessary after a cast
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
WARNING: usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc

##############################
Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support"
Test: build-rv64-clang-allmodconfig - ERROR
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Output:
Redirect to /build/tmp.X6LHAo52Cr and /build/tmp.PxnB52Z4L0
Tree base:
0a09f5d861238 ("riscv: add support for SBI Supervisor Software Events extension")
Building the whole tree with the patch
Building the tree before the patch
Building the tree with the patch
New errors added:
--- /build/tmp.F7yXwhUVqO 2025-05-16 18:47:46.729220092 +0000
+++ /build/tmp.rFN4UzdzI1 2025-05-16 18:47:46.732220086 +0000
@@ -117,0 +118 @@
+ 1 /build/tmpe9ouq6l9/drivers/firmware/riscv/riscv_sse.c:395:31: warning: variable 'reg_evt' set but not used [-Wunused-but-set-variable]
Per-file breakdown
error/warning file pre:
error/warning file post:
pre: 118 post: 119

real 13m27.406s
user 503m48.835s
sys 98m57.881s

real 1m32.125s
user 3m6.796s
sys 2m11.070s

real 1m28.459s
user 2m49.216s
sys 2m8.484s
##############################
Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support"
Test: build-rv64-gcc-allmodconfig - ERROR
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Output:
Redirect to /build/tmp.bDcV4iITWI and /build/tmp.lPAid6QjfD
Tree base:
0a09f5d861238 ("riscv: add support for SBI Supervisor Software Events extension")
Building the whole tree with the patch
Building the tree before the patch
Building the tree with the patch
New errors added:
--- /build/tmp.VZJEs99C1a 2025-05-16 19:09:16.741736133 +0000
+++ /build/tmp.SDGvankwIL 2025-05-16 19:09:16.745736126 +0000
@@ -117,0 +118 @@
+ 1 /build/tmpe9ouq6l9/drivers/firmware/riscv/riscv_sse.c:395:38: warning: variable 'reg_evt' set but not used [-Wunused-but-set-variable]
Per-file breakdown
error/warning file pre:
pre: 117 post: 118

real 17m52.839s
user 673m54.194s
sys 116m44.101s

real 1m46.868s
user 3m23.876s
sys 2m7.310s

real 1m39.776s
user 2m50.413s
sys 2m1.493s
##############################
Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support"
Test: checkpatch - WARNING
Desc: Runs checkpatch.pl on the patch
Output:
WARNING: Co-developed-by and Signed-off-by: name/email do not match
#14:
Co-developed-by: Himanshu Chauhan <hcha...@ventanamicro.com>
Signed-off-by: Clément Léger <cle...@rivosinc.com>

WARNING: 'ment' may be misspelled - perhaps 'meant'?
#55: FILE: MAINTAINERS:20908:
+M: Clément Léger <cle...@rivosinc.com>
^^^^

CHECK: Alignment should match open parenthesis
#261: FILE: drivers/firmware/riscv/riscv_sse.c:137:
+ sret = sbi_ecall(SBI_EXT_SSE, SBI_SSE_EVENT_ATTR_READ, evt,
+ attr_id, 1, phys, 0, 0);

CHECK: Alignment should match open parenthesis
#284: FILE: drivers/firmware/riscv/riscv_sse.c:160:
+ sret = sbi_ecall(SBI_EXT_SSE, SBI_SSE_EVENT_ATTR_WRITE, evt,
+ attr_id, 1, phys, 0, 0);

CHECK: Blank lines aren't necessary after an open brace '{'
#537: FILE: drivers/firmware/riscv/riscv_sse.c:413:
+ for_each_online_cpu(cpu) {
+

CHECK: Blank lines aren't necessary before a close brace '}'
#538: FILE: drivers/firmware/riscv/riscv_sse.c:414:
+
+ }

CHECK: Blank lines aren't necessary after an open brace '{'
#706: FILE: drivers/firmware/riscv/riscv_sse.c:582:
+ if (!sse_event_is_global(event->evt_id)) {
+

CHECK: Alignment should match open parenthesis
#764: FILE: drivers/firmware/riscv/riscv_sse.c:640:
+static int sse_reboot_notifier(struct notifier_block *nb, unsigned long action,
+ void *data)

CHECK: Please don't use multiple blank lines
#882: FILE: include/linux/riscv_sse.h:56:
+
+

total: 0 errors, 2 warnings, 7 checks, 814 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
mechanically convert to the typical style using --fix or --fix-inplace.

Commit 5c9feca65578 ("drivers: firmware: add riscv SSE support") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 2 warnings, 7 checks, 814 lines checked
CHECK: Alignment should match open parenthesis
CHECK: Blank lines aren't necessary after an open brace '{'
CHECK: Blank lines aren't necessary before a close brace '}'
CHECK: Please don't use multiple blank lines
WARNING: 'ment' may be misspelled - perhaps 'meant'?
WARNING: Co-developed-by and Signed-off-by: name/email do not match

##############################
Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event"
Test: checkpatch - WARNING
Desc: Runs checkpatch.pl on the patch
Output:
WARNING: please write a help paragraph that fully describes the config symbol with at least 4 lines
#31: FILE: drivers/perf/Kconfig:108:
+config RISCV_PMU_SSE
+ depends on RISCV_PMU && RISCV_SSE
+ bool "RISC-V PMU SSE events"
+ default n
+ help
+ Say y if you want to use SSE events to deliver PMU interrupts. This
+ provides a way to profile the kernel at any level by using NMI-like
+ SSE events.
+

CHECK: Prefer kernel type 'u32' over 'uint32_t'
#169: FILE: drivers/perf/riscv_pmu_sbi.c:1066:
+static int pmu_sbi_ovf_sse_handler(uint32_t evt, void *arg,

CHECK: Alignment should match open parenthesis
#170: FILE: drivers/perf/riscv_pmu_sbi.c:1067:
+static int pmu_sbi_ovf_sse_handler(uint32_t evt, void *arg,
+ struct pt_regs *regs)

CHECK: Alignment should match open parenthesis
#187: FILE: drivers/perf/riscv_pmu_sbi.c:1084:
+ evt = sse_event_register(SBI_SSE_EVENT_LOCAL_PMU_OVERFLOW, 0,
+ pmu_sbi_ovf_sse_handler, hw_events);

total: 0 errors, 1 warnings, 3 checks, 200 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
mechanically convert to the typical style using --fix or --fix-inplace.

Commit 533582005501 ("perf: RISC-V: add support for SSE event") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 1 warnings, 3 checks, 200 lines checked
CHECK: Alignment should match open parenthesis
CHECK: Prefer kernel type 'u32' over 'uint32_t'
WARNING: please write a help paragraph that fully describes the config symbol with at least 4 lines