interest in Linux-on-Linux-VexRiscV for ASIC?

[Drew Fustini]

I brought this up on #litex IRC but thought I would raise it to this
mailing list too.

Is anyone interested in the idea of an ASIC based on
Linux-on-Linux-VexRiscV with SDRAM interface?

I'm not sure how the emulator would work in an ASIC situation though.

Thanks,
Drew

[Tim 'mithro' Ansell]

Taking an FPGA based design and converting it into an ASIC is not a small project. My random thought is that it would probably need a full time team of ~3 engineers for about 1-2 years and ~2m in funding at a minimum.

Tim 'mithro' Ansell

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[Florent Kermarrec]

For a fully synchronous SoC with simple IOs/Memories the amount ASIC specific work can probably be reduced a lot. I would say the cost greatly depends of the aim of this:

- 1) Is it just to demonstrate that it's possible to create an ASIC with this flow and test this on a minimal system with low perfs.

- 2) Is it to create something with more reasonable perfs (high CPU clocks, good DRAM performance, etc...).

I would say 1) has more sense than 2) since even with reasonable perfs this would still be a lot less performant/efficient than the SoCs were are using in our everyday life and i wouldn't risk doing 2) without first doing 1).

For the costs, that would be interesting to know how much creating an ASIC around PicoRV32/PicoSoC has cost: https://content.riscv.org/wp-content/uploads/2017/12/Wed-1142-RISCV-Tim-Edwards.pdf,

the work here for 1) would be very similar.

Regards,

Florent

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[Staf Verhaegen]

(Resend, hopefully now on maillist)

I agree with Florent,

The question from Drew came after we met in Istanbul. Currently you need the high cost SiFive development board or a chip with only on-chip 8MB SRAM memory to run Linux on an open source (RISC-V) ASIC.

Proposal is to use my Chips4Makers beta run to have a first open source low-cost, low-performance Linux capable chip. Currently tape-out is planned in July; costs are given on the linked page.

I am using 0.35um and I expect performance to be similar to current FPGA performance (around 100MHz; to be verified). Also due to limited space we may need to limit cache or even make it cache-less. On an ASIC logic takes up relative less space than on-chip RAM when comparing to FPGA.

As explained in my ORConf presentation I did some test tape-outs. I was using Qflow for them; for the beta tape-out the plan is to use Coriolis. They already are using a cache-less VexRisc as a CI testbench for their flow. They have the clock tree synthesis working but there is still work to be done for other high fan-out networks like a reset etc. Jean-Paul Chaput of LIP6 said he would work on that and have it ready for the tape-out. If not, tape-out may need to be delayed (they run every two months).

Alternatively I would love to see somebody else diving into OpenROAD as alternative flow; I won't have bandwidth for the July tape-out for that.

I have the chips but still need to test them. The packaging and bonding seems to have gone fine and I could sort the ESD test chip from Z80/MOS6502. If somebody fancies testing a Z80/MOS6502 I am all ears.

I think the main work to be done is how to define the ASIC platform in LiteX. Personally I have been mainly developing in nMigen and have ideas on how to define the platform there. Platform definition has changed quite a lot between Migen and nMigen so that needs to be ported.

I think two things need to be implemented in LiteX:

- I want to include a JTAG interface in the platform and thus also on every Chips4Makers. Idea is that people would make a .svf file that they would test in FPGA or in simulation (cocotb, verilator, ...) and that .svf would then be used to test the chip after manufacturing. Chips4Makers customers would only receive chips that pass this .svf test. This may change in the future if open source scan chain insertion and ATPG (automatic test pattern generating) software becomes available.

- The LiteX platform should allow to change the functionality of the pins: input and/or output, pull-up/pull-down, drive strength, ... It have a fixed number of configurable pins.

Currently only digital IO will be present but in future it could also include differential signaling (LVDS, ...), DDRn etc.

I have test tape-out in another project in May and will be working full-time on Chips4Makers beta after that.

greets,

Staf.

Florent Kermarrec schreef op vr 20-03-2020 om 09:13 [+0100]:

[Drew Fustini]

Should we revisit this topic in light of the Google+skywater 130nm shuttle?

-Drew 

[Saket Sinha]

Is anyone interested in the idea of an ASIC based on
Linux-on-Linux-VexRiscV with SDRAM interface?

I'm not sure how the emulator would work in an ASIC situation though.

Should we revisit this topic in light of the Google+skywater 130nm shuttle?

Any update here ?

Regards,

Saket Sinha

 

[Drew Fustini]

The impression I got talking to Tim and some others was that this was too ambitious for the Skywater 130nm shuttle run but I would love to hear if anyone is trying this!

Thanks

Drew 

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[Tim 'mithro' Ansell]

As I think I mentioned, the most likely pathway to success for doing a Linux capable design on SKY130 using LiteX would be to start with doing a microcontroller style system using LiteX. Once you are able to do microcontrollers designs using LiteX easily, then looking at doing Linux would be a logical next step.

I highly encourage a team to get together and try to make a range of LiteX based microcontrollers (from space optimized to performance optimized) for the November target. You don't have much time left, so get going right now! Doing multiple designs will also help you understand the correct trade offs around silicon usage verse performance when doing the more complicated Linux device. 

This will then put you in a good position when the next set of shuttle runs start happening. As well, things like the RPC DDR support and high speed IO on SKY130 will be much further along which gives a much more viable pathway to solve the memory requirement problem that a Linux SoC needs.

Hope that helps,

Tim 'mithro' Ansell

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[Saket Sinha]

Any update or follow up here ?

[Saket Sinha]

Any update here ?

[Drew Fustini]

My understanding is that the Google+eFabless+Skywater 130nm PDK is not capable of handling a Vexriscv core.  Future versions on a smaller process node might make this possible but there are no firm plans for that yet.

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[Tim 'mithro' Ansell]

On Tue, 16 Mar 2021 at 09:18, Drew Fustini <pdp7...@gmail.com> wrote:

My understanding is that the Google+eFabless+Skywater 130nm PDK is not capable of handling a Vexriscv core.  Future versions on a smaller process node might make this possible but there are no firm plans for that yet.

That is not really correct. The issue is the cost verse benefit ratio makes it not economically viable to invest heavily in at the moment. If you can find >10,000 people willing to pay >$30ish per IC that only has RPi 1-2 style performance, you could do a design right now.

There are multiple groups working on getting the cost per IC down and proving out the required interfacing IP at the same time (like USB3 / DDR / etc). There is plenty of basic work here that still could be done -- much of which doesn't need any experience with hardware. There is plenty of work around things like improving the documentation generation tooling, the CI system for testing changes and tracking improvements or even just packaging the tools to enable everyone to easily get started!

It should be noted that pretty much all work on improving Linux-on-Linux-VexRISCV on FPGAs helps the ASIC efforts too. If you are interested in contributing, you should start by actively starting to improve the FPGA space. Helping things like https://antmicro.com/blog/2020/05/multicore-vex-in-litex/ help make general capabilities better!

[Hasjim Williams]

At my dayjob, we could use a IC that has some ADC, some RF (for Bluetooth LE), a tiny bit of RAM and FLASH and a processor.

It wouldn't be a linux capable processor, but we could definitely satisfy the demand requirements probably on our own.

Crawl before you walk. And walk before you run.

However, I suspect that the mainstream ARM Cortex based processors would come in cheaper, because of volumes that they already do in IoT, and the qualification processes etc. 

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