Our client is looking for Design & Validation Engineer
Location: Austin, TX
Duration: 6 month contract
Rate: DOE
1 position for Design & Validation Engineer
Exhaustive hands-on experience in Verilog / System Verilog, Shell Scripting.
Experience on Altera Q-II flow, Cadence Build Gates / PKS Synthesis tool and Linux environment is highly desirable.
Design experience in PCIe, HDMI, HD-SDI, Image Processing Pipeline, DDR3C, H.264, XAUI, J2K Decoder etc. logic block is preferable.
If interested, please do reply with your updated resume along with the details requested below.
Current Location:
Availability:
Rate:
Interview contact number:
Regards
Anand
KRG Technologies Inc
Phone: 661 310 1202 | Fax: 661 257 9968
Email:an...@krgtech.com|URL:www.krgtech.com
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