RF Loopback
Brian Padalino
2. Register 0x08 [3-0] = '1'. TXMIX output connected to LNA1 path. make sure that for Rx path LNA1 is selected.
3. Register 0x7D [0] ='1'. LNA power down. To power up LNAS set register to '0'.
Ricardas Vadoklis
0x08 |
7
6
5
4
3–0 |
BBBYP: RX baseband bypass. If =1, RXTIA output is shorted to the output pins. If enabled, RXLPF and RXVGA2 should be disabled (powered down) 0 – default value. LBEN_LPFIN: BB loopback enable. If =1, TX BB loopback signal is connected to RXLPF input. If enabled, RXTIA should be disabled (powered down) 0 – default value. LBEN_VGA2IN: BB loopback enable. If =1, TX BB loopback signal is connected to RXVGA2 input. If enabled, LPF should be disabled (powered down). 0 – default value. LBEN_OPIN: BB loopback enable. If =1, TX BB loopback signal is connected to the RX output pins. If enabled, RXLPF and RXVGA2 should be disabled (powered down) 0 – default value. LBRFEN[3:0]: RF loop back control. When activated, LNAs should be disabled (powered down). 0 RF loopback disabled (default) 1 TXMIX output connected to LNA1 path 2 TXMIX output connected to LNA2 path 3 TXMIX output connected to LNA3 path 4-15 Reserved. Not valid for settings. Default: 00000000 |
0x7D | 7–4 3
2
1
0 | Not used PD_TIA_RXFE: TIA (RXVGA1) power down. 0 – block active (default) 1 – block inactive PD_MXLOB_RXFE: Mixer LO buffer power down. 0 – block active (default) 1 – block inactive PD_MIX_RXFE: Mixer power down. 0 – block active (default) 1 – block inactive PD_LNA_RXFE: LNA power down. 0 – block active (default) 1 – block inactive Default: 00000000 |
Ricardas Vadoklis
The process for getting the LMS-6002D to be in RF loopback is as follows:
1. Register 0x0B [0] = '1' .RF loop back switch powered up.
2. Register 0x08 [3-0] = '1'. TXMIX output connected to LNA1 path. make sure that for Rx path LNA1 is selected.
3. Register 0x7D [0] ='1'. LNA power down. To power up LNA set register to '0'.
4. Register 0x70 [1] = '1'. Decode test registers to be able to decode 0x7D LNA power down.There seem to be some other RESERVED bits in the register map. Can you shed some light on some of the other RESERVED bits that are around?I am mainly curious for verification and testing of boards in an automated fashion.
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Alexander Chemeris
Alexander Chemeris
According to my testing, bit 0 from register 0x0B has no effect on RF
loopback. I.e. it works no matter whether this bit is set or not. Is
there some catch which I'm missing?
The procedure I found to work for me is following:
0. (optionally) Disable PAs. This is not strictly necessary, but reduce noise.
1. Register 0x75 LNASEL_RXFE[1:0] = lna_num: Selects the active LNA.
2. Register 0x25 SELOUT[1:0] = lna_num: Select output buffer in RX PLL
3. Register 0x7D[0] = 1: Power down LNAs with a test mode register
4. Register 0x70[1] = 1: Enable test mode for RX FE for the previous
setting to take effect
5. This has no effect according to my testing: Register 0x0B PD[0] =
1: power up RF loopback
6. Register 0x08 LBRFEN[3:0] = lna_num: Select RXMIX input for loopback
Also, according to the loopback connections diagram, RF loopback goes
through AUX PA. But it seems that PD_DRVAUX (register 0x44) doesn't
have any effect on the RF loopback operation. Does that mean that AUX
PA is enabled automatically when RF loopback is enabled?
Ricardas Vadoklis
Yes, the output pins means the analogue Rx out.
There is only one way, to bypass LNA. But in this case you will have the buffer before RXMIX.
Best Regards, Ricardas Vadoklis,
Ricardas Vadoklis
In normal operation register 0x0B[0] by default is set '1', which means that, the RF loopback switch is powered up. The switch will be power down when the register 0x05 [7] is set to '1' ( Direct signals mode).
Regarding the AUX PA, see updated 0x44 register description below:
|
0x44 |
7-5 4-3
2
1
0 |
Not used PA_EN[2:0]: VGA2 power amplifier (TX output) selection PA_EN[2:1] PA1 PA2 =========================== 00 OFF OFF 01 ON OFF (default) 10 OFF ON 11 OFF OFF PA_EN[0]: AUXPA, auxiliary (RF loop back) PA power down, mask set v1, not used in v0. 0 – powered up (default) 1 – powered down PD_DRVAUX: AUXPA, auxiliary (RF loop back) PA power down (available in test mode only) mask set v0, not used in v1. 0 – powered up 1 – powered down (default) PD_PKDET: Power down for envelop/peak detectors (available in test mode only) mask set v0, not used in v1. 0 – powered up 1 – powered down (default) Default: 00001011 |
Mask set v0 and mask set v1 indicates the chip version. To check version use register 0x0E:
|
0x0E
|
7-0 |
Mask set version 00000000 – v0 00000001 – v1 Read only |
Most likely you will have the version v1, as it went to production 2 years ago.
Best Regards, Ricardas Vadoklis,
Alexander Chemeris
Ricardas Vadoklis
I hope soon. We need to finalize document before we release it for public domain.
Best Regards, Ricardas Vadoklis,