Using lower than recommended PLL reference clock

[Med]

Dear technical support team,

I need to use LMS6002D with a lower that recommended PLL Reference Clock (e.g. 19 MHz).

I like to know what would be the possible effects on the performance of the chip if the PLL Reference Clock frequency goes below 23 MHz recommended in the datasheet?

Thanks in advance for your help

[Srdjan Milenkovic]

Hi Med,

Both your questions have been just answered on the forum. Please check there.

Best regards, Srdjan

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[Mehrdad Ghanad]

Hi Srdjan,

Many thanks, it was very helpful for my design.

Best regards

Mehrdad

On Fri, Sep 29, 2017 at 12:00 PM, Srdjan Milenkovic <s.mile...@limemicro.com> wrote:

Hi Med,

Both your questions have been just answered on the forum. Please check there.

Best regards, Srdjan

 

On 29/09/2017 11:27, Med wrote:

Dear technical support team,

I need to use LMS6002D with a lower that recommended PLL Reference Clock (e.g. 19 MHz).

I like to know what would be the possible effects on the performance of the chip if the PLL Reference Clock frequency goes below 23 MHz recommended in the datasheet?

Thanks in advance for your help

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——————————————————

Mehrdad Ghanad
RF Design Engineer

mghanad@astrocast.net  

Astrocast SA

EPFL Innovation Park

Building L

Chemin de la Dent d'Oche 1B

1024 Ecublens, Switzerland

in...@astrocast.net

www.astrocast.net

[Med]

Hi Srdjan,

I am using the reference of 19.2 MHz and trying to lock the PLL to frequency of 1630 MHz, the integer divider value for this configuration NINT is 339, it seems that for the NINT values above 320, the PLL does not lock to the desired frequency.

In theory 9 bits is allocated to NINT and it can be as large as 511, but is there something related to the design of the chip that limits the maximum value of this divider?

Many thanks in advance for your help.

Best regards

Mehrdad

On Friday, September 29, 2017 at 12:00:24 PM UTC+2, Srdjan Milenkovic wrote:

Hi Med,

Both your questions have been just answered on the forum. Please check there.

Best regards, Srdjan

 

On 29/09/2017 11:27, Med wrote:

Dear technical support team,

I need to use LMS6002D with a lower that recommended PLL Reference Clock (e.g. 19 MHz).

I like to know what would be the possible effects on the performance of the chip if the PLL Reference Clock frequency goes below 23 MHz recommended in the datasheet?

Thanks in advance for your help

--
You received this message because you are subscribed to the Google Groups "Lime Microsystems open-source support channel" group.

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[Srdjan Milenkovic]

Hello Mehrdad,

Based on the previous emails, you are using LMS6002D device. In this case attached xls will give you the answers.

To summarize,  NINT min and max are determined by pulse swallow feedback divider design. In this particular case
    Nmin = 93, Nmax = 317

With the reference frequency of 19.2MHz, PLL does not provide continuous frequency range coverage as you can see in the attached. There are frequency gaps. Unfortunately, under your set up, required NINT=339 is out of range which means your target LO = 1630 MHz is in the gap and PLL can not lock.

Hence suggestion. Use TCXCO for double frequency 19.2*2MHz as the PLL reference clock. Divide by 2 the same TCXCO output to get 19.2MHz CLK for the rest of the system. Or, you may have some other better ideas in mind.

Best regards, Srdjan

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[Med]

Many thanks for the explanation