understanding the MEM group and its limitations

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Nichols A. Romero

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Jul 11, 2023, 11:44:34 AM7/11/23
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Hello,

The MEM group for Cascade Lake is defined here:

I don't fully understand the CAS_COUNT_[RD,WR] -- I am assuming its data pulled from main memory into the LLC?

Are there circumstances where the memory data volumes measured by these Uncore counters may be overcounting the *real* data volume?

Yes, this post is about FLOPS and not memory data transfers, but it made me wonder if there is an analogous issue with measuring data volumes.

Some context: I am hoping that the memory data volume collected on a Cascade Lake will help me predict performance on a RISC-V system. But I am encountering some issues at the moment... which I can certainly provide more details later, but I thought I would start with a shorter initial e-mail.




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Nichols A. Romero, Ph.D.

Thomas Gruber

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Jul 11, 2023, 11:55:11 AM7/11/23
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Hello,

the Intel Forum post is about Intel architectures from 2013 (SandyBridge - Haswell). There the FP rate events were not counting retirement but issuing/executing which leads to overcounting if the instruction needs to be rescheduled in order to wait for data (reservation station).

LIKWID measures the memory traffic directly on the memory controllers for Intel Cascadelake SP. In my tests they are quite accurate [1]. Don't get confused by the undercounting for small sizes, the heurisitics when to keep non-modified data in the  L3 victim cache is quite clever. I can't remember any case where the events overcounted.

CAS_COUNT_RD: "Counts all CAS (Column Access Select) read commands issued to DRAM on a per channel basis.  CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every read.  This event includes underfill reads due to partial write requests.  This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write)  is enabled or not."
CAS_COUNT_WR: "Counts all CAS (Column Address Select) commands issued to DRAM per memory channel.  CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not."

Best,
Thomas

Nichols A. Romero

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Jul 12, 2023, 12:16:24 PM7/12/23
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Thank you Thomas for the links and the explanation.

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