hardware events for RISC-V

[Nichols A. Romero]

Hi,

I have an interest in hardware events for RISC-V.

At the moment, the events available on RISC-V are very limited. I am hoping this will improve with time, especially since this announcement from last month.

https://www.syclops.org/updates/2023/05/10/launch-of-the-new-horizon-europe-project-syclops

I have two broad questions:

1. How does one go about steering the hardware events so that they are useful to application developers? (Attend a RISC-V Summit and complain to hardware engineers?)

2. Is there any developer documentation somewhere that describes what is needed to support a new architecture? (Seems like it's including the correct header file(s) and reading the register and mapping it to a meaningful event).

Thanks,

--

Nichols A. Romero, Ph.D.

[Thomas Gruber]

Hi Nichols,

As far as I know, the latest RISC-V Privileged Specification contains a design for hardware counters but it is unclear to me whether this is a final version. It seems too simple for me to cover all use-cases like more external units (memory controller, ...). Moreover, HPC relevant stuff like vectorization is not yet finalized (to my knowledge). I hope that each component (e.g. vectorization) will add own events.

1. Work on these specifications occurs on Github . You could probably work on broader support there. My assumption is that it will be somewhat similar to the ARM world with a basic set (in the specs) and vendor-specific extensions.

2. For LIKWID, there exist two wiki pages (Feedback to the docs would be great):

 - The ARM specific version which uses only the perf_event backend: https://github.com/RRZE-HPC/likwid/wiki/AddARMSupport

 - The x86/x86_64 specific version which provides all three backends (direct access, accessdaemon and perf_event): https://github.com/RRZE-HPC/likwid/wiki/AddX86Support

For RISC-V, I don't know enough about the architecture/ISA/... to tell whether the direct access and accessdaemon backends can be made. We need access to the performance counters from user-space, so either there are instructions to access them directly or we need a kernel-interface for register access. That's also the reason why LIKWID has no direct access for ARM, the user-space access can be enabled, but only at kernel level (kernel module required) and there is no interface for register access.

Best,

Thomas