What Is Fpga Xilinx
Karmen Mcarthun
Field-programmable gate arrays (FPGAs) are used in a wide variety of applications and end markets, including digital signal processing, medical imaging, and high-performance computing. This application note outlines the issues related to powering FPGAs. It also discusses Analog Devices' solutions for powering Xilinx FPGAs.
Field-programmable gate arrays (FPGAs) are used in a wide variety of applications and end markets, and they have been gaining market share over ASICs due to their excellent design flexibility and low engineering costs. Power-supply design and management for FPGAs is an important part of the overall application. This article discusses ways to overcome some of the power-supply design challenges and explains the trade-offs between cost, size, and efficiency. Analog Devices' solutions for Xilinx FPGAs are also presented.
FPGAs are programmable devices consisting of an array of configurable logic blocks (CLBs) connected through programmable interconnects. These CLBs typically comprise various digital logic components, such as lookup tables, flip-flops, multiplexers, etc. Other components of an FPGA include input/output pin driver circuits (I/Os), memory, and digital-clock management (DCM) circuits. Modern FPGAs integrate features that include FIFO and error correction code (ECC) logic, DSP blocks, PCI Express controllers, Ethernet MAC blocks, and high-speed gigabit transceivers Figure 1.
Most high-performance/high-power FPGA applications in communications applications are built on plug-in cards that are powered by a 48V backplane. A two-stage intermediate bus architecture (IBA) is typically used in these applications for the individual cards (Figure 2). The first stage is a step-down converter that converts the 48V to an intermediate voltage, such as 12V or 5V. The plug-in-cards are often isolated from each other for safety reasons, and to eliminate the possibility of current loops and interference between the cards. The second stage of the IBA is to convert the intermediate voltage to multiple lower DC voltages, using nonisolated regulators known as "point-of-load" (POL) regulators. FPGAs used in computing, industrial, and automotive applications typically derive their power from a 12V to 24V nonisolated supply.
POLs are high-performance regulators whose VOUT rails are placed close to their respective loads. This helps solve the difficulties of high-transient-current demands and the low-noise requirements of high-performance semiconductor devices like FPGAs. The application-level parameters to be considered when designing a POL are:
The priority assigned to each of the above parameters often depends on the end market. Thus, each solution should be considered independently. For example, industrial and medical markets tend to favor size over cost, while wireless applications generally favor cost over size. Consumer applications are very conscious of all three parameters. Efficiency is particularly important to applications that run on batteries. The required efficiency usually determines what kind of DC-DC regulator is used, either low-dropout linear regulators or switch-mode power supplies.
LDOs are relatively simple to implement, inexpensive, and produce very little noise. The major drawback with LDOs is their poor efficiency, which depends on the ratio of VOUT to VIN. For example, an LDO with VIN = 3.3V and VOUT = 1.2V has only 36% efficiency. The power difference is dissipated as heat.
LDOs are typically considered for applications with relatively low power requirements. SMPSs are used in higher-power applications due to their better efficiency, an important parameter for thermal management and reliability. Higher efficiency results in lower device temperatures, which improves reliability and reduces the overall solution size through smaller heatsink requirements.
A good example of a high-performance FPGA is the Xilinx Virtex-7 FPGA. Table 1 shows the main voltage-supply requirements for this part. There are also other less-demanding voltage rails such as VCCBRAM, VBATT and VREF that require lower current levels. In many applications, a single power supply can be used, along with passive filters to supply two or more of the power rails that use a common voltage. In these cases, the power supply may be required to supply 20A or more.
FPGA manufacturers such as Xilinx have power estimation spreadsheets for estimating the power requirements of an FPGA device, based on the required functionality of the FPGA (www.xilinx.com/power). Designers should use these spreadsheets at the early design stage of a project to assist in selecting appropriate power-supply and thermal-management components. Through the use of the power estimators, designers can determine the voltage supply rails needed and their currents to select the most suitable regulators. Table 2 shows a sample power budget for a Virtex-7 FPGA. These power calculations are used to determine the system efficiency and the required thermal-management solution.
In addition to using the power estimation tools to estimate the FPGA supply rail voltages and currents, there are several other aspects to choosing a power regulator. The following are some topics to consider.
Three or more voltage rails are typically required to power an FPGA. It is good design practice to implement sequencing for power-up and power-down between these rails. One advantage of this is that sequencing limits the inrush current during power-up. Also, even if the FPGA itself does not require sequencing, other devices in the design, such as microcontrollers and flash PROM, may have sequencing requirements. If the sequencing is ignored, the devices that require sequencing can be damaged or latchup which, in turn, can cause a malfunction.
With coincident tracking, typically the preferred sequencing method for FPGAs, the rails ramp up simultaneously and at the same rate to their final set-points. This prevents unreliable startup due to latchup and bus contention. It also avoids turning on any parasitic conduction paths that could damage an FPGA. The higher startup inrush currents required by this type of sequencing can require a larger capacitor bank to ensure that the rails rise monotonically. The inrush current issue is alleviated by the adjustable soft-start feature found on most of Analog's POLs. For example, the MAX8686 facilitates coincident tracking and provides a programmable soft-start time based on the value of a single capacitor.
The main advantage with sequential sequencing is that it is generally easy to implement; startup inrush-current requirements are less than both coincident and ratiometric sequencing. However, the maximum voltage differential occurs between the voltage rails with this method, which could cause unreliable device behavior.
Ratiometric tracking ramps up all the voltage rails to reach their set-points at the same time. This reduces the voltage differential between the rails, compared to sequential sequencing. The level of startup inrush current is between the level for coincident tracking and sequential sequencing.
It is important for the ramping voltage rails to rise monotonically at startup to achieve successful power-up. That means that they should rise continuously to their set-point and not droop. Drooping could result if the POL does not have enough output capacitance (Figure 4). The critical area for most FPGA core voltages is between 0.5V and 0.9V when the internal logic blocks are initialized to valid operating states.
Most Xilinx FPGAs specify minimum and maximum startup ramp rates of 0.2ms and 50ms, respectively. However, there are exceptions. For example, the "-1L" version of the Spartan-6 ramp rate is 0.2ms to 40ms, while the Spartan-3A has a ramp rate of 0.2ms to 100ms.
Power-supply regulators implement soft-start by gradually increasing the current limit at startup. This slows the rate of rise of the voltage rail and reduces the peak inrush current to the FPGA. Analog's POLs allow soft-start times to be programmed based on the value of a soft-start capacitor connected to one of the POL pins.
There are situations where an FPGA voltage rail remains biased at some voltage level when a power supply is shut down. This prebias is usually the result of various parasitic conduction paths through the FPGA. If the power supply restarts and pulls the prebiased output voltage low, it can result in unsuccessful startup of the FPGA. The output voltage of the power supply should instead be ramped up to its set-point, along with the other FPGA voltage rails in their desired sequence.
While working on the PCB design, engineers must consider component placement, signal routing, and board layers. A multilayer board is highly recommended for FPGA designs, with a ground layer between each signal routing layer. The shielding that the ground layers provide allows for signal routing on every layer, without having to consider the adjacent routing layers. This facilitates a simpler and more practical layout.
Decoupling capacitors should be connected as close to the FPGA power pins as possible. The decoupling capacitors reduce any conducted noise from the power supply and radiated noise from surrounding circuits.
FPGAs can implement many functions at different frequencies due to their multiple clock domains. This can result in larger step changes in current requirements. The term "transient response" refers to a power supply's ability to respond to these abrupt changes in load current. A regulator should respond without significantly overshooting or undershooting its set-point and without sustained ringing in the output voltage. The transient response of a regulator depends on the following:
93ddb68554