Recruitment of Engineer Trainees

[Surya Narayana Varma Uppalapati]

HI all,

VEDA IIT is conducting examination for recruitment of Engineer Trainees into its consortium companies in VLSI  Logic Design , VLSI Physical Design, Embedded System Design, VLSI Layout Design and VLSI Analog Design on  Sunday 26th October, 2014.

Last date for on-line applications:  22nd October, 2014.

Interested candidates need to pay Rs. 300/- by DD towards their application and  can apply at http://www.vedaiit.com.

For further details including examination date please visit  at http://www.vedaiit.com/careers.htm   and visit the facebook at https://www.facebook.com/VEDAIIT

Thanks & Regards,

Surya Narayana Varma Uppalapati
Reach me @ +91 96 66 03 00 83