Fwd: only for ECE &EEE for JKC & Non JKC

[burra naresh]

---------- Forwarded message ----------
From: mahi veshala <placeme...@gmail.com>
Date: Mon, Feb 9, 2015 at 12:49 PM
Subject: only for ECE &EEE for JKC & Non JKC
To: vishwateja bodla <Vish...@gmail.com>, anusha dasi <anushadas...@gmail.com>, Shashidhar Dhavala <dhavalas...@gmail.com>, Fazal Ahmed <fazal....@gmail.com>, Snehitha Chinnapally <snehithac...@gmail.com>, Masadi Ramya <masadi....@gmail.com>, Pradeep I <ipradeepk...@gmail.com>, Gurijala Sirimuvva <sirimu...@gmail.com>, burra naresh <nareshb...@gmail.com>, yamini reddy <bodhe.ya...@gmail.com>, bhukya pavan kumar Kumar <pavantej...@gmail.com>

visit jKC site for details and conformation

VEDAIIT Engineer Trainee Recruitment Process

 

JKC is organizing a recruitment event with vedaIIT at Hyderabad for 2015 pass outs. Eligibility criteria, Positions details are as given below. The eligible and interested candidates can confirm their participation through the following link

Position:-

1.       Engineer trainee in VLSI Analog design

Job Profile:-

• Analog Mixed Signal Design in latest FinFET technologies for blocks like PLL, DLL, CDR, Equalizers, drivers, LDO, etc..
• Design of high speed SerDes like USB3, SATA, PCI Express, 10G, SAS, Infiniband, Fibre Channel, etc. handling data rates from 1.2 to 28 Gbps
• ADC, Memory, Standard Cell designs
• AMS Block level and system simulation

Eligibility:-

2015 B.E/B.Tech graduates ( from  ECE, EEE, EIE, EICE, ECM, ETM streams )   with 65% throughout academics

NOTE:- 

Last date for confirmation is Feb 12, 2015