Hi Roy,
Yes you are correct in your observations with this. Each of /dev/uio0-/dev/uio15 is mapped to the 16 PL->PS interrupts respectively and mapped to the entire AXI GP0/GP1 master address space.
The intention is to give a way for hardware oriented users to interface FPGA IP with the Linux userspace without having to reconfigure the Linux kernel/device tree/etc.
Also, the last 1/4 of DDR memory (256MB on the snickerdoodle black) is held aside from linux control (but cached) for physical mapping via /dev/mem (direct access via the AXI ACP slave port from PL).
We have tested the /dev/uioX interrupt performance and AXI GP0/GP1 interaction extensively and I will share some code from that attached here (to be published to Git later).
I've recently pushed a Vivado HLS project implementing a bespoke data mover/DMA intended in operate in a straightforward manner using the above mechanisms for high performance data transfers over the AXI ACP to that 256MB reserved memory area.
The linux user space side source for this I am in the process of testing this week and will push when it is ready. It will show utilization of the default Linux image reserved memory, AXI ACP, AXI GP0, /dev/mem and /dev/uioX devices.
-Jamil