JTAG debugging, Digilent HS3 interface, PS_SRST_B

[Rob Barris]

I'm looking at this USB->JTAG interface to use with the breakyBreaky baseboard.

https://www.digilentinc.com/Products/Detail.cfm?NavPath=2,395,1298&Prod=JTAG-HS3

Of note in the manual for it, is this segment:

https://www.digilentinc.com/Data/Products/JTAG-HS3/JTAG-HS3_RM.pdf

"The Xilinx Tools occasionally require the processor core of the Zynq-7000 to be reset during debug operations. The

Zynq platform processor has a pin dedicated for this purpose (PS_SRST_B). Driving the PS_SRST_B pin low causes

the processor to reset while maintaining any existing break points and watch points. The JTAG-HS3 is capable of

driving this pin low under the instruction of Xilinx’s SDK during debugging operations. In order for this to work, pin

14 of Xilinx JTAG header on the target board must be connected to the PS_SRST_B pin of the Zynq (see Figs. 3 & 4)."

The schematic for the breakyBreaky shows pin14 connected to something called "ZYNQ_JRST".  Is that the same thing as PS_SRST_B?  If not, can you go into some detail about the debugging experience in the Xilinx toolset (Vivado/XSDK) using this type of interface, or one like it ?

curious,Rob

[weath...@krtkl.com]

Hi Rob, ZYNQ_JRST drives PS_SRST_B_501 on the Zynq.

See table 6.3 in the user manual https://github.com/krtkl/snickerdoodle-manual/blob/master/snickerdoodle-user-manual.pdf

-Jamil