This talk walks through the complete bring-up flow of a CXL Type-3 memory device on a Acpi/non-ACPI platform (Risc Processor), covering how firmware exposes CXL capabilities via Acpi or Device Tree, how Linux initialises CXL HDM decoders, and how CDAT/HMAT attributes shape performance-aware memory topology. We will deep-dive into CXL.mem region creation, multi-region handling, and enabling DAX/pmem drivers via ACPI/Non-Acpi. The session combines firmware design, kernel internals, and practical debugging to help developers integrate CXL memory on heterogeneous architectures.
Topic Outline :
Decoder Init • CDAT/HMAT Integration • Memory Regions & DAX Enablement
Preferred Format: 25+5 mins (but open for Lightning talk as well for selection)