CXL Bringup on X86 and Risc Processor

[Er Krishna]

Hi All, 
Please find my talk proposal for the kernel meetup Blr, December 2025.
Abstract / Talk Description :

This talk walks through the complete bring-up flow of a CXL Type-3 memory device on a Acpi/non-ACPI platform (Risc Processor), covering how firmware exposes CXL capabilities via Acpi or Device Tree, how Linux initialises CXL HDM decoders, and how CDAT/HMAT attributes shape performance-aware memory topology. We will deep-dive into CXL.mem region creation, multi-region handling, and enabling DAX/pmem drivers via ACPI/Non-Acpi. The session combines firmware design, kernel internals, and practical debugging to help developers integrate CXL memory on heterogeneous architectures.

Topic Outline :
Decoder Init • CDAT/HMAT Integration • Memory Regions & DAX Enablement

Preferred Format: 25+5 mins (but open for Lightning talk as well for selection)

Speaker:

Krishna is currently a Principal Engineer at Upscale AI (https://upscaleai.com/), where he leads the ASIC-side software design for scale-up and scale-out networking. Previously, he was a kernel developer at IBM-LTC, contributed to the CXL bring-up initiative. Before that, he worked in the Oracle Linux Engineering group for the Oracle Linux Kernel team. At Cisco Systems, he developed an ARM-based, proprietary Cisco bootloader from scratch for both the Linux Kernel and FreeRTOS. At Nutanix, he served as a subject matter expert for the kernel block and network layers. He also contributed to Pavilion Data Systems, working on the world’s fastest NVMe-over-Fabric product line. Krishna has approximately 19 years of IT experience.

Best regards,

Krishna 

[Sumit Gupta]

+1

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Thanks & Regards,
Sumit Gupta
Mob: +91-9717222038