Digital Electronics By Br Gupta Pdf 257
Totaly Benoit
The Industry 4.0 concept promotes a digital manufacturing (DM) paradigm that can enhance quality and productivity, which reduces inventory and the lead time for delivering custom, batch-of-one products based on achieving convergence of additive, subtractive, and hybrid manufacturing machines, automation and robotic systems, sensors, com- puting, and communication networks, artificial intelligence, and big data. A DM system consists of embedded electronics, sensors, actuators, control software, and interconnectivity to enable the machines and the components within them to exchange data with other machines, components therein, the plant operators, the inventory managers, and customers.
Concurrently, there is a shift in demand from high-volume manufacturing to batches-of-one, custom manufacturing of products. While the large manufacturing enterprises can reallocate resources and transform themselves to seize these opportunities, the medium-scale enterprises (MSEs) and small-scale enterprises with limited resources need to become federated and proactively deal with digitalization. Many MSEs essentially consist of general-purpose machines that give them the flexibility to execute a variety of process plans and workflows to create one-off products with complex shapes, textures, properties, and functionalities. One way the MSEs can stay relevant in the next-generation digital manufacturing (DM) environment is to become fully interconnected with other MSEs by using the digital thread and becoming part of a larger, cyber-manufacturing business network. This allows the MSEs to make their resources visible to the market and continue to serve as suppliers to OEMs and other parts of the manufacturing supply networks.
Disruption and transformation get a lot of hype, and for good reason. Digital technologies have disrupted entire industries and incumbents have often struggled in this new world. Typical approaches used by legacy players such as using technology to improve efficiency, encouraging business units to do digital experiments, or launching independent units to spur innovation have met with limited success. These players have to strengthen their core and build for the future at the same time. It is like changing the engine of a plane while it is flying.
The fact that digital technology disrupts existing businesses is no longer news. We have seen and heard many case studies of incumbents struggling in the digital age as new and nimble players emerge with innovative business models. How should large established companies respond to these changes and how should they transform their businesses in this dynamic environment? My research addresses this fundamental question to help large established companies transform their businesses for the digital era.
He has served in various capacities in IEEE-CS, the main ones being TMRC member since 2013, TAC Vice-Chair in 2015-16, T&C Executive Committee member in 2015, and two-term Chair of TCPP from 2011-2015. He brings experience in strategy formulation, in policy discussions for technical committees, and extensive experience in conference organization from his various roles which include steering committee member, general co-chair, finance co-chair, TPC co-chair, and advisory boards in major international conferences such as IPDPS, HiPC, PaaP, PDCAT, IACC, etc. He is involved in the global efforts to revise undergraduate and graduate computer science and computer engineering curriculums to keep pace with technological advances. Browse www.cs.wmich.edu/gupta for more details.
Flexible electronics has significantly advanced over the last few years, as devices and circuits from nanoscale structures to printed thin films have started to appear. Simultaneously, the demand for high-performance electronics has also increased because flexible and compact integrated circuits are needed to obtain fully flexible electronic systems. It is challenging to obtain flexible and compact integrated circuits as the silicon based CMOS electronics, which is currently the industry standard for high-performance, is planar and the brittle nature of silicon makes bendability difficult. For this reason, the ultra-thin chips from silicon is gaining interest. This review provides an in-depth analysis of various approaches for obtaining ultra-thin chips from rigid silicon wafer. The comprehensive study presented here includes analysis of ultra-thin chips properties such as the electrical, thermal, optical and mechanical properties, stress modelling, and packaging techniques. The underpinning advances in areas such as sensing, computing, data storage, and energy have been discussed along with several emerging applications (e.g., wearable systems, m-Health, smart cities and Internet of Things etc.) they will enable. This paper is targeted to the readers working in the field of integrated circuits on thin and bendable silicon; but it can be of broad interest to everyone working in the field of flexible electronics.
Thus, the fTnorm is directly proportional to the mobility and inversely to square of channel length when the devices have similar parameters other than the mobility and the channel length. Putting the µ and L values from some of the recent works in Eq. (2), the comparison in Table 1 shows that the monocrystalline silicon based devices with channel length in nanoscale regime will have high fTnorm and as a result they will outperform most of the other semiconductor materials. Interestingly, the devices from high mobility materials such as graphene, carbon nanotubes,7 and some the 2D materials are slower than silicon. Clearly, the channel length or device technology plays a significant role in the final performance of devices. Therefore, instead of fixating on high-mobility materials, a holistic view with inputs from both material science and engineering is important. With technological advances, the devices from high mobility materials such as graphene, and carbon nanotube etc. could eventually catch up and possibly may have better performance than monocrystalline silicon, but this is unlikely in next few year as related technology is still in the nascent stage of development and is far from commercialization.8,9 Considering these facts, the monocrystalline silicon appears to be the best bet to meet immediate high-performance needs of flexible electronic systems. This also explains why silicon and other materials such as compound semiconductors have attracted significant interest in recent years. Nanostructures such as nanomembranes, nanoribbons, nanowires etc. from these materials have been explored for flexible electronics.10,11,12 Considering the challenges such as printing of aligned nanostructures, poor density of printed nanostructures, and difficulties in terms of obtaining very large-scale functional integrated circuits (ICs), the silicon-based microelectronics is an obvious choice.
The technology readiness to obtain devices down to nanoscale dimensions and the possibility to exponentially scale the device densities up to billions of devices per mm2, makes silicon based microelectronics a good candidate for addressing immediate high-performance needs in flexible electronics. For this the first issue that need to be overcome is the lack of flexibility (and hence conformability) of silicon wafers. This has been achieved by thinning the wafers down to
Temperature is known to have significant impact on the performance and reliable operation of electronics and therefore discussion on thermal properties of UTCs gain importance. The heat dissipation, particularly in the UTCs realized from SOI wafers having top Si thickness in the nanoscale, significantly differ from conventional bulk Si based chips. For example, the thermal conductivity of
The etch stop layer method, typically used in a MEMS, takes advantage of the fact that doping could be used to stop etching. It involves developing a highly doped (p++ type) film at certain depth (roughly equal to desired thickness of UTCs) on the front side of wafer, followed by lightly doped epitaxial layer which act as active layer for device fabrication. Post device fabrication the wafer is chemically etched from back side until the chemical hits the p++ layer, which stops the etch process. The final thickness of UTC is the equivalent to the thicknesses of the epitaxial and p++ layer.65 With a good control over the final thickness and uniformity of UTCs, this method (Fig. 6c) offers an alternative solution to the SOI wafer based approach. During growth process, the diffusion of impurities between Si wafer and p++ film may prevent the fabrication of an ideal step junction, which may lead to lower switching current ratio and hence the poor performance of electronics on UTCs. One way to control the impurity diffusion is to adopt low temperature epitaxial growth with a trade-off between high quality epitaxial film and higher impurity diffusion.
A wide range of applications require UTCs as through underpinning high-performance electronics they enable advances in several areas, as illustrated in Fig. 1. The UTCs form the key components of various smart systems as sensing units, data processing or storage unit, driving or output unit and power or energy management units etc. Depending on the application requirements, the specification of electronics/sensing components on UTCs may vary. Some of the applications where UTCs are used as sensing units, data processing or storage unit, driving or output unit, and power or energy management units are described below.
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