Compilation to hardware (ASICs)

[David Ainish]

3D printing is growing at a rapid pace and in a few years it will be possible to 3D print our own integrated circuits and microprocessors.

Would it be possible for Julia in the future to do Hardware compilation and 3D print ASICs from our Julia code?

[John Myles White]

If someone wrote code to do that, I don't see why it wouldn't be possible.

 -- John

[Matt Bauman]

It seems like there are several groups working on an LLVM IR to FPGA/ASIC compiler.  That'd be the way to do it.  Make julia emit the IR, and then compile that to your ASIC.

http://stackoverflow.com/questions/3664692/creating-a-vhdl-backend-for-llvm
Google search: llvm ir hardware (asic|fpga)

[Steve Kelly]

I am currently working on a path planner for 3D printing written in
Julia. I also am going to be working on solid modeling with Julia
scripts and functional representation for my undergraduate thesis.

So maybe we can meet half way :)

[David Ainish]

Nice projects on those links. LegUp looks good.

I'm new to Julia so this may be a silly question... For that workflow (LLVM IR -> FPGA/ASIC), does Julia already emit IR code? if not, once Julia is able to emit IR code, would it be possible to use a tool like LegUp to create an ASIC?

The workflow IR -> ASIC would be a two-steps workflow. While it's a good option, there could be an integrated workflow that would give very interesting possibilities tied to Julia's dynamic nature.
Dreaming out loud, at the time we can 3D print microprocessors, if part of our code requires intensive processing and that task could be parallelized, we could 3D print for instance 100 processors of that specific task and Julia spread the work over those 100 ASICs.
Or translate the code that requires more computational power dynamically to any available FPGA.

[Jameson Nash]

JIT hardware? I guess that is a reasonably logical next step after doing JIT software compilers

JIT FGPA sounds almost reasonable. Last time I checked, the Xilinx FGPA coprocessor was very expensive (like new luxury car expensive), but is anyone doing stuff like that already?

[David Ainish]

It seems the idea of JIT Hardware Compilation has been around for a while:

http://link.springer.com/chapter/10.1007%2F978-3-540-78791-4_12#page-1

http://www.informationweek.com/jit-compilation-to-hardware/d/d-id/1073781?

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6567576&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D6567576

[David Ainish]

@Jameson
Apparently IBM's Liquid Metal project (LIME programming language) is already taking this approach.

It seems LIME can compile into heterogeneous hardware with both CPUs, GPUs and FPGAs and customize the hardware according to the application that is running, executing tasks in the most efficient hardware for each kind of task. Things would be transparent for the programmer.

From their website: "Our long-term goal is to 'JIT the hardware' to dynamically select methods for compilation and synthesis to hardware, potentially taking advantage of dynamic information in the same way that multi-level JIT compilers do today for software."

IBM's Liquid Metal project.


For those not familiar with FPGAs/ASICs here is a very good article that discusses the benefits and related technologies, like High-Level synthesis, which turns high-level language code into integrated circuits. It discusses Liquid Metal and shares thoughts about the future of programming languages and the hardware architecture they'll run on:
http://queue.acm.org/detail.cfm?id=2443836

And an open source project for hardware construction from code (Chisel):
https://chisel.eecs.berkeley.edu/


Julia seems perfect for this level of dynamism. I'd rather see Julia's simplicity, clean and flexible style taking advantage of pioneering in this field to help it become a standard rather than a not so optimal adaptation of any legacy language just for the sake of compatibility.

On Friday, May 30, 2014 8:58:29 PM UTC-3, Jameson wrote:

 

[Tony Kelman]

I actually just started collaborating with these guys http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6546013 who recently moved from MIT to Berkeley. They're using Chisel, Bluespec, and a custom compiler that takes a graph representation of an algorithm and determines a hardware layout and schedule for deployment on an FPGA or ASIC. I'm trying to convince them that Julia would be the best choice as a high-level algorithm description language to generate inputs to their tools, but haven't won them over yet. It's still early going in terms of making it usable with a high level BLAS-like interface.

[David Ainish]

Sounds good. Whenever there is any news that you'd like to share, it'll be welcome.