Altera Vhdl
Ferdinando Addison
I am trying to use 'Floating point and Fixed point package' as a part of my filter design in VHDL. I am using Altera Quartus II as the development environment. I downloaded the file package from the website: , now available at ://www.vhdl.org/fphdl/
Using Altera Quartus II GUI you can add the 'fixed_float_types_c.vhdl','fixed_pkg_c.vhdl' and 'float_pkg_c.vhdl' files to the project through the"Project Navigator" tab called "Files". See figure below.
If I were starting out today, I would use SystemVerilog. Altera has very strong support for it and is improving it with every release, and as someone mentioned, is developing new IP in this language. It is a super-set of Verilog and adds a lot of the structure that VHDL has, but it is optional to use it. IMHO, this is the way of the future of HDL (although we may never be able to fully kill VHDL unfortunately :-)
About the emergence of a new HDL language, I'm rather pessimistic. Some fields of the industry are very slow to adapt to new standards. As an example some customers still ask for VHDL'93 and System Verilog, despite it's advantages, isn't as widely used as it should be.
i was writing in verilog for couple of years. and came to conclusion that your module may work perfectly in one project, and will not in another. i guess the reason lies in the way verilog itself is engineered. my personal opinion is that no language knows how to treat altera's fpga better than AHDL itself. in verilog you model behavior. and god knows what decisions will synthesis make to satisfy that behavior. since verilog throws you far from gate level , sometimes your behavior is too complex or even errorous to synthesize but you don't sense it anymore.because you lost a gate level vision. you have a demand and want it to be satisfied. that's where things get complicated. verilog tries to swallow everything without questioning. that is why in some projects verilog module works perfectly, and in some other projects it does not. sometimes outside of module, you add a very unimportant multiplexer in addition to the output of your module and it starts to synthesize correctly. remove it - again, module is dead.... sometimes very important registers get synthesized away that leads to catastrophic results.in short nobody knows what will come into synthesis's mind when it tries to put your behavioral model into realization. sometimes it does synthesizes correctly. and sometimes logic drives synthesis so far that it starts to dysfunction. ..change a tiny option in quartus from normal fitting to aggressive one(or vice versa), and your module is again dead... i wonder how could such a colossal barrier was left without notice. people continue working with it as with something unavoidable. it's fine when entire project is yours and you can run after single register but nobody will forgive you at work that you gave them some module that sometimes synthesizes and sometimes not. boss demanded this morning to study AHDL. well... if it came to this.. what choice do i have. what decisions did you made in your life in similar situations people..?
hmm... iiii... don'tknow! i can simulate AHDL in modelsim same way i do with verilog. or mixed verilog - ahdl project, also simulates perfectly. modelsim needs a netlist of logic gates it does not care about language (i think). and company i work in produces competitive modern hardware on worldwide market. in it, FPGA s (cyclone 4. 115 000 cells) nearly 100% is programmed in AHDL. but i agree that it is an old language and kinda has a prehistoric style synthax :) working with it feels like working with a dinosaur :) and yes it may make me non employable. but trust me if you compare verilog's synthesis stability and AHDL 's synthesis stability, AHDL proved through years that it's synthesis is always correct while verilog may synthesize something away only because the module was copied in a more dense project and compiled. i know you don't believe me but. nobody did before they copied my module. we all had eyes on out foreheads. how is this possible but it is. of course it could be my lack of knowledge and bad coding but i usually run after each register and it's timing. and it worked great on lighter projects where only 20% of fpga was used. as fitter sees that resources are on limits, say close to 90%, the synthesis and fitter simply chews away verilog module parts. again, forgive me if my incompetence makes me say incorrect things... but i am sure many people have observed the same things with verilog. tricky... you are a moderator here so.. your suggestion has a value because you work for altera. so is it true? that altera is planning to withdraw AHDL? that would be a big mistake i think.companies like mine are welded to altera and they can't even look away from it. because of AHDL. xilinx users are also welded to it because of xilinx programming language (i forgot it's name). by withdrawing AHDL altera will simply force people to jump on verilog. which will open their hands -to more freely slide between altera and it's competitors (according to whoever places cheaper prices on better products). you own us guys :D and you are planning to let it go? well i don't know :)))
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I am doing some undergraduate research this summer at Beckman Institute
and I am working on some VHDL code to control an analog to digital
converter for various sensors on a robot. I am fairly new to ALTERA's MAX+PLUS II software and have a question
regarding how to convert GDF files to straight VHDL. I would like to
know if it is possible to tern a GDF file into a VHDL file. Any suggestions...?
Best regards,>Asher
Jaya,You are the first person I have heard from who is designing an FPGA
using Orcad and VHDL. I attempted this a year ago using version 7.1. The
software worked so poorly and Orcad support was so unhelpful that I
finally gave up and bought the Xilinx Foundation package to finish the
design. How far have you gotten? Are you using the new release 9 software or the
older version 7? Are you having any problems with the VHDL synthesis and
simulation? I liked the fact that I could do a VHDL simulation of my entire design
including the schematic portions. I didn't like the fact that I couldn't
simulate anything because the simulator would crash every third time I
ran it.
-- Rick Collinsrick.c...@XYarius.comremove the XY to email me.Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA designArius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
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> I liked the fact that I could do a VHDL simulation of my entire
> design including the schematic portions. I didn't like the fact that
> I couldn't simulate anything because the simulator would crash every
> third time I ran it.
I don't have any current plans to eval ver 9. I have the software
sitting on my shelf, but the software was only part of the problem. No
small part of my complaints with Orcad have to do with my $100 phone
bill from calling support and not getting good answers. My experience is
that Orcad doesn't or can't do a good job of supporting FGPA design
because that is not their main business and they just don't know enough
about the issues and techniques involved in FPGA design using an HDL. I am not trying to slam Orcad, nor do I wish to start an online
argument. But this was my experience. At this time I am evaluating the Lucent tools for designing their parts.
If this does not pan out, I may be willing to give Orcad another shot.
Rick,I'm not designing an FPGA using Orcad. Orcad is used just for creating a top
level DSN file equivalent to altera GDF. (If I have the vhdl files, it is
easy to make a dsn in Orcad.). It creates a VHDL netlist so that I dont have
to type the componets and ports.(Actually that is the only step I'm gaining
and that was Asher's question I guess!) I have Orcad (version 9) in my PC for
Schematic Cpature.
Also, I'm not using ORcad for synthesis or simulation.(I don't think it's a
good idea! ) .I have Synplify and Modelsim for that.Regards,
Jaya Rajesh.
> I attempted this a year ago using version 7.1. The
> software worked so poorly and Orcad support was so unhelpful that I
> finally gave up and bought the Xilinx Foundation package to finish the
> design.
>
> I liked the fact that I could do a VHDL simulation of my entire design
> including the schematic portions. I didn't like the fact that I couldn't
> simulate anything because the simulator would crash every third time I
> ran it.
>
The general procedure with something like this is to write your VHDL in
sections which reflect your GDF in its most general form. You would create
components where you have separate GDFs and basically create a VHDL
hierarchy in parallel to your GDF structure.This is the easy bit, just fill in the "component is" and "architecture is"
declarations withthe signals you find in the GDF.Then you have to work out how each GDF works, and try to express this in
VHDL using clauses which don't involve a clock at all (combinatorial
blocks), or blocks which execute on a clock edge.The code I would write would involve condition statements, such as if, or
case, and so forth, determining the state of each signal at a time. That way
you can separate the whole circuit into signals and their sources.This is made a lot easier if you really understand the GDFs, maybe having
worked with them for a bit. Of course, in VHDL, you can comment the thing
far more effectively.If the design has a lot of flip flops with asynchronous inputs used heavily,
you would probably be advised to use one process per flip flop (or set of
flip flops if they all implement a bus), since the sensitivity list should
contain the clocks and asynchronous controls. I think this is certainly the
best way of doing it in Max Plus II.Good luckMarkAsher C. Martin wrote in message
news:3777D761...@acm.uiuc.edu...