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US-CA: San Diego-ASIC Engineer - RTL - Top Pay - Cutting-Edge Technology

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JobCircle.Com

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Jul 5, 2011, 10:02:32 PM7/5/11
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Job Title: ASIC Engineer - RTL - Top Pay - Cutting-Edge Technology
Job Location: CA: San Diego
Pay Rate: competitive
Job Length: full time
Start Date: 2011-07-05

Company Name: Cybercoders
Contact: Shea Stone
Phone: email only
Fax: email only

Description: ASIC Engineer - RTL - Top Pay - Cutting-Edge Technology ASIC Engineer - RTL - Top Pay - Cutting-Edge Technology - Career Growth - Global Leader - Skills Required - RTL, ASIC Design, Digital Design, VHDL, Verilog, Synthesis, Gate-level Simulation, DSP, pipe-lining

ASIC Design - RTL - Digital Design - Simulation - high-speed - Logic - DSP - ECC

We are the global leader in a rapidly growing space, working on the most cutting-edge technology on the market. As the global leader, we are in great position to continue growing and dominating the market. We have a great working environment and tons of room for growth. Managing a vibrant, startup-like environment where innovation and technological advancement happen on a daily basis is a top priority. You will have the chance to shine as a top contributor and rise the ranks in a growing company while working in an exciting, technology space. The product you will work on is a next generation product that will revolutionize the data storage space. We are located in Sunny Southern California in one of the best places to live and work in the world! Relocation assistance is available for top-candidates.

If you are a stellar ASIC Engineer, Logic Designer or Digital IC Engineer with strong RTL design, Verilog/VHDL and high-speed design experience, please read on!

What you need for this position:

Required Skill set:
- RTL/Logic design in Verilog and/or VHDL for high-speed, multi-clock domain digital design(s)
- RTL simulation tools exp. (Generation of stimulus for testing & verification)
- Development of bus-functional / cycle accurate models for performance modeling
- RTL Synthesis (i.e. Synopsys, topographical) to meet power/ performance / area targets
- Signal processing design experience
- Knowledge of multi cycle, false paths, etc..
- Gate-level simulation w/ back-annotation of post placement/synthesis SDF (floorplanning, etc.)
Rigorous understanding of state machine design, pipe-lining, etc..

Pluses:
- CPF /UPF experience. Design flow experience for low-power
- Floor-planning experience/knowledge
- Some experience with linting & CDS check tools
- Knowledge of coding theory (advanced codes, i.e.: LDPC, Reed-Solomon, Turbo Codes, ECC, etc.)
- Some experience with advanced verification tools & methodologies, e.g. OVM, UVM, VMM, etc.

What youll be doing:

- RTL & Logic design, simulation, emulation, etc.
- RTL Synthesis
- Verilog / VHDL high speed design
- Gate Level simulation

Whats in it for you:

- Be part of a growing team and company in a cutting-edge, exciting, space
- Be a part of an industry leader creating exciting new products
- Top pay and benefits package and room and visibility for growth
- Making major contributions and a true impact on our companys bottom line and technology

So, if you are a stellar ASIC Engineer, Logic Designer or Digital IC Engineer with strong RTL design, Verilog/VHDL and high-speed design experience, please apply today! - JK-ASICENG - , , , , , CyberCoders CyberScientific
CyberCoders, Inc is proud to be an Equal Opportunity Employer. Applicants are considered for all positions without regard to race, color, religion, sex, national origin, age, disability, sexual orientation, ancestry, marital or veteran status.

Job ID: JK-ASICENG

Please refer to Job code JK-ASICENG when responding to this ad.


For FASTEST PROCESSING of your resume, please visit http://www.jobcircle.com/classifieds/9146811.html?source=ng to apply online.


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you apply to this job using the URL above.
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Jul 5, 2011, 10:02:30 PM7/5/11
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