Client - Tata Elexsi
Job Title - RTL Validation Engineer
Location – San Jose
Duration - 6-12+Months
RTL Validation Engineer
Description
Job Description: A role in RTL validation at IP and full-chip level. Hands on experience in defining validation strategy, creating test benches, defining test plan, creating directed tests, generating random tests, writing/using BFM to generate and check traffic. Experience in OVM/UVM and have a working knowledge of modifying TestBenches. Good skills in object-oriented programming such as SystemC and SystemVerilog, assertion languages such as OVA, as well as verification coverage tools and matrices are required. Knowledge of scripting languages such as PERL, TCL or Python recommended. Familiarity of lab testing a plus. Familiarity with one or more bus protocols such as PCIe, USB, Ethernet, AMBA, IOSF, DDR, display, JTAG, DFT required.
The candidate must be able to interact effectively with cross functional design engineers/leads as well as communicate effectively with management and peers. In addition, be self-motivated with the initiative to seek constant improvements in the logic validation methodologies. The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.
Qualifications
You should possess a relevant educational qualification, BSEE or higher
6+ years design experience in the RTL validation domain.
5+ years of experience in OVM/UVM
Additional qualifications include:
- extensive knowledge & hands-on experience in RTL design, validation, flows and relevant EDA tools (VCS, etc.)
- hands-on expertise with OOP languages as well as hardware description languages VHDL, SystemVerilog, and Verilog
- experience in setting up flows and methodologies and in executing to ensure full functional coverage and minimal logic escapes
Regards,
Clepus Dcruz
Kelly Maxson, Inc.