Emulation Engineer - Sunnyvale, CA - 18+ Months Contract

0 views
Skip to first unread message

Avisheak Singh

unread,
Sep 24, 2018, 12:59:43 PM9/24/18
to avish...@altencalsoftlabs.com

Hi Folks,

Hope you're doing great there..!

I am wondering if you have consultant available for the below position, if so please respond me with their most updated resume and the best contact number to reach them to discuss about the below role ASAP.

Please respond back to
Avish...@altencalsoftlabs.com


Note: Must Be Local To CA Only..!!!!!!!

Job Title: Emulation Engineer

Location: Sunnyvale, CA

Duration: 18+ Months Contract

 

System Level Emulation Compilation and Support

 

Job Description

Core Responsibilities:

As an emulation support engineer you will be involved in developing, implementing and deploying simulation acceleration and emulation using Synopsys ZeBu-S3, Cadence palladium Z1. Create synthesizable/emulate-able models for some modules of the system. Develop methodology/tool flow for running system tests/SW applications/boot OS on emulator. Use emulator effectively to test various areas of the chip using simulation acceleration, coverage, and power aware emulation. Help reproduce post-silicon failures on emulator and help with reproduction of failures in emulator on simulation. Closely work with RTL/verification/design/SW engineers for debug and root-cause. Develop and debug related RTL models, assertions, collateral.

 

Education

Minimum BS (EE or CS) required with over 7 years relevant experience.

 

Skills/Experience Required

Prior experience with hardware emulation (Synopsys ZeBu-S3, Cadence Palladium XP II/Z1) – must have

Strong scripting skills (Python, Ruby, TCL, Shell etc.) – must have

Prior experience with RTL (synthesizable) coding, Verilog coding preferred – must have

Expertise in waveform debugging using Verdi – must have

Experience in C/C++/System-C programming – must have

Excellent hands-on experience with SOC verification

Excellent communication skills and demonstrate the desire to take on diverse challenges

Experience with Verilog/SV will be a plus

Design verification knowledge on UVM, transactor model, assertion, coverage will be a plus

PCIe knowledge a plus

x86_64 knowledge a plus


Thanks

 

Avisheak Singh

Alten Calsoft Labs

Avish...@altencalsoftlabs.com

Avisheak Singh

unread,
Sep 25, 2018, 3:47:34 PM9/25/18
to avish...@altencalsoftlabs.com

Avisheak Singh

unread,
Oct 1, 2018, 1:39:32 PM10/1/18
to avish...@altencalsoftlabs.com

Avisheak Singh

unread,
Oct 9, 2018, 3:48:18 PM10/9/18
to avis...@billionapps.co
Reply all
Reply to author
Forward
0 new messages