An experienced ASIC/FPGA RTL developer is looking for a new contract
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Eran Cohen
Jul 15, 2014, 6:29:21 PM7/15/14
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Subject: An experienced ASIC/FPGA RTL developer is looking for a new contract
Eran Cohen
Cell: (408) 483-3063 begin_of_the_skype_highlighting![]()
(408) 483-3063 FREE end_of_the_skype_highlighting; era...@comcast.net Linkedin profile: http://www.linkedin.com/pub/eran-cohen-eran99-comcast-net/0/519/652
Profile:
Highly skilled expert with more than 25 years of leadership and hands on experience developing ASICs and FPGAs throughout the entire flow: Architecture and specification, micro-architecture, design (RTL, Verilog and VHDL), debug, verification, DFT, synthesis and timing closure, formal verification, prototyping and emulation, interfacing with physical design (back end) groups, COT and foundry service providers, and silicon bring up and interfacing with hardware, software and application groups.
Led or participated in the design of dozens of ASICs, mainly in the area of wired and wireless Physical Layer communications and DSP, but also in image and video processing, compression and coding, low power consumer application, CPUs and more.
Worked in diverse groups and environments for big and established companies, as well as numerous startup companies. Broad and deep knowledge of most (if not all) industry standard tools and flows.
Driven self starter individual, fast learner, team player, experienced in building groups and companies from the ground up.
EXPERIENCE:
NFTI Corp., Cupertino, CA. (June 2002 – Present) www.nfti-asic-fpga-dsp.com Chief Developer Consulted for the following companies:
• - Texas Instruments(Twice in 2007 and 2008-2013)
• - Intel (Thru Kelly Services, 2005)
• - Broadcom (Twice: 2006 and 2008-2009)
• - Mentor-Graphics (2006)
• - Lecroy (2008-2009)
• - Rosum (2002-2003)
• - FyreStorm (2003-2005)
• - Ambarella (Twice in 2004 and 2005)
• - Altierre (2005-2006)
• - Novafora (2005-2006)
• - EnvisionTech (2006)
• - IPSIL (2006-2007)
• - OcarinaTech (2006)
• - Exalt Communications (2007)
• - IncelVision (2008)
• - W5 Networks (2008)
• - Intevac (2010)
• - Echelon (2011-2013)
• - Samplify Systems (2011-2013)
• - MoSys Inc. (2013-Current)
Developed numerous ASICs and FPGAs in the following areas: ATSC/NTSC/PAL Positioning, Video compression, Video and image processing, Graphics, Consumer applications, low power, RFID, TCP/IP DDR, and Wired and wireless communications (PHY, DSP) such as 3G, Wimax, USB (Wireless USB), back-haul, power line Modems, 10Gbase-T , SPI, I2C, MDIO, JTAG and highly parallel Reed Solomon FEC for 100gbs Ethernet, and many more.
Teranetics Inc, Santa Clara, CA. (July 2002 – April 2004) VP of IC Engineering
• Built and ran the mixed signal, IT, digital and backend teams to develop 10Gbase-T ASICs.
• Architected the digital chip, which is DSP heavy with tens of millions of gates at high speeds, yet low power.
• Participated hands on in the digital chip, board and FPGA design.
• Explored potential IP cores and SOC modules to be used on the digital and analog chips.
• Participated in developing the system concept and architecture, standard committee activities, etc.
Morphics Technology Incorporation, Campbell, CA. (March 2001 – June 2002) Sr. Director of VLSI
• Built and led the VLSI group that peaked at ~30 top notch engineers. The VLSI group deals with architecture, design, verification, synthesis, testing and bring up of large and complex deep sub micron wireless processors.
• Supervised the development of a 14M gate, >200MHz multi channel baseband processing chip for 3G cellular base stations. Two stages of the chip were taped out and resulted with fully functional silicon in less than a year.
• Greatly improved the cooperation and coerced tight interaction between VLSI and the other group: Marketing, SW, HW, Systems, and COT/Physical Design (floor plan, static timing, place and route).
• Defined, improved and evaluated procedures, methodology, design flow and tool set for the VLSI group that included random verification (using Vera), formal verification (Assertion and equivalency checking), code coverage, co-simulation, coding rules and Linting, emulation, etc.
• Contributed to the architecture of these chips, and enhanced BIST, scan, and DFT in general.
PC-Tel Incorporation, Milpitas, CA. (December 1998 – February 2001)
Sr. Director of Broadband HW
• Architected and Implemented (hands on, almost by myself) a combination ADSL/V.92 modem HW (FPGA prototyping, production ASIC and various PCI reference boards). The design included FFT, IFFT, interpolation IIR, Codec interface, etc.
• Wrote and maintained the functional and detailed specification for the ASICs mentioned above.
• Built FPGA prototypes (Xilinx Virtex and Virtex-II) of the above ASIC.
• Built from the ground up, and managed the Broadband HW team in PC-Tel.
• Represented the company in the ACR (Advanced Communications Riser) HW specification development.
• Participated in the product and system definition of various broadband products in the company.
ITeX Incorporation, Santa-Clara, CA. (January 1998 - November 1998) Director of IC Department
• Led the development of a 1M gate ADSL CO/CP chip, which was the top seller, and enabled ITeX to go public.
• Built and managed a team consists of 3 groups: Digital design, Analog design and Physical design (back-end).
• Established development methodology, defined, purchased and assimilated advanced tool set.
• Participated in the ADSL modem product-line definition, and contributed to the system and IC architectures.
Terayon Communication Systems, Santa-Clara, CA. (December 1994 – January 1998) Sr. ASIC Manager/ASIC and systems architect.
• First engineer to join Terayon. Built a 15 engineer ASIC team from the ground up, and developed its design and verification methodologies and processes. Terayon employs ~700 people today.
• Participated in developing the system concept and specification, including technical interaction with customers. Contributed significantly to the system definition: Algorithms, Software, Hardware and RF.
• Architected an ASIC that implements most of the cable modem mentioned above, and led its development from concept to production. The chip had 525,000 gates (mostly logic) in more than 50 different blocks, including FEC (Reed-Solomon, Trellis, Viterbi), sophisticated modulation such as CAP, QAM, S-CDMA (DOCSIS 2.0) and other DSP intensive blocks (FIR, raised cosine shaping filters, matched filter, Decimation, Interpolation, Carrier and clock recovery, AGC, noise prediction adaptive equalizers, precoder, and more).
• Developed road map and detailed architecture and wrote specifications for Terayon’s other ASICs, responsible for methodology and development process, relationship with ASIC vendors, packaging and testability.
• Millions of chips have been sold so far, and still going strongly. This chip virtually took Terayon public.
AT&T Bell Laboratories, Middle-Town, NJ. (November 1992 - November 1994) Lead Senior VLSI Engineer
• Architected, designed and implemented the Signal Processing Engine, which was the heart of one of the most successful xDSL modem chip sets ever built. That department was later spun off as Globe Span.
• Conducted DSP simulations and LAN modeling, and led the system engineering for a fast transceiver for LAN applications (100/10Mbps Ethernet, FDDI, and ATM in different rates).
• Definition and design of a chip-set that implements fast Ethernet transceiver (100/10Mbps). ). The chip included cross-coupled echo canceller, adaptive blind equalizer, etc.
• Participated in IEEE 802.3 standards committee and its High Speed Working Group.
• Filed two patent applications regarding the implementation of the above fast transceiver.
National Semi-Conductor Tel-Aviv (NSTA). (February 1986 - December 1992) Senior Chip Design Engineer.
• Implemented a V.32bis modem transmitter and echo canceller, based on National Semi Conductor DSP.
• Participated in the development of different CISC and DSP processors (up to 4 million transistors).
• Played a key role in the automation and systematization of the design and verification process.
T.M.R. Electronics. (January 1984 - February 1986)
• Developed sophisticated Electronic Cash Registers around Z-80 microprocessor, including several peripherals.
Scitex Corporation. (March 1983 - January 1984)
• Designed and wrote automatic test-programs for final tests and integration of high-end imaging systems.
Tadiran, Communication & Electronics Division. (September 1982 - March 1983)
• Tested electronic devices and components, and qualified them for production and development.
EDUCATION: (All 3 degrees in Technion – Israel Institute of Technology) MS in Industrial Management. (Major: R&D Management), 1988 - 1992.
MS in Electrical Engineering. (Major: VLSI Architectures), 1985 - 1988.
Master thesis: “Communication Processors for Multi-Computer Systems”.
BS in Computer Engineering - Cum Laude. (Major: Communication and DSP), 1981 - 1985.
Other Design tools & Skills:
Verilog RTL, SystemVerilog, PLI, Synopsys, BC, Behavioral Synthesis, VCS, NC-Verilog, Vericov, Covermeter, Prime-time, Synplicity, ISE, Vivado, Quartos, ChipScope, SignalScan, Ambit (BuildGates), Verplex/Tuxedo, Synopsys/Formality, Cadence/SPW, Matlab, Simulink, Verisity/Specman, Vera, SyetemVerilog, Tetramex, Mentor/Fastscan, Syntest, HDL-Score, TransEDA, AtHDL, Novas Debussy & Verdi, Virsim, Orcad, Unix/Solaris, Windows, Perl, Python, SystemC, C/C++, Assembler, Xilinx Virtex, Altera Stratix-III, Cyclone-III, NIOS, Arm, AMBA, AHB, Microblaze, OpenRisc, DW8051, master/target PCI bus, DMA, Codec I/F, DDR1, DDR2, DDR3, FEC (ReedSolomon, Trellis, Viterbi), modulation (CAP, QAM, CAP, OFDM), DSP (FFT, IFFT, FIR, IIR, Bi-Quad, raised cosine shaping filters, matched filters, Decimation, Interpolation, Carrier recovery, Clock recovery, AGC, blind/noise predictive/adaptive equalizers, THP), wireless, G.lite, G.dmt, SAR, SERDES, 802.11, 802.16, WiFi, WiMAX, Bluetooth, CFR, DPD, DTV, Ethernet (100Mbps, 10GBE, 40GBE, 100GBE), DOCSIS
Eran Cohen
Cell: (408) 483-3063 begin_of_the_skype_highlighting
Profile:
Highly skilled expert with more than 25 years of leadership and hands on experience developing ASICs and FPGAs throughout the entire flow: Architecture and specification, micro-architecture, design (RTL, Verilog and VHDL), debug, verification, DFT, synthesis and timing closure, formal verification, prototyping and emulation, interfacing with physical design (back end) groups, COT and foundry service providers, and silicon bring up and interfacing with hardware, software and application groups.
Led or participated in the design of dozens of ASICs, mainly in the area of wired and wireless Physical Layer communications and DSP, but also in image and video processing, compression and coding, low power consumer application, CPUs and more.
Worked in diverse groups and environments for big and established companies, as well as numerous startup companies. Broad and deep knowledge of most (if not all) industry standard tools and flows.
Driven self starter individual, fast learner, team player, experienced in building groups and companies from the ground up.
EXPERIENCE:
NFTI Corp., Cupertino, CA. (June 2002 – Present) www.nfti-asic-fpga-dsp.com Chief Developer Consulted for the following companies:
• - Texas Instruments(Twice in 2007 and 2008-2013)
• - Intel (Thru Kelly Services, 2005)
• - Broadcom (Twice: 2006 and 2008-2009)
• - Mentor-Graphics (2006)
• - Lecroy (2008-2009)
• - Rosum (2002-2003)
• - FyreStorm (2003-2005)
• - Ambarella (Twice in 2004 and 2005)
• - Altierre (2005-2006)
• - Novafora (2005-2006)
• - EnvisionTech (2006)
• - IPSIL (2006-2007)
• - OcarinaTech (2006)
• - Exalt Communications (2007)
• - IncelVision (2008)
• - W5 Networks (2008)
• - Intevac (2010)
• - Echelon (2011-2013)
• - Samplify Systems (2011-2013)
• - MoSys Inc. (2013-Current)
Developed numerous ASICs and FPGAs in the following areas: ATSC/NTSC/PAL Positioning, Video compression, Video and image processing, Graphics, Consumer applications, low power, RFID, TCP/IP DDR, and Wired and wireless communications (PHY, DSP) such as 3G, Wimax, USB (Wireless USB), back-haul, power line Modems, 10Gbase-T , SPI, I2C, MDIO, JTAG and highly parallel Reed Solomon FEC for 100gbs Ethernet, and many more.
Teranetics Inc, Santa Clara, CA. (July 2002 – April 2004) VP of IC Engineering
• Built and ran the mixed signal, IT, digital and backend teams to develop 10Gbase-T ASICs.
• Architected the digital chip, which is DSP heavy with tens of millions of gates at high speeds, yet low power.
• Participated hands on in the digital chip, board and FPGA design.
• Explored potential IP cores and SOC modules to be used on the digital and analog chips.
• Participated in developing the system concept and architecture, standard committee activities, etc.
Morphics Technology Incorporation, Campbell, CA. (March 2001 – June 2002) Sr. Director of VLSI
• Built and led the VLSI group that peaked at ~30 top notch engineers. The VLSI group deals with architecture, design, verification, synthesis, testing and bring up of large and complex deep sub micron wireless processors.
• Supervised the development of a 14M gate, >200MHz multi channel baseband processing chip for 3G cellular base stations. Two stages of the chip were taped out and resulted with fully functional silicon in less than a year.
• Greatly improved the cooperation and coerced tight interaction between VLSI and the other group: Marketing, SW, HW, Systems, and COT/Physical Design (floor plan, static timing, place and route).
• Defined, improved and evaluated procedures, methodology, design flow and tool set for the VLSI group that included random verification (using Vera), formal verification (Assertion and equivalency checking), code coverage, co-simulation, coding rules and Linting, emulation, etc.
• Contributed to the architecture of these chips, and enhanced BIST, scan, and DFT in general.
PC-Tel Incorporation, Milpitas, CA. (December 1998 – February 2001)
Sr. Director of Broadband HW
• Architected and Implemented (hands on, almost by myself) a combination ADSL/V.92 modem HW (FPGA prototyping, production ASIC and various PCI reference boards). The design included FFT, IFFT, interpolation IIR, Codec interface, etc.
• Wrote and maintained the functional and detailed specification for the ASICs mentioned above.
• Built FPGA prototypes (Xilinx Virtex and Virtex-II) of the above ASIC.
• Built from the ground up, and managed the Broadband HW team in PC-Tel.
• Represented the company in the ACR (Advanced Communications Riser) HW specification development.
• Participated in the product and system definition of various broadband products in the company.
ITeX Incorporation, Santa-Clara, CA. (January 1998 - November 1998) Director of IC Department
• Led the development of a 1M gate ADSL CO/CP chip, which was the top seller, and enabled ITeX to go public.
• Built and managed a team consists of 3 groups: Digital design, Analog design and Physical design (back-end).
• Established development methodology, defined, purchased and assimilated advanced tool set.
• Participated in the ADSL modem product-line definition, and contributed to the system and IC architectures.
Terayon Communication Systems, Santa-Clara, CA. (December 1994 – January 1998) Sr. ASIC Manager/ASIC and systems architect.
• First engineer to join Terayon. Built a 15 engineer ASIC team from the ground up, and developed its design and verification methodologies and processes. Terayon employs ~700 people today.
• Participated in developing the system concept and specification, including technical interaction with customers. Contributed significantly to the system definition: Algorithms, Software, Hardware and RF.
• Architected an ASIC that implements most of the cable modem mentioned above, and led its development from concept to production. The chip had 525,000 gates (mostly logic) in more than 50 different blocks, including FEC (Reed-Solomon, Trellis, Viterbi), sophisticated modulation such as CAP, QAM, S-CDMA (DOCSIS 2.0) and other DSP intensive blocks (FIR, raised cosine shaping filters, matched filter, Decimation, Interpolation, Carrier and clock recovery, AGC, noise prediction adaptive equalizers, precoder, and more).
• Developed road map and detailed architecture and wrote specifications for Terayon’s other ASICs, responsible for methodology and development process, relationship with ASIC vendors, packaging and testability.
• Millions of chips have been sold so far, and still going strongly. This chip virtually took Terayon public.
AT&T Bell Laboratories, Middle-Town, NJ. (November 1992 - November 1994) Lead Senior VLSI Engineer
• Architected, designed and implemented the Signal Processing Engine, which was the heart of one of the most successful xDSL modem chip sets ever built. That department was later spun off as Globe Span.
• Conducted DSP simulations and LAN modeling, and led the system engineering for a fast transceiver for LAN applications (100/10Mbps Ethernet, FDDI, and ATM in different rates).
• Definition and design of a chip-set that implements fast Ethernet transceiver (100/10Mbps). ). The chip included cross-coupled echo canceller, adaptive blind equalizer, etc.
• Participated in IEEE 802.3 standards committee and its High Speed Working Group.
• Filed two patent applications regarding the implementation of the above fast transceiver.
National Semi-Conductor Tel-Aviv (NSTA). (February 1986 - December 1992) Senior Chip Design Engineer.
• Implemented a V.32bis modem transmitter and echo canceller, based on National Semi Conductor DSP.
• Participated in the development of different CISC and DSP processors (up to 4 million transistors).
• Played a key role in the automation and systematization of the design and verification process.
T.M.R. Electronics. (January 1984 - February 1986)
• Developed sophisticated Electronic Cash Registers around Z-80 microprocessor, including several peripherals.
Scitex Corporation. (March 1983 - January 1984)
• Designed and wrote automatic test-programs for final tests and integration of high-end imaging systems.
Tadiran, Communication & Electronics Division. (September 1982 - March 1983)
• Tested electronic devices and components, and qualified them for production and development.
EDUCATION: (All 3 degrees in Technion – Israel Institute of Technology) MS in Industrial Management. (Major: R&D Management), 1988 - 1992.
MS in Electrical Engineering. (Major: VLSI Architectures), 1985 - 1988.
Master thesis: “Communication Processors for Multi-Computer Systems”.
BS in Computer Engineering - Cum Laude. (Major: Communication and DSP), 1981 - 1985.
Other Design tools & Skills:
Verilog RTL, SystemVerilog, PLI, Synopsys, BC, Behavioral Synthesis, VCS, NC-Verilog, Vericov, Covermeter, Prime-time, Synplicity, ISE, Vivado, Quartos, ChipScope, SignalScan, Ambit (BuildGates), Verplex/Tuxedo, Synopsys/Formality, Cadence/SPW, Matlab, Simulink, Verisity/Specman, Vera, SyetemVerilog, Tetramex, Mentor/Fastscan, Syntest, HDL-Score, TransEDA, AtHDL, Novas Debussy & Verdi, Virsim, Orcad, Unix/Solaris, Windows, Perl, Python, SystemC, C/C++, Assembler, Xilinx Virtex, Altera Stratix-III, Cyclone-III, NIOS, Arm, AMBA, AHB, Microblaze, OpenRisc, DW8051, master/target PCI bus, DMA, Codec I/F, DDR1, DDR2, DDR3, FEC (ReedSolomon, Trellis, Viterbi), modulation (CAP, QAM, CAP, OFDM), DSP (FFT, IFFT, FIR, IIR, Bi-Quad, raised cosine shaping filters, matched filters, Decimation, Interpolation, Carrier recovery, Clock recovery, AGC, blind/noise predictive/adaptive equalizers, THP), wireless, G.lite, G.dmt, SAR, SERDES, 802.11, 802.16, WiFi, WiMAX, Bluetooth, CFR, DPD, DTV, Ethernet (100Mbps, 10GBE, 40GBE, 100GBE), DOCSIS
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