Xschem Windows

[Jenette Bregantini]

6Circuit simulation and visualization of the output waveforms

For the simulation and visualization of the outputs xschem provides the ability to interface with ngspice and gaw (Gtk Anaog Wave viewer).

In this blog post I would like to show you how to create your own NAND gate using the newly released ICPS PDK. I highly recommend following the tutorial for yourself to get some hands-on experience. For comparison, you can find all the resulting source files in this repository.

Luckily, the PDK is not only open source, but it is also designed for open source tools. We will be using xschem for schematic entry, ngspice for simulation purposes and KLayout for the layout of the design.

KLayout allows the installation of packages via it's "Salt" package manager. For now, the ICPS PDK is not yet available via the "Salt.Mine" package index service. This means we have to install it manually into the correct directory.

The installation procedure should be the same as under Linux. You can also download the packages from GitHub and extract them manually. The path to the salt/ folder under Windows is c:\users\you\KLayout\salt, were you is your username.

The first line tells xschem where it can find the symbol libraries.The second line tells xschem which terminal emulator to use. Xschem will use gnome-terminal instead of the default xterm to start the simulation via ngspice.

Now edit the transistors by selecting them and pressing q. Delete all properties after the name. For the PMOS we want to use l=10.0U w=40.0U and for the NMOS l=10.0U w=10.0U. These are the same values as in the Minimal Fab design contest template. Of course you could set other values for L and W, with a minimum of 6u for L and 10u for W.

Next, press the Insert key again and navigate to the ICPS symbol library. Here we need ipin for the inputs opin for the output and iopin for the power supply. Change the names to VDD, VSS, A, B and Z. Use shift + f to flip symbols.

Open KLayout in editor mode. On Linux this is done by passing the -e flag. For example with klayout -e or in my case via Flatpak flatpak run de.klayout.KLayout -e. Under Windows there should be an extra start menu entry.

Next, place the cell in the empty window by clicking anywhere in it. Initially, you will only see a rectangle with the name of the cell. To see the actual layout, select TOP in the cell browser and select Show As New Top. If that did not help, also select Show All.

Select the ML1 layer on the right side and click on Path at the top. We will use the metal layer to connect the transistors with each other and the pads. Make sure there are no gaps between metal paths that should be connected. You can also overlap paths just to be sure.

But we have one problem! We can't connect the gates of the p-channel mosfets without going around the pads. The solution is to use the TIN layer to go underneath ML1. It is basically a bridge underneath the metal layer.

Basically, the pcont cell consists of a metal layer and an underlying TiN layer with a contact in between. So why don't we just draw them ourselves? Well, connections and vias often have strict requirements. For connections in the CNT layer the size has to be 5x5um. By using this cell, we ensure that there won't be an issue.

The first is the DRC - Design Rule Check. With this check, we make sure our design is actually manufacturable. For example, no metal path is too thin, or the distance between two paths too narrow. Therefore DRC analyzes your layout based on the DRC rules from the PDK and prints the results.

It refers to the VIA1 layer and says that only vias of a fixed size of 5x5um are allowed. But we did not even use VIA1, right? Yes, but the PAD60 contains a VIA1 larger than 5x5um and that's where the error comes from.

In this case the gap between ML1 is too narrow and could lead to problems during manufacturing. The solution would be to remove the gap, either by increasing the width of the smaller path or by moving it.

Next, we use the LVS - Layout Versus Schematic check to make sure the layout is actually equivalent to our circuit. For example, in an extreme case our layout could just be empty. Then DRC would still pass, but it would certainly not represent our intended circuit.

Therefore, during LVS, a netlist is built from just the layout - what devices are present and how are they connected to each other - and this netlist is compared to the spice netlist of our NAND gate. If they match, LVS passes.

Now that you have successfully completed this tutorial, how about tackling a different design? For example an XNOR gate? A D-FF? An amplifier? You can use not only transistors, but also resistors and capacitors from the cell library.

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