Please send in your referral resumes to prashanth.kumar@xilinx.com
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Information Technology |
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· IRC98792 IT Security Administrator Masters / Bachelors with 7 to 10 years of experience with IT and 5 to 7 years of IT Security . Experience with *nix and Windows Knowledge of IDS and SIEM, operations and procedures relating to event management. Experience with services such as load balancing, proxies, firewalls Experience in Patch / Vulnerability Management. Knowledge of routing / switching would be advantageous. .
· IRC98658 Staff Systems Administrator Masters / Bachelors with 9-14 years’ experience supporting business and/or mission critical systems environments. UNIX skills principally in the areas of Red hat Linux and Sun Solaris essential. Linux skills principally in Red Hat Linux. Very good shell/Perl programming skills are essential. Knowledge of Python/PHP programming is desirable. Good knowledge of IBM LSF. Experience in administering network services such as DNS, NIS, NFS, LDAP, sendmail, ftp, rsync and SSH, VMWare Virtualization products like vSphere, Vcentre, ESX server and HP/Dell Blade servers. Good knowledge of TCP/IP networking fundamentals.
· IRC99767 Senior Systems Administrator Masters / Bachelors with 6-8 years infrastructure experience. Solid background, understanding and hands on experience both technically and functionally of NIS, BIND Linux DNS, SAMBA, syslog-ng, Splunk and LDAP (AD and non-Active Directory). Experience in Linux administration, PERL, Shell and other Linux scripting and Directory a plus. Solid Experience in scalability design using best practices
· IRC100011 Senior IDM Administrator Masters / Bachelors with 6-8years of experience in Information Technology industry. 4+years of hands-on Subject Matter Expertise in Oracle Identity Manager, Oracle Access Manager, Oracle Directory Server. Strong experience in support, maintenance and deployment of Oracle Identity Manager, Oracle Access Manager, Oracle Directory Server, Oracle Virtual Directory . Proficiency in J2EE, Web Services and SOA for Oracle Identity Manager. Strong experience in Oracle and Red Hat LDAP Directory Servers
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PSSA & SIV |
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· IRC99185 Compiler Architect Masters / Bachelors with 10+ years of work-related experience in developing, debugging and maintaining(Compilers, Assemblers, Debuggers, Linker) . Experience in developing, debugging and maintaining (GCC, GDB, Binutils, Linker, newlib , glibc) including keep the tools at the Tip, building the tool chain for Linux/Windows. Experience in submitting patches to Free Software Foundation (and patches getting accepted) as a contributor And running the Deja GNU tests or Nullstone or Perennial or PlumHall on the Tool chain and analyzing/fixing the failures. Experience in benchmarking and optimizations
· IRC100351 Verification Engineer Masters / Bachelors 4 + years of design verification experience. 3+ years of OOP coding experience (VERA, System Verilog, SpecmanE or C++) and SV Assertions. Strong Verification Methodologies such as OVM, UVM, or VMM .Familiarity with Verilog and General Logic Design concepts, system-level architecture including buses like AXI/AHB, bridges, memory controllers such as DDR2/DDR3, and peripherals such as USB and Ethernet, UNIX environment and scripting languages ( Perl or Python). Good with debug skills using front end industry standard design tools like VCS, NCSIM, Verdi, ModelSim.
· IRC100352 Senior Verification Engineer Masters / Bachelors 6 + years of design verification experience. 4+ years of OOP coding experience (VERA, System Verilog, SpecmanE or C++) and SV Assertions. Strong Verification Methodologies such as OVM, UVM, or VMM .Familiarity with Verilog and General Logic Design concepts, system-level architecture including buses like AXI/AHB, bridges, memory controllers such as DDR2/DDR3, and peripherals such as USB and Ethernet, UNIX environment and scripting languages ( Perl or Python). Good with debug skills using front end industry standard design tools like VCS, NCSIM, Verdi, ModelSim.
· IRC99201 Senior Verification Engineer Masters / Bachelors 8 + years of design verification experience. 5 + years of OOP coding experience (VERA, System Verilog, SpecmanE or C++) and SV Assertions. Strong Verification Methodologies such as OVM, UVM, or VMM .Familiarity with Verilog and General Logic Design concepts, system-level architecture including buses like AXI/AHB, bridges, memory controllers such as DDR2/DDR3, and peripherals such as USB and Ethernet, UNIX environment and scripting languages ( Perl or Python). Good with debug skills using front end industry standard design tools like VCS, NCSIM, Verdi, ModelSim.
· IRC99122 Lead Physical Design Engineer Masters / Bachelors with 10 years of experience in Physical Design. Strong success taping out multiple ASICs at 32nm or below. Deep understanding of all aspects of ASIC design(RTL--> GDS) and implementation. Good understanding of package. Hands-on experience with ASIC methodologies including advanced DFM, DFT, OCV, signoff methodologies. Strong experience using synthesis, place and route tools from Synopsys or ATOP. Must possess good analytical skills, ability to lead, train and guide 5-6 member teams. Must possess good TCL scripting. Should be adaptable and work closer with different teams across Xilinx.
· IRC100272 Senior Systems Software Design Engineer Masters / Bachelors with 10 -12 years of experience designing and developing embedded software and systems. Good knowledge of operating system software stacks (e.g. networking stack, video & graphics drivers), USB, file system & SCSI, PCI/PCIe-capable drivers, Functional Safety in automotive and Android stack. Experience using Xilinx ISE and EDK tools. Experience working with hardware engineers for HW/SW integration and scripting languages (e.g. Perl, Tcl, shell).
· IRC100274 Senior Systems Software Design Engineer Masters / Bachelors with 10 -12 years of experience designing and developing embedded software and systems. Good knowledge of embedded system concepts, BSPs, boot code, boot loaders, benchmarking, embedded / real-time operating systems such as Linux or VxWorks, including kernel and device drivers. Contribution to open-source Linux. Good knowledge of operating system software stacks (e.g. networking stack, video & graphics drivers), USB, file system & SCSI, PCI/PCIe-capable drivers, Functional Safety in automotive and Android stack. Experience using Xilinx ISE and EDK tools. Experience working with hardware engineers for HW/SW integration and scripting languages (e.g. Perl, Tcl, shell).
· IRC100273 Systems Software Design Engineer Masters / Bachelors with 6-9 years of experience designing and developing embedded software and systems. Good knowledge of embedded system concepts, BSPs, boot code, boot loaders, benchmarking, embedded / real-time operating systems such as Linux or VxWorks, including kernel and device drivers. Contribution to open-source Linux. Good knowledge of operating system software stacks (e.g. networking stack, video & graphics drivers), USB, file system & SCSI, PCI/PCIe-capable drivers, Functional Safety in automotive and Android stack. Experience using Xilinx ISE and EDK tools. Experience working with hardware engineers for HW/SW integration and scripting languages (e.g. Perl, Tcl, shell).
· IRC100276 Systems Software Design Engineer Masters / Bachelors with 6-9 years of experience designing and developing embedded software and systems. Good knowledge of embedded system concepts, BSPs, boot code, boot loaders, benchmarking, embedded / real-time operating systems such as Linux or VxWorks, including kernel and device drivers. Contribution to open-source Linux. Good knowledge of operating system software stacks (e.g. networking stack, video & graphics drivers), USB, file system & SCSI, PCI/PCIe-capable drivers, Functional Safety in automotive and Android stack. Experience using Xilinx ISE and EDK tools. Experience working with hardware engineers for HW/SW integration and scripting languages (e.g. Perl, Tcl, shell).
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ICD |
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· IRC99266 Silicon Development Senior Program Manager Masters / Bachelors with 12+ years of FPGA (or ASIC) design and development experience. Excellent with managing delivery of FPGA (or ASIC) products. Experience with full-custom or semi-custom designs, FPGA (or ASIC) design steps including HDL design and verification, synthesis and place & route, Post-silicon validation and debug experience. Strong with coordinating deliverables across the hardware software boundary and coordinating programs across multiple organizations including experience with global organizations. Expert with project management tools
· IRC96058 Senior Hardware Engineer II Masters / Bachelors with 8+ years of Experience. Participate in the Test Bench development, development of OVCs. Strong experience with block level and full-chip level using Constrained Random Verification methodology [SV+OVM] .Experience in writing/developing test plans and development of OVCs.
· IRC96762 Senior CAD Engineer II Masters / Bachelors with 6 to 8 years of CAD flow and methodology development. Experience in synthesis, place and route flows (Synopsys – Design Compiler, I Compiler), STA tools such as PT, PTSI. Strong Experience with physical verification tools such as Calibre or Hercules. Should be good with languages like PERL, TCL and debug capabilities.
· IRC100353 Senior Design Engineer Masters / Bachelors with 8 years of experience in IC Design. Experience Using CAD tools extensively to simulate circuit performance and validation, Level Shifter Designs from/to Periphery and the High Speed SRAMs, Verifying and characterizing the circuit behavior on silicon. Expert in HSPICE/HSIM/ Power analysis tools, shell/PERL and other scripting tools. Power management design experience.
· IRC98725 Staff Design Engineer Masters / Bachelors with 11 years of experience in IC Design. Experience in Analog circuit design of Band-gap voltage references and Analog circuit design of LDO regulators, Power-on-reset and Oscillators. Expert in Verifying and characterizing the circuit behavior on silicon. Excellent experience with HSPICE/HSIM/ Power analysis tools, shell/PERL and other scripting tools.
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XHD Software Center |
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· IRC100437 Senior Staff Software Engineer Masters / Bachelors with of 10 years or PHD with 5+ years of industry experience. Excellent software development skills in C++. Familiarity with design patterns, boost/STL, Verilog, simulation tools such as VCS or Modelsim. Understanding of simulation models, static timing analysis, familiarity with tools such as primetime. Excellent with scripting languages such as Tcl or Perl.
· IRC100438 Senior Software Engineer Masters / Bachelors with of 6+ years of industry experience. Excellent software development skills in C++.Familiarity with design patterns, boost/STL, Verilog, simulation tools such as VCS or Modelsim. Understanding of simulation models, static timing analysis, familiarity with tools such as primetime. Excellent with scripting languages such as Tcl or Perl.
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ADVS |
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IRC99204 Hardware Validation Manager Masters / Bachelors with 10+ years of experience .Good with FPGA Design Tools and Flows. Experience with debugging of failures on hardware board. Verilog/VHDL and scripting languages (TCL and PERL). Knowledge of simulation, synthesis and Timing Analysis, Embedded Systems.
· IRC100643 Hardware Validation Engineer Masters / Bachelors with least 4+ years of experience .3+ year’s FPGA/ASIC design/verification experience. Strong understanding of Xilinx FPGA architecture and tool flow, debugging of failures on hardware board, design and HDL (Verilog/SV/VHDL), simulation, synthesis and Timing Analysis. Strong knowledge in PERL/TCL/C-Shell and Understanding of a domain specific IPs (embedded, DSP, connectivity, etc.).
· IRC100640 Hardware Validation Engineer Masters / Bachelors with at least 8+ years of experience .6 + year’s FPGA/ASIC design/verification experience. Strong understanding of Xilinx FPGA architecture and tool flow, debugging of failures on hardware board, design and HDL (Verilog/SV/VHDL), simulation, synthesis and Timing Analysis. Strong knowledge in PERL/TCL/C-Shell and Understanding of a domain specific IPs (embedded, DSP, connectivity, etc.).
· IRC100638 System and IP Tools Verification Engineer Masters / Bachelors with at least 8+ years of experience. 6+ years FPGA/ASIC design/verification experience. Strong understanding of logic design and HDL (Verilog/SV/VHDL), Xilinx FPGA architecture, tool flow and design optimization techniques, GUI testing methodology and familiar with GUI test automation. Experience debugging skills using simulators (MTI/VCS/etc.). Strong knowledge in PERL/TCL/C-Shell and domain specific IPs (embedded, DSP, connectivity, etc.).
· IRC100639 System and IP Tools Verification Engineer Masters / Bachelors with at least 4+ years of experience. 3+ years FPGA/ASIC design/verification experience. Strong understanding of logic design and HDL (Verilog/SV/VHDL), Xilinx FPGA architecture, tool flow and design optimization techniques, GUI testing methodology and familiar with GUI test automation. Experience debugging skills using simulators (MTI/VCS/etc.). Strong knowledge in PERL/TCL/C-Shell and domain specific IPs (embedded, DSP, connectivity, etc.).
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SIPD |
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· IRC100591 Software Engineer Masters / Bachelors with 3-5 years C++ Experience. Experience in the EDA Tools development. Experience in the Design flows. |
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Best Regards
HR - Staffing team