[inferno-kirkwood] push by mechiel@ueber.net - fix dcache flushing.... on 2010-03-16 17:57 GMT

[inferno-...@googlecode.com]

Revision: a22feeb0e7
Author: Mechiel Lukkien <mec...@ueber.net>
Date: Tue Mar 16 10:55:21 2010
Log: fix dcache flushing.

do not try to use arm926ej-s' test & clean (& invalidate)
instructions/loop, they don't seem to work on the arm9-cpu in the
sheevaplug. so instead, just clean and/or invalidate all ways in
all sets. also, for large regions, clean and/or invalidate whole
cache by calling *all() variant, making sure we don't spend too
long cleaning addresses.

also print the special cpu feature coprocessor register, supposedly
used for l2 cache (from uboot or linux sources).
http://code.google.com/p/inferno-kirkwood/source/detail?r=a22feeb0e7

Modified:
/fns.h
/l.s
/main.c

=======================================
--- /fns.h Mon Mar 15 06:57:05 2010
+++ /fns.h Tue Mar 16 10:55:21 2010
@@ -88,4 +88,8 @@
void dcinv(void*, ulong);
void dcinvall(void);

+ulong mvfeatget(void);
+void mvfeatset(ulong);
+
int segflush(void*, ulong);
+
=======================================
--- /l.s Mon Mar 15 06:57:05 2010
+++ /l.s Tue Mar 16 10:55:21 2010
@@ -210,7 +210,8 @@

TEXT idle(SB), $-4
MOVW $0, R0
- MCR CpMMU, 0, R0, C(CpCacheCtl), C0, 4
+ MCR CpMMU, 0, R0, C7, C10, 4 /* drain write buffer */
+ MCR CpMMU, 0, R0, C(CpCacheCtl), C0, 4 /* wait for interrupt */
RET

@@ -317,41 +318,60 @@
#define DRAINWB MOVW $0, R2; \
MCR CpMMU, 0, R2, C7, C10, 4

+/* arm926ej-s' special test,clean,invalidate instruction does not seem to
work. walk through each way for each set. */
TEXT dcwball(SB), $-4
dcwball0:
- MCR CpMMU, 0, R15, C7, C10, 3 /* special: modifies condition flags, not
r15 */
- BNE dcwball0
+ MOVW $(127<<5), R1 /* start at set 128 */
+wbset:
+ ORR $(3<<30), R1, R0 /* start at way 4 */
+wbway:
+ MCR CpMMU, 0, R0, C7, C10, 2 /* clean set/way */
+ SUB.S $(1<<30), R0 /* flag C for no borrow: another way */
+ BCS wbway
+ SUB.S $(1<<5), R1 /* flag C for no borrow: another set */
+ BCS wbset
DRAINWB
RET

-TEXT dcwb0(SB), $-4
+TEXT dcwb(SB), $-4
MOVW 4(FP), R1
+ CMP $(CACHESIZE), R1
+ BCS dcwball0
ADD R0, R1
BIC $(CACHELINESIZE-1), R0
-dcwb00:
+dcwb0:
MCR CpMMU, 0, R0, C7, C10, 1
ADD $CACHELINESIZE, R0
CMP R1, R0
- BLO dcwb00
+ BLO dcwb0
DRAINWB
RET

TEXT dcwbinvall(SB), $-4
dcwbinvall0:
- MCR CpMMU, 0, R15, C7, C14, 3 /* special: modifies condition flags, not
r15 */
- BNE dcwbinvall0
+ MOVW $(127<<5), R1 /* start at set 128 */
+wbinvset:
+ ORR $(3<<30), R1, R0 /* start at way 4 */
+wbinvway:
+ MCR CpMMU, 0, R0, C7, C14, 2 /* clean & invalidate set/way */
+ SUB.S $(1<<30), R0 /* flag C for no borrow: another way */
+ BCS wbinvway
+ SUB.S $(1<<5), R1 /* flag C for no borrow: another set */
+ BCS wbinvset
DRAINWB
RET

-TEXT dcwbinv0(SB), $-4
+TEXT dcwbinv(SB), $-4
MOVW 4(FP), R1
+ CMP $(CACHESIZE), R1
+ BCS dcwbinvall0
ADD R0, R1
BIC $(CACHELINESIZE-1), R0
-dcwbinv00:
+dcwbinv0:
MCR CpMMU, 0, R0, C7, C14, 1
ADD $CACHELINESIZE, R0
CMP R1, R0
- BLO dcwbinv00
+ BLO dcwbinv0
DRAINWB
RET

@@ -370,3 +390,11 @@
CMP R1, R0
BLO dcinv0
RET
+
+TEXT mvfeatget(SB), $-4
+ MRC CpMMU, 1, R0, C15, C1, 0
+ RET
+
+TEXT mvfeatset(SB), $-4
+ MCR CpMMU, 1, R0, C15, C1, 0
+ RET
=======================================
--- /main.c Mon Mar 15 06:57:05 2010
+++ /main.c Tue Mar 16 10:55:21 2010
@@ -244,31 +244,7 @@
cpctlput(cpctlget()|MMUena|Icacheena|Dcacheena|Alignfault);
}

-/*
-xxx something is wrong with flushing the dcache.
-perhaps the special test & clean cp mrc instructions _do_ modify r15?
-*/
-void dcwb0(void *, ulong);
-void dcwbinv0(void *, ulong);
-
-void
-dcwb(void *p, ulong n)
-{
- if(0 && n > CACHESIZE/2)
- dcwball();
- else
- dcwb0(p, n);
-}
-
-void
-dcwbinv(void *p, ulong n)
-{
- if(0 && n > CACHESIZE/2)
- dcwbinvall();
- else
- dcwbinv0(p, n);
-}
-
+extern ulong flierp(ulong);
void
main(void)
{
@@ -314,6 +290,7 @@
print("conf %s (%lud) jit %d\n\n", conffile, kerndate, cflag);
print("kirkwood %s\n\n", conf.devidstr);

+ print("mvfeat %#lux\n", mvfeatget());
l2print();
cacheprint();