Instruction Enhancement Programme (IEP) On Design Finishing for Chip Tape Out –SMDP-II 8 Oct 2011 to 10 Oct 2011

[chandrashekhar kukade]

Instruction Enhancement Programme  (IEP)  On Design Finishing for Chip Tape Out –SMDP-II

8 Oct 2011 to 10 Oct 2011

 

 

Indian Institute of Technology Bombay , Mumbai and Visvesvaraya National Institute of Technology, Nagpur is organizing 3 days workshop on “Instruction Enhancement Programme  (IEP)  On Design Finishing for Chip Tape Out ” from

8 Oct, 2011 to 10 Oct, 2011, at Department of Electronics V.N.I.T. Nagpur.

 

The main features of the workshop

·   Stress on integration and Tapeout flow.

·   Keynotes Lectures by professors from VNIT and IIT Bombay

·   Sharing experience of Tapeout based on IndiaChip 2010 program.

·   Demo of Chip Testing

Digital Flow :- Digital Flow will include RTL to GDSII flow for digital ASIC design using various industry standard tools. Main focus will be on physical design process steps covering aspects of I/O connections, power ring and timing verification. Integration of mixed module assuming a black box for analog logic.

Analog Flow :- Analog flow will cover schematic entry, simulation, layout and post-layout checks. Importing I/O ring, gds and analog modules and asic designs to demonstrate analog/asic integration, RF design and Layouts.  

Tapeout: Issues experienced during tapeouts, precautions for faster and successful tapeout, I/O sharing, power cut and considerations for testing and process parameter extraction.

 

 You are requested to send the nomination for the candidates associated with the SMDP-II for the above IEP. Details of the program are given below.

 

Rajendra M.Patrikar

Professor and Dean (Acd)

Department of Electronics Engineering

VNIT, Nagpur 440011

Email: Raje...@computer.org  rmpat...@ece.vnit.ac.in

Ph. No. 0712-2801336 (Office)  Fax : 0712-2223230

 

 

Tentative Program

 

Day 1 :-

1.Expert Lecture

2.Tutorial on Digital Flow(RTL to GDSII)

 

Day 2 :-

1.Expert Lecture

2.Tutorial on Analog Design Flow(Schematic to GDSII)

 

Day 3 :-

1.Expert Lecture

2.Tutorial on Integration of Digital & Analog design

3.Image Flow(Hardware Accelerator)

 FACULTY:

Lectures will be delivered by the faculty members of IIT Bombay and VNIT Nagpur.

LOCATION OF VNIT NAGPUR : Central Part of the country, Zero Mile location

 

ACCOMODATION:

Accommodation for the participants will be arranged in the Guest House, VNIT Nagpur, which has dining hall facilities.

 

HOW TO SEND NOMINATION?

 

Due to limited no. rooms in our guest house, maximum of 2 persons is allowed from each institute. Please send the personal details of the nominated candidate on or before 1^stOct 2011. Without the PIs permission no one will be consider as a participant.

 

Please send a reply mail by giving personal details along with the itinerary details of the nominated candidate from your institute.

 

 

IMPORTANT DATES:

 

Last Date of Registration /Nomination           : 1st October  2011

Course Date:                                                      8-10 October 2010

--
With Regards:-
Mr.Chadrashekahar T. Kukade
Research Assistant
VLSI Design & Research Lab.
Department of Electronics and Computer Science
VNIT, Nagpur 440011
email id: shekha...@ece.vnit.ac.in
contact no.(+91) 9823871147
                 (+91)712-2801045
http://ece.vnit.ac.in/MiNaG/mng.html

[Vishal Sharma]

Dear Sir,

I hope you can now recognize me. we met in IIT Kanpur during India Chip 2010 tapeout program.

Sir, Do you have any manual telling complete flow from schematic to GDS-II for digital design with cadence???

Please sir, share  it if something related you have...

Kindly give your skype id and phone number, if you can give me some of your time on phone call to help me...

Thank you.

Vishal Sharma

+91 9685551573

skype id: vishalfzd

--

Thanks & Regards,

VISHAL SHARMA

PhD Research Scholar,

Nanoscale Devices, VLSI Circuit & System Design Lab,

Electrical Engineering,

IIT Indore
+91 9685551573

[Iliyas malik]

hey dear 

Its very nice to see ur mail. I have to check. I will do it on weekend. 

Then i will let u know.

My no is 9560533077.

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With regards
Mohd Iliyas
Mo. No. 09465829393

[Vishal Sharma]

Thank you sir for the response.

Please do it as soon as possible.

Apart from that: where are you sir these days, and whats going on???

Thank you sir.

[Iliyas malik]

i m in delhi....whr r u?

n wat r u doing nowadays.....

[Vishal Sharma]

Sir,

I am at IIT Indore doing PhD from July, 2015.

Sir, You are still with BSNL or joined somewhere else???

[Ramesh Kini M]

Dear Mr. Sharma,

I do not have any notes. But recently there was an IEP at IISc Bangalore and they have put out lot of documentation on the following URL:

http://chips.ece.iisc.ernet.in/

There is a search box on that page. search for 'iep RTL to GDSII' or 'iep 2016 lab instructions'. You will see lot of informative material on these pages.

Hope this helps.

Regards,
Ramesh Kini. M.
==================================================
Ramesh Kini.M,

Associate Professor,
Dept. of Electronics and Communication Engg.,
National Institute of Technology Karnataka, Surathkal,
Srinivasnagar - P.O.,
INDIA - 575025
Ph: +91-824-2473506
==================================================

[Kamlesh Kumar]

Dear Vishal,

I left DEITY last year, now i started my buseness at Ghaziabad UP in
embedded design.

Regards,
Kamlesh
--------------------------

> Please sir, share  it if something related you have...

> Kindly give your skype id and phone number, if you can give me some of your
> time on phone call to help me...
> Thank you.

> Vishal Sharma+91 9685551573skype id: vishalfzd

> On Wed, Sep 21, 2011 at 12:25 PM, chandrashekhar kukade

> <shekha...@gmail.com> wrote:
>
> Instruction Enhancement Programme  (IEP)  On Design Finishing

> for Chip Tape Out –SMDP-II
> 8 Oct 2011 to 10 Oct 2011

>  
>  Indian Institute of Technology Bombay
> , Mumbai and Visvesvaraya National Institute of
> Technology, Nagpur is organizing 3 days workshop on “Instruction
> Enhancement Programme  (IEP)  On Design Finishing for Chip
> Tape Out ” from
> 8 Oct, 2011 to 10 Oct, 2011, at Department of Electronics V.N.I.T.
> Nagpur.
>  The main features of the workshop
> ·   Stress on integration and Tapeout flow.
> ·   Keynotes Lectures by professors
> from VNIT and IIT Bombay
> ·   Sharing experience of Tapeout based
> on IndiaChip 2010 program.
> ·   Demo of Chip Testing

> Digital Flow :- Digital Flow will

> include RTL to GDSII flow for
> digital ASIC design using various industry standard tools. Main

> focus will be on physical design process steps covering aspects of I/O
> connections, power ring and timing verification. Integration of mixed module
> assuming a black box for analog logic.

> Analog Flow :- Analog flow will cover schematic entry, simulation,
> layout and post-layout checks. Importing I/O ring, gds and analog
> modules and asic designs to demonstrate
> analog/asic integration, RF design and Layouts.  
> Tapeout: Issues experienced during tapeouts, precautions for
> faster and successful tapeout, I/O sharing, power cut and

> considerations for testing and process parameter extraction.

>  
>  You are requested to send the nomination for the candidates associated
> with the SMDP-II for the above IEP. Details of the program are
> given below.
>  Rajendra M.Patrikar
> Professor and Dean (Acd)Department of Electronics Engineering
> VNIT, Nagpur 440011
> Email: Raje...@computer.org  rmpat...@ece.vnit.ac.in
> Ph. No. 0712-2801336 (Office)  Fax : 0712-2223230
>   
> Tentative Program 
> Day 1 :-1.Expert Lecture
> 2.Tutorial on Digital Flow(RTL to GDSII)
>  Day 2 :-
> 1.Expert Lecture
> 2.Tutorial on Analog Design Flow(Schematic to GDSII)
>  Day 3 :-
> 1.Expert Lecture2.Tutorial on Integration of Digital & Analog design
> 3.Image Flow(Hardware Accelerator)
>  FACULTY:
> Lectures will be delivered by the faculty members of IIT Bombay
> and VNIT Nagpur.
> LOCATION OF VNIT NAGPUR : Central Part of the country, Zero Mile
> location 

> ACCOMODATION:
> Accommodation for the participants will be arranged in the Guest

> House, VNIT Nagpur, which has dining hall facilities.
>  HOW TO SEND NOMINATION?
>  Due to limited no. rooms in our guest house, maximum of 2 persons is

> allowed from each institute. Please send the personal details of the
> nominated candidate on or before 1stOct 2011. Without

> the PIs permission no one will be consider as a participant.
>  

> Please send a reply mail by giving personal details along with the itinerary
> details of the nominated candidate from your institute.

>   
> IMPORTANT DATES: 
> Last Date of Registration
> /Nomination           :
> 1st October  2011
> Course
> Date:                                                    
>  8-10 October 2010

>
>
>
>
>
>
> --
> With Regards:-
> Mr.Chadrashekahar T. Kukade
> Research Assistant

> VLSI Design & Research Lab.

> Department of Electronics and Computer Science
> VNIT, Nagpur 440011
> email id: shekha...@ece.vnit.ac.in
>
> contact no.(+91) 9823871147

>                 
> (+91)712-2801045
> http://ece.vnit.ac.in/MiNaG/mng.html
>
>
>
>
> --
> Thanks & Regards,
>
> VISHAL SHARMAPhD Research Scholar,Nanoscale Devices, VLSI Circuit &
> System Design Lab,Electrical Engineering,IIT Indore

[Vishal Sharma]

Thank you sir for the information.

Thanks & regards,

Vishal Sharma

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