Regarding the connection of SCL 180nm I/O Pads and power pads

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Vishal Sharma

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Nov 9, 2017, 3:14:02 AM11/9/17

to deep shekhar, mit...@cadence.com, tanmay dubey, Chandra Shekhar Gautam, pinal engineer, anil rawat, npi...@cadence.com, indi...@googlegroups.com, Iliyas malik, chandrashekhar kukade, anand kumar, naveen bishnoi, Pankaj Kumar, sunny sharma, ChArAnPrEeT SiNgH, manish tikyani, manish jaiswal, swapne...@gmail.com, akshay...@gmail.com, a.goy...@gmail.com

Hi all,

This is Vishal Sharma from IIT Indore.

Has anyone completed the design for tapeout using SCL 180nm digital IO pads. I am not able to understand exactly which pads are to be chosen for the digital I/Os of 1.8V and for the power pads (VDD and Gnd).

Moreover, what is the strategy to simulate the design using these pads, as symbol views are not available for pads, while the cadence ADE simulation needs it.

Thanks in advance.

Thanks & Regards,

VISHAL SHARMA

PhD Research Scholar,

Nanoscale Devices, VLSI Circuit & System Design Lab,

Electrical Engineering,

IIT Indore
+91 9685551573

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