Critical: Help required in Memory Array Circuit simulation using Cadence

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Vishal Sharma

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Mar 18, 2017, 5:45:34 AM3/18/17
to d.she...@gmail.com, harsh...@iiti.ac.in, mit...@cadence.com, dubey....@gmail.com, cs.g...@gmail.com, pinale...@gmail.com, anil rawat, npi...@cadence.com, indi...@googlegroups.com, mohdil...@gmail.com, chandrashekhar kukade, anand kumar, naveen bishnoi, Pankaj Kumar, sunny sharma, ChArAnPrEeT SiNgH, manish tikyani, manish jaiswal, ritesh patel, Mithun Mukherjee

Respected all,

I am looking for your valuable help and suggestions required to simulate the memory array's circuit using Cadence.


Kindly let me know how to verify the functionality of a memory array through simulation. 

Is it transient analysis, or any other kind of simulation engine is there to check the functionality of the complete array?

If anyone of you are aware of memory functionality test through simulation, then please let me know.

Iliyas Sir:  I am specially expecting some help from your end.


Thanks,
Vishal Sharma

--
Thanks & Regards,

VISHAL SHARMA
PhD Research Scholar,
Nanoscale Devices, VLSI Circuit & System Design Lab,
Electrical Engineering,
IIT Indore
+91 9685551573

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