LEF generation of analog block & Steps for SOC encounter for Aanalog blocks

[VNIT]

Hi Savi,

Follow the steps given in attached user guide.

--
With regards,

VLSI Design and Research Lab,
VNIT, Nagpur.
http://ece.vnit.ac.in/vlsi/VLSI_LAB/VDRL.html

On Sun, Jan 3, 2010 at 5:43 PM, savi <savithas...@gmail.com> wrote:

Hi all,

Thank you. I could get through synthesis step of the ANALOGESD.

For generating the ABSTRACT for the analog desgin we have done the
following steps:

1) First, we attached the techfile uploaded in the google groups to
our library.
2) In the layout, we changed the pins from M1_CAD_TT to M1_T  and so
on.
3) While doing the Abstract -> create abstract step we got resolution
problem i.e. the dialog box was going beyond the screen. So we
proceeded
   with GUI mode off. The log file obtained from the above step is
attached. (abstract.log). Then LEF has been also created.
4) For the purpose of importing this LEF into SOC Encounter we have
replaced ME1,ME2,... to metal1, metal2 and so on respectively.
5) The Design -> Import Design step is completed without any errors
but we don't get the analog block. The log file obtained from the same
is
   attached. (encounter.log)

Thanks in advance

With regards
savitha
M.Tech(VLSI)
NITK,Surathkal