Revised Buffer schematic and Symbol
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VNIT
Dec 17, 2009, 8:44:38 PM12/17/09
to indi...@googlegroups.com, rkh...@sgsits.ac.in, saurabh srivastava, Gaurav Konar, Naveen Suda
Dear All,
As discussed in the integrator's meeting and on indiachip. We have designed a 600uA total current buffer capable of driving 8Kohm(minimum and to ground) and CL = 50pF. It is a two stage opam in unity gain configuration with Ac gain of -14mdB and Maximum linear frequency of 1MHz. the Maximum peak to peak output voltage is 0.9V and common mode voltage is 0.9V using 1.8V Vdd. I have attached the schematic and symbol. We are currently doing its layout. We could not send it earlier as we were testing it. We are planning to use an external IC to connect the pin output(from this buffer) to a 50ohm load of a spectrum analyser. So circuits with sufficient current drive may not require this.
--
With regards,
VLSI Design and Research Lab,
VNIT, Nagpur.
http://ece.vnit.ac.in/vlsi/VLSI_LAB/VDRL.html
As discussed in the integrator's meeting and on indiachip. We have designed a 600uA total current buffer capable of driving 8Kohm(minimum and to ground) and CL = 50pF. It is a two stage opam in unity gain configuration with Ac gain of -14mdB and Maximum linear frequency of 1MHz. the Maximum peak to peak output voltage is 0.9V and common mode voltage is 0.9V using 1.8V Vdd. I have attached the schematic and symbol. We are currently doing its layout. We could not send it earlier as we were testing it. We are planning to use an external IC to connect the pin output(from this buffer) to a 50ohm load of a spectrum analyser. So circuits with sufficient current drive may not require this.
--
With regards,
VLSI Design and Research Lab,
VNIT, Nagpur.
http://ece.vnit.ac.in/vlsi/VLSI_LAB/VDRL.html
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